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  ? 2000 motorola, inc. all rights reserved. revision 0 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" para meters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's tec hnical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authoriz ed for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any othe r application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufac ture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. powerpc ? mpc823e reference manual the microprocessor for mobile computing
trademarks quicc ? is a registered trademark of motorola, inc. powerpc ? is a registered trademark of ibm corporation and is used by motorola under license from ibm. i 2 c ? is a registered tradmark of philips corporation. appletalk ? is a trademark of apple computer, inc. all other trademarks are the property of their respective owners. acknowledgments the mpc823e support team would like to thank the following people for their contribution to the success of the mpc823e: art miller, cw clark, ken edwards, kevin owen, ray burgess, tom gunter, john round, mike shoemake, james wilson, chris lines, ricardo berger, yehuda rudin, yair liebman, udi barel, the rest of the israel design team, stu werbner, tiffany huling-broadous, john dailey, lan nguyen, richard hendricks, darcy volden, trish sierer, arnaldo cruz, danny nguyen, myle buchanan, joseph mayfield, rodolfo guillen, the rest of the product/test engineering team, brian mccalley, alan weiss, steve rosebaugh, jasmine hsiao, mike collier, john southard, joseph lee, pat carr, mark vandenbrink, the rest of the systems software team, yoichi kimura, yuzo kuramochi, tanamachi goro, fumihiko kondo, keiji momozaki, jean-paul davi, per-eric josefsson, rodney watt, axel streicher, pierre juste, gary segal, mark diperri, kurt miller, steve shoap, rob wackerman, rick heider, gary wilson, thomas yeh, bill durrenberger, dave hyder, the rest of the field applications engineering/sales support team, pamela mitchell, nina friedman, the rest of the technical information center support team, dan malek, jim belesiu, clark liang, ronny svensson, mark wagner, bulent egilmez, kurt fuqua, robert applebaum, nick vaccaro, weifu shi, roozbeh ghorishi, robert ritchey, brad scott, dan malek, the rest of our customers, the gang at comp.sys.powerpc.tech and linuxppc-embedded, and to many others.
motorola mpc823e reference manual i table of contents paragraph page number title number section 1 introduction 1.1 features ................................................................................................1-1 1.2 architecture ...........................................................................................1-6 1.2.1 the embedded powerpc core ..................................................1-8 1.2.2 the system interface unit ..........................................................1-8 1.2.3 the communication processor module .....................................1-9 1.2.4 the video/lcd controller ........................................................1-10 1.2.4.1 the video controller .....................................................1-10 1.2.4.2 the lcd controller .......................................................1-10 1.3 the pcmcia-ata controller ..............................................................1-10 1.4 power management ............................................................................1-11 1.5 system debug support .......................................................................1-11 1.6 applications .........................................................................................1-11 1.7 differences between mpc823 (rev b) and mpc823e .......................1-12 1.8 mpc823e glueless system design ....................................................1-12 section 2 external signals 2.1 the system bus signals .......................................................................2-2 section 3 memory map section 4 reset 4.1 types of reset ......................................................................................4-2 4.1.1 power-on reset .........................................................................4-2 4.1.2 external hard reset ...................................................................4-3 4.1.3 internal hard reset ....................................................................4-3 4.1.3.1 loss of lock ....................................................................4-3 4.1.3.2 software watchdog reset ..............................................4-3 4.1.3.3 checkstop reset ............................................................4-3 4.1.3.4 debug port hard reset ..................................................4-4 4.1.3.5 jtag reset ....................................................................4-4
table of contents (continued) paragraph page number title number ii mpc823e reference manual motorola 4.1.4 external soft reset .................................................................... 4-4 4.1.5 internal soft reset ..................................................................... 4-4 4.1.5.1 debug port soft reset .................................................... 4-4 4.2 reset status register ........................................................................... 4-5 4.3 how to configure reset ........................................................................ 4-7 4.3.1 hard reset ................................................................................. 4-7 4.3.1.1 hard reset configuration word ................................... 4-10 4.3.2 soft reset ................................................................................ 4-12 section 5 clocks and power control 5.1 features ................................................................................................ 5-1 5.2 register model ...................................................................................... 5-3 5.2.1 system clock and reset control register ................................. 5-3 5.2.2 pll, low-power, and reset control register ........................... 5-7 5.3 the clock module ............................................................................... 5-10 5.3.1 on-chip oscillators and external clock input .......................... 5-12 5.3.2 system pll .............................................................................. 5-12 5.3.2.1 spll stability ............................................................... 5-13 5.3.3 the low-power clock divider .................................................. 5-14 5.3.4 internal clock signals .............................................................. 5-16 5.3.4.1 the general system clocks ......................................... 5-16 5.3.4.2 the baud rate generator clock .................................. 5-19 5.3.4.3 the synchronization clocks ......................................... 5-20 5.3.4.4 the lcd clocks ........................................................... 5-21 5.3.5 clock configuration .................................................................. 5-22 5.3.5.1 mode clock pins ........................................................... 5-22 5.3.5.2 the system phase-locked loop pins ......................... 5-23 5.4 power control ..................................................................................... 5-24 5.4.1 power rails .............................................................................. 5-24 5.4.2 keep-alive power ..................................................................... 5-25 5.4.2.1 power switching example ............................................ 5-26 5.4.2.2 register lock ................................................................ 5-27 5.5 low-power operation ......................................................................... 5-28 section 6 the powerpc core 6.1 features ................................................................................................ 6-1 6.2 basic structure of the core ................................................................... 6-2 6.2.1 instruction flow within the core ................................................ 6-2
table of contents (continued) paragraph page number title number motorola mpc823e reference manual iii 6.2.2 basic instruction pipeline ...........................................................6-4 6.3 sequencer unit .....................................................................................6-4 6.3.1 flow control ...............................................................................6-5 6.3.2 issuing instructions .....................................................................6-6 6.3.3 interrupts ....................................................................................6-7 6.3.4 implementing the precise exception model ...............................6-8 6.3.4.1 restartability after an interrupt .....................................6-10 6.3.5 processing an interrupt ............................................................6-11 6.3.6 serialization ..............................................................................6-12 6.3.6.1 latency .........................................................................6-12 6.3.7 the external interrupt ...............................................................6-13 6.3.7.1 latency .........................................................................6-13 6.3.8 interrupt ordering .....................................................................6-14 6.4 the register unit ................................................................................6-15 6.4.1 control registers ......................................................................6-16 6.4.1.1 physical location of special registers .........................6-19 6.4.1.2 powerpc standard control register bit assignment ....6-20 6.4.1.2.1 machine state register ....................................6-20 6.4.1.2.2 the condition register ....................................6-22 6.4.1.2.3 fixed-point exception cause register ............6-23 6.4.1.3 initializing the control registers ...................................6-24 6.4.1.3.1 system reset interrupt ....................................6-24 6.4.1.3.2 hard/soft reset ................................................6-24 6.5 the fixed-point unit ...........................................................................6-24 6.5.1 xer update in divide instructions ...........................................6-24 6.6 the load/store unit ............................................................................6-25 6.6.1 issuing load/store instructions ................................................6-26 6.6.2 serializing load/store instructions ...........................................6-27 6.6.3 instructions issued to the data cache .....................................6-27 6.6.4 issuing store instruction cycles ...............................................6-27 6.6.5 issuing nonspeculative load instructions ................................6-27 6.6.6 executing unaligned instructions .............................................6-28 6.6.7 little-endian mode support ......................................................6-29 6.6.8 atomic update primitives .........................................................6-29 6.6.9 instruction timing .....................................................................6-30 6.6.10 stalling storage control instructions ........................................6-30 6.6.11 accessing off-core special registers .....................................6-30 6.6.12 storage control instructions .....................................................6-31 6.6.13 exceptions ................................................................................6-31 6.6.13.1 dar, dsisr, and bar operation ................................6-31 section 7
table of contents (continued) paragraph page number title number iv mpc823e reference manual motorola powerpc architecture compliance 7.1 powerpc user instruction set architecture (book i) ............................ 7-1 7.1.1 computation modes ................................................................... 7-1 7.1.2 reserved fields ......................................................................... 7-1 7.1.3 classes of instructions ............................................................... 7-1 7.1.4 exceptions .................................................................................. 7-2 7.1.5 the branch processor ............................................................... 7-2 7.1.6 fetching instructions .................................................................. 7-2 7.1.7 branch instructions .................................................................... 7-2 7.1.7.1 invalid branch instruction forms .................................... 7-2 7.1.7.2 branch prediction ........................................................... 7-2 7.1.8 the fixed-point processor ......................................................... 7-2 7.1.8.1 move to/from system register instructions ................. 7-3 7.1.8.2 fixed-point arithmetic instructions ................................. 7-3 7.1.9 the load/store processor ......................................................... 7-3 7.1.9.1 fixed-point load with update and store with update instructions ................................................ 7-3 7.1.9.2 fixed-point load and store multiple instructions ........... 7-3 7.1.9.3 fixed-point load string instructions ............................... 7-3 7.1.9.4 storage synchronization instructions ............................. 7-4 7.1.9.5 optional instructions ....................................................... 7-4 7.1.9.6 little-endian byte ordering ............................................ 7-4 7.2 powerpc virtual environment architecture (book ii) ............................ 7-4 7.2.1 storage model ............................................................................ 7-4 7.2.1.1 memory coherence ........................................................ 7-4 7.2.1.2 atomic update primitives ............................................... 7-4 7.2.2 the effect of operand placement on performance .................. 7-5 7.2.3 the storage control instructions ............................................... 7-5 7.2.4 timebase ................................................................................... 7-6 7.3 powerpc operating environment architecture (book iii) ..................... 7-6 7.3.1 the branch processor ............................................................... 7-6 7.3.1.1 machine state register .................................................. 7-6 7.3.1.2 processor version register ............................................ 7-6 7.3.1.3 branch processors instructions ...................................... 7-6 7.3.2 the fixed-point processor ......................................................... 7-6 7.3.2.1 unsupported registers ................................................... 7-6 7.3.2.2 added registers ............................................................. 7-6 7.3.3 storage model ............................................................................ 7-6 7.3.3.1 address translation ........................................................ 7-6 7.3.4 reference and change bits ....................................................... 7-7 7.3.5 storage protection ..................................................................... 7-7 7.3.6 storage control instructions ....................................................... 7-7
table of contents (continued) paragraph page number title number motorola mpc823e reference manual v 7.3.6.1 data cache block invalidate (dcbi) .................................7-7 7.3.6.2 tlb invalidate entry (tlbie) .............................................7-7 7.3.6.3 tlb invalidate all (tlbia) ..................................................7-7 7.3.6.4 tlb synchronize (tlbsync) ..............................................7-7 7.3.7 interrupts ....................................................................................7-7 7.3.7.1 classes ...........................................................................7-7 7.3.7.2 processing ......................................................................7-8 7.3.7.3 definitions .......................................................................7-8 7.3.7.3.1 system reset interrupt ......................................7-9 7.3.7.3.2 machine check interrupt ....................................7-9 7.3.7.3.3 data storage interrupt ......................................7-10 7.3.7.3.4 instruction storage interrupt .............................7-10 7.3.7.3.5 alignment interrupt ...........................................7-10 7.3.7.3.6 program interrupt .............................................7-11 7.3.7.3.7 floating-point unavailable interrupt .................7-11 7.3.7.3.8 trace interrupt ..................................................7-11 7.3.7.3.9 floating-point assist interrupt ..........................7-11 7.3.7.3.10 implementation-dependent software emulation interrupt ............................................7-12 7.3.7.3.11 implementation-specific instruction tlb miss interrupt ....................................................7-12 7.3.7.3.12 implementation-specific instruction tlb error interrupt ....................................................7-13 7.3.7.3.13 implementation-specific data tlb miss interrupt .............................................................7-14 7.3.7.3.14 implementation-specific data tlb error interrupt .............................................................7-14 7.3.7.3.15 implementation-specific debug register .........7-15 7.3.7.4 partially executed instructions ......................................7-17 7.3.8 timer facilities .........................................................................7-17 7.3.9 optional facilities and instructions ...........................................7-17 section 8 instruction execution timing 8.1 instruction timing list ...........................................................................8-1 8.2 instruction execution timing examples ................................................8-4 8.2.1 data cache load .......................................................................8-4 8.2.2 writeback ...................................................................................8-5 8.2.2.1 writeback arbitration ......................................................8-5 8.2.2.2 private writeback bus load ...........................................8-6 8.2.3 fastest external load (data cache miss) ..................................8-7
table of contents (continued) paragraph page number title number vi mpc823e reference manual motorola 8.2.4 a full history buffer ................................................................... 8-8 8.2.5 branch folding ........................................................................... 8-9 8.2.6 branch prediction ..................................................................... 8-10 section 9 instruction cache 9.1 features ................................................................................................ 9-1 9.2 programming the instruction cache ..................................................... 9-4 9.2.1 instruction cache control and status register .......................... 9-5 9.2.2 instruction cache address register ........................................... 9-6 9.2.3 instruction cache data port register ......................................... 9-7 9.3 instruction cache operation ................................................................. 9-7 9.3.1 instruction cache hit .................................................................. 9-7 9.3.2 instruction cache miss ............................................................... 9-8 9.3.3 instruction fetch on a predicted path ....................................... 9-8 9.4 instruction cache commands ............................................................... 9-8 9.4.1 invalidating the instruction cache .............................................. 9-9 9.4.2 loading and locking the instruction cache ............................. 9-10 9.4.3 unlocking a line ...................................................................... 9-10 9.4.4 unlocking the entire instruction cache .................................... 9-11 9.4.5 inhibiting the instruction cache ................................................ 9-11 9.4.6 instruction cache read ............................................................ 9-12 9.4.7 instruction cache write ............................................................ 9-14 9.5 restrictions ......................................................................................... 9-14 9.6 instruction cache coherency .............................................................. 9-14 9.7 updating code and memory region attributes .................................. 9-14 9.8 reset sequence ................................................................................. 9-14 9.9 debug support .................................................................................... 9-15 9.9.1 fetching instructions from the development port .................. 9-15 section 10 data cache 10.1 features .............................................................................................. 10-1 10.2 organization of the data cache .......................................................... 10-2 10.3 programming the data cache ............................................................ 10-3 10.3.1 powerpc architecture instructions .......................................... 10-3 10.3.1.1 powerpc user instruction set architecture (book i) ..... 10-3 10.3.1.2 powerpc virtual environment architecture (book ii) .... 10-4 10.3.1.3 powerpc operating environment architecture (book iii) ....................................................................... 10-4
table of contents (continued) paragraph page number title number motorola mpc823e reference manual vii 10.3.2 implementation-specific operations ........................................10-4 10.3.3 special registers of the data cache .......................................10-4 10.3.3.1 data cache control and status register ......................10-5 10.3.3.2 data cache address register ......................................10-7 10.3.3.3 reading the cache structures ......................................10-7 10.4 operating the data cache ................................................................10-10 10.4.1 data cache read ...................................................................10-10 10.4.2 data cache write ...................................................................10-10 10.4.2.1 copyback mode ..........................................................10-11 10.4.2.2 writethrough mode .....................................................10-12 10.4.3 data cache inhibited accesses .............................................10-12 10.4.4 data cache freeze ................................................................10-12 10.4.5 data cache coherency ..........................................................10-13 10.5 data cache commands ....................................................................10-13 10.5.1 flushing and invalidating the cache ......................................10-13 10.5.2 enabling and disabling the cache .........................................10-13 10.5.3 locking and unlocking the cache ..........................................10-13 10.5.4 data cache instructions .........................................................10-14 10.5.4.1 dcbi, dcbst, dcbf and dcbz instructions ......................10-14 10.5.4.2 touch ..........................................................................10-14 10.5.4.3 storage synchronization/reservation ........................10-14 10.5.5 data cache read ...................................................................10-14 section 11 memory management unit 11.1 features ..............................................................................................11-1 11.2 address translation ............................................................................11-2 11.2.1 translation lookaside buffer operation ...................................11-2 11.3 protection ............................................................................................11-3 11.4 storage control ...................................................................................11-4 11.5 translation table structure .................................................................11-5 11.5.1 level one descriptor ................................................................11-9 11.5.2 level two descriptor ..............................................................11-10 11.6 programming the memory management unit ...................................11-15 11.6.1 control registers ....................................................................11-16 11.6.1.1 mmu instruction control register ...............................11-16 11.6.1.2 mmu data control register ........................................11-17 11.6.1.3 mmu current address space id register ..................11-18 11.6.1.4 mmu instruction effective page number register .....11-19 11.6.1.5 mmu data effective page number register ..............11-20 11.6.1.6 mmu instruction real page number register ............11-21
table of contents (continued) paragraph page number title number viii mpc823e reference manual motorola 11.6.1.7 mmu data real page number register .................... 11-26 11.6.1.8 mmu instruction access protection register ............. 11-31 11.6.1.9 mmu data access protection register ...................... 11-32 11.6.1.10 mmu instruction tablewalk control register ............. 11-33 11.6.1.11 mmu data tablewalk control register ...................... 11-34 11.6.1.12 mmu tablewalk base register .................................. 11-36 11.6.1.13 mmu tablewalk special register ............................... 11-37 11.6.2 mmu data content-addressable registers ........................... 11-37 11.6.2.1 mmu data cam entry read register ........................ 11-38 11.6.2.2 mmu data ram entry read register 0 ..................... 11-39 11.6.2.3 mmu data ram entry read register 1 ..................... 11-41 11.6.3 mmu instruction content-addressable registers .................. 11-43 11.6.3.1 mmu instruction cam entry read register ............... 11-43 11.6.3.2 mmu instruction ram entry read register 0 ............ 11-45 11.6.3.3 mmu instruction ram entry read register 1 ............ 11-46 11.7 interrupts ........................................................................................... 11-47 11.7.1 implementation-specific instruction tlb miss ....................... 11-47 11.7.2 implementation-specific data tlb miss ................................ 11-47 11.7.3 implementation-specific instruction tlb error ....................... 11-48 11.7.4 implementation-specific data tlb error ................................ 11-48 11.8 manipulating the translation lookaside buffer ................................. 11-49 11.8.1 reloading the translation lookaside buffer .......................... 11-49 11.8.1.1 translation reload examples ..................................... 11-50 11.8.2 controlling the tlb replacement counter ............................ 11-51 11.8.3 invalidating the translation lookaside buffer ........................ 11-51 11.8.4 loading the reserved tlb entries ........................................ 11-51 11.9 requirements for accessing the memory management unit control registers .............................................................................. 11-52 section 12 system interface unit 12.1 features .............................................................................................. 12-2 12.2 system configuration and protection ................................................. 12-2 12.3 interrupt configuration ........................................................................ 12-5 12.3.1 the interrupt structure ............................................................. 12-5 12.3.2 priority of the interrupt sources ............................................... 12-6 12.3.3 programming the interrupt controller ....................................... 12-7 12.3.3.1 siu interrupt pending register ..................................... 12-7 12.3.3.2 siu interrupt mask register ......................................... 12-8 12.3.3.3 siu interrupt edge/level register ................................ 12-9 12.3.3.4 siu interrupt vector register ..................................... 12-10
table of contents (continued) paragraph page number title number motorola mpc823e reference manual ix 12.4 the bus monitor ................................................................................12-11 12.5 the powerpc decrementer ..............................................................12-12 12.5.1 decrementer register ............................................................12-13 12.6 the powerpc timebase ...................................................................12-14 12.6.1 timebase register .................................................................12-14 12.6.2 timebase reference registers ..............................................12-15 12.6.3 timebase status and control register ..................................12-16 12.7 the real-time clock ........................................................................12-17 12.7.1 real-time clock status and control register ........................12-18 12.7.2 real-time clock register ......................................................12-19 12.7.3 real-time clock alarm seconds register .............................12-20 12.7.4 real-time clock alarm register ............................................12-21 12.8 the periodic interrupt timer .............................................................12-22 12.8.1 periodic interrupt status and control register .......................12-23 12.8.2 periodic interrupt timer count register .................................12-24 12.8.3 periodic interrupt timer register ...........................................12-25 12.9 the software watchdog timer .........................................................12-26 12.9.1 software service register ......................................................12-27 12.10 freeze operation ..............................................................................12-28 12.10.1 low-power stop operation ....................................................12-28 12.11 multiplexing the system interface unit pins ......................................12-29 12.12 programming the system interface unit ...........................................12-30 12.12.1 system configuration and protection registers .....................12-30 12.12.1.1 siu module configuration register ............................12-30 12.12.1.2 internal memory map register ...................................12-34 12.12.1.3 system protection control register ............................12-35 12.12.1.4 transfer error status register ....................................12-36 section 13 external bus interface 13.1 features ..............................................................................................13-1 13.2 transfer signals ..................................................................................13-1 13.2.1 control signals .........................................................................13-3 13.3 bus signal descriptions ......................................................................13-4 13.4 bus interface operation ......................................................................13-7 13.4.1 basic transfers ........................................................................13-8 13.4.2 single beat transfers ...............................................................13-8 13.4.2.1 single beat read flow .................................................13-9 13.4.2.2 single beat write flow ...............................................13-12 13.4.3 burst transfers .......................................................................13-16 13.4.4 the burst mechanism ............................................................13-16
table of contents (continued) paragraph page number title number x mpc823e reference manual motorola 13.4.5 transfer alignment and packaging ........................................ 13-25 13.4.6 arbitration phase-related signals ......................................... 13-27 13.4.6.1 bus request signal .................................................... 13-28 13.4.6.2 bus grant signal ........................................................ 13-29 13.4.6.3 bus busy signal ......................................................... 13-29 13.4.7 address transfer phase-related signals .............................. 13-31 13.4.7.1 transfer start signal ................................................... 13-31 13.4.7.2 address bus ............................................................... 13-32 13.4.7.3 transfer attributes ...................................................... 13-32 13.4.7.3.1 read/write signal .......................................... 13-32 13.4.7.3.2 burst signal .................................................... 13-32 13.4.7.3.3 transfer size signal ....................................... 13-33 13.4.7.3.4 address space attributes .............................. 13-33 13.4.7.3.5 special transfer start signal ......................... 13-33 13.4.7.3.6 burst data in progress signal ........................ 13-36 13.4.8 data transfer phase-related signals .................................... 13-36 13.4.8.1 data signal ................................................................. 13-36 13.4.9 termination phase-related signals ....................................... 13-36 13.4.9.1 transfer acknowledge signal ..................................... 13-36 13.4.9.2 burst inhibit signal ...................................................... 13-36 13.4.9.3 transfer error acknowledge signal ............................ 13-36 13.4.9.4 protocol for termination signals ................................ 13-37 13.4.10 storage reservation protocol ................................................ 13-38 13.4.11 exception control cycles ....................................................... 13-41 13.4.11.1 retry signal ............................................................ 13-42 section 14 endian modes 14.1 little-endian features ......................................................................... 14-3 14.2 big-endian system features .............................................................. 14-5 14.3 powerpc little-endian system features ............................................ 14-5 14.4 setting the endian mode of operation .............................................. 14-5 section 15 memory controller 15.1 features .............................................................................................. 15-1 15.2 architecture ......................................................................................... 15-4 15.3 register model .................................................................................... 15-7 15.3.1 register descriptions ............................................................... 15-9 15.3.1.1 base registers ............................................................. 15-9
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xi 15.3.1.2 option registers .........................................................15-11 15.3.1.3 memory status register .............................................15-15 15.3.1.4 memory command register .......................................15-17 15.3.1.5 machine a mode register ..........................................15-19 15.3.1.6 machine b mode register ..........................................15-22 15.3.1.7 memory data register ................................................15-26 15.3.1.8 memory address register ..........................................15-26 15.3.1.9 memory periodic timer prescaler register ................15-27 15.4 the general-purpose chip-select machine .....................................15-27 15.4.1 configuration ..........................................................................15-27 15.4.1.1 programmable wait state configuration ....................15-34 15.4.1.2 extended hold time on read accesses ....................15-34 15.4.1.3 boot chip-select operation ........................................15-37 15.4.1.4 sram interface ..........................................................15-38 15.4.1.5 external asynchronous master support ......................15-38 15.5 user-programmable machines .........................................................15-41 15.5.1 requests ................................................................................15-42 15.5.1.1 internal/external memory access requests ...............15-43 15.5.1.2 memory periodic timer requests ..............................15-43 15.5.1.3 software requests .....................................................15-44 15.5.1.4 exception requests ....................................................15-44 15.5.2 programming the user-programmable machine ....................15-44 15.5.3 clock timing ...........................................................................15-45 15.5.4 the ram array .......................................................................15-49 15.5.4.1 the ram word ...........................................................15-50 15.5.4.1.1 ram word format .........................................15-50 15.5.4.2 ram word operation .................................................15-55 15.5.4.2.1 start addresses ..............................................15-55 15.5.4.2.2 chip-select signals ........................................15-56 15.5.4.2.3 byte-select signals ........................................15-57 15.5.4.2.4 general-purpose signals ...............................15-59 15.5.4.2.5 loop control ...................................................15-60 15.5.4.2.6 exception handling ........................................15-60 15.5.4.2.7 address multiplexing ......................................15-61 15.5.4.2.8 transfer acknowledge and data sample control ............................................................15-65 15.5.4.2.9 disable timer mechanism ..............................15-65 15.5.4.2.10 last word .......................................................15-65 15.5.5 the wait mechanism ..............................................................15-66 15.5.5.1 internal and external synchronous master .................15-66 15.5.5.2 external asynchronous master ...................................15-67 15.5.5.3 handling variable access time and slow devices ....15-68
table of contents (continued) paragraph page number title number xii mpc823e reference manual motorola 15.5.5.3.1 hierarchical bus interface example ............... 15-68 15.5.5.3.2 slow device interface example ..................... 15-68 15.6 external master support ................................................................... 15-69 15.6.1 external master examples ..................................................... 15-73 15.6.1.1 memory system interface examples .......................... 15-77 15.6.2 page mode dram interface example ................................... 15-77 15.6.3 page mode extended data-out dram interface example .... 15-89 section 16 communication processor module 16.1 features .............................................................................................. 16-1 16.2 the risc microcontroller .................................................................... 16-4 16.2.1 risc microcontroller features ................................................. 16-5 16.2.2 communication between the microcontroller and core ........... 16-6 16.2.3 communication between the microcontroller and peripherals ......................................................................... 16-6 16.2.4 executing microcode from ram or rom ................................ 16-7 16.2.5 risc configuration and control registers .............................. 16-7 16.2.6 risc microcontroller commands ............................................. 16-9 16.2.6.1 cpm command register .............................................. 16-9 16.2.6.2 command definitions ................................................. 16-11 16.2.6.2.1 cpm command register example ................ 16-13 16.2.6.3 dual-port ram ........................................................... 16-13 16.2.6.3.1 buffer descriptors .......................................... 16-15 16.2.6.3.2 parameter ram ............................................. 16-15 16.2.6.4 the risc timer tables .............................................. 16-17 16.2.6.4.1 risc timer table parameter ram memory map ................................................... 16-18 16.2.6.4.2 risc timer table entries .............................. 16-22 16.2.6.4.3 the set timer command ........................... 16-22 16.2.6.4.4 pwm mode .................................................... 16-22 16.2.6.5 risc timer event register ........................................ 16-23 16.2.6.6 risc timer mask register ......................................... 16-23 16.2.6.7 risc timer initialization sequence example ............. 16-24 16.2.6.8 risc timer interrupt handling example .................... 16-25 16.2.6.9 risc timer table algorithm ....................................... 16-25 16.2.6.10 using the timers to track microcontroller loading ..... 16-25 16.3 digital signal processing .................................................................. 16-26 16.3.1 features ................................................................................. 16-26 16.3.2 dsp operation ....................................................................... 16-26 16.3.2.1 hardware .................................................................... 16-27
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xiii 16.3.2.2 software ......................................................................16-27 16.3.2.3 firmware .....................................................................16-27 16.3.3 programming the dsp functions ...........................................16-27 16.3.3.1 data representation ...................................................16-28 16.3.3.2 modulo addressing .....................................................16-29 16.3.3.2.1 dsp function descriptors ..............................16-29 16.3.3.2.2 dsp parameter ram memory map ...............16-30 16.3.3.2.3 dsp commands ............................................16-32 16.3.3.3 dsp event register ....................................................16-33 16.3.3.4 dsp mask register ....................................................16-34 16.3.3.5 dsp implementation ...................................................16-35 16.3.3.5.1 dsp programming example (core only) .......16-36 16.3.3.5.2 dsp programming example (core and cpm) ..............................................16-37 16.3.4 dsp on-chip library functions .............................................16-38 16.3.4.1 fir1Creal c, real x, and real y ..............................16-39 16.3.4.1.1 coefficients and sample data buffers ...........16-39 16.3.4.1.2 fir1 function descriptor ...............................16-40 16.3.4.1.3 fir1 parameter packet ..................................16-41 16.3.4.1.4 application example .......................................16-41 16.3.4.2 fir2Creal c, complex x, and complex y .................16-42 16.3.4.2.1 coefficients and sample data buffers ...........16-42 16.3.4.2.2 fir2 function descriptor ...............................16-43 16.3.4.2.3 fir2 parameter packet ..................................16-45 16.3.4.2.4 application example .......................................16-45 16.3.4.3 fir3Ccomplex c, complex x, and real/complex y .........................................................16-46 16.3.4.3.1 coefficients and sample data buffers ...........16-47 16.3.4.3.2 fir3 function descriptor ...............................16-47 16.3.4.3.3 fir3 parameter packet ..................................16-49 16.3.4.3.4 application example .......................................16-49 16.3.4.4 fir5Ccomplex c, complex x, and complex y ..........16-50 16.3.4.4.1 coefficients and sample data buffers ...........16-50 16.3.4.4.2 fir5 function descriptor ...............................16-51 16.3.4.4.3 fir5 parameter packet ..................................16-53 16.3.4.4.4 application example .......................................16-53 16.3.4.5 fir6Ccomplex c, real x, and complex y .................16-54 16.3.4.5.1 coefficients and sample data buffers ...........16-54 16.3.4.5.2 fir6 function descriptor ...............................16-55 16.3.4.5.3 fir6 parameter packet ..................................16-57 16.3.4.6 iirCreal c, real x, real y .........................................16-57
table of contents (continued) paragraph page number title number xiv mpc823e reference manual motorola 16.3.4.6.1 coefficients and sample data buffers ........... 16-57 16.3.4.6.2 iir function descriptor .................................. 16-58 16.3.4.6.3 iir parameter packet ..................................... 16-59 16.3.4.6.4 application example ...................................... 16-59 16.3.4.7 modCreal sin, real cos, complex x, and real/complex y .......................................................... 16-60 16.3.4.7.1 modulation table and sample data buffers .. 16-60 16.3.4.7.2 mod function descriptor .............................. 16-61 16.3.4.7.3 mod parameter packet ................................. 16-62 16.3.4.7.4 application example ...................................... 16-62 16.3.4.8 demodCreal sin; real cos, real x, and complex y .................................................................. 16-62 16.3.4.8.1 modulation table, sample data buffers, and agc constant ......................................... 16-63 16.3.4.8.2 demod function descriptor ......................... 16-63 16.3.4.8.3 demod parameter packet ............................ 16-64 16.3.4.8.4 application example ...................................... 16-65 16.3.4.9 lms1Ccomplex coefficients, complex samples, and real/complex scalar ........................................... 16-65 16.3.4.9.1 coefficients and sample data buffers ........... 16-65 16.3.4.9.2 lms1 function descriptor ............................. 16-66 16.3.4.9.3 lms1 parameter packet ................................ 16-67 16.3.4.9.4 application example ...................................... 16-67 16.3.4.10 lms2Ccomplex coefficients, complex samples, and real/complex scalar ........................................... 16-67 16.3.4.10.1 coefficients and sample data buffers ........... 16-68 16.3.4.10.2 lms2 function descriptor ............................. 16-68 16.3.4.10.3 lms2 parameter packet ................................ 16-70 16.3.4.10.4 application example ...................................... 16-70 16.3.4.11 waddCreal x and real y ......................................... 16-70 16.3.4.11.1 coefficients and sample data buffers ........... 16-71 16.3.4.11.2 wadd function descriptor ............................ 16-71 16.3.4.11.3 wadd parameter packet .............................. 16-72 16.3.4.11.4 application example ...................................... 16-73 16.3.4.12 the dsp execution times ......................................... 16-73 16.4 timers ............................................................................................... 16-75 16.4.1 features ................................................................................. 16-75 16.4.2 timer operation ..................................................................... 16-76 16.4.2.1 cascaded mode ......................................................... 16-77 16.4.2.2 timer global configuration register .......................... 16-78 16.4.2.3 timer mode registers ................................................ 16-79 16.4.2.4 timer reference registers ......................................... 16-80
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xv 16.4.2.5 timer capture registers .............................................16-81 16.4.2.6 timer counter registers .............................................16-81 16.4.2.7 timer event registers ................................................16-82 16.4.3 initializing the timers ..............................................................16-82 16.5 the sdma channels ........................................................................16-83 16.5.1 sdma bus arbitration and transfers .....................................16-85 16.5.2 the sdma registers ..............................................................16-86 16.5.2.1 sdma configuration register .....................................16-86 16.5.2.2 sdma status register ................................................16-88 16.5.2.3 sdma mask register .................................................16-89 16.5.2.4 sdma address register .............................................16-90 16.6 emulating idma ................................................................................16-90 16.6.1 features .................................................................................16-91 16.6.2 idma interface signals ...........................................................16-91 16.6.2.1 dreqx and sdackx .................................................16-91 16.6.3 idma operation ......................................................................16-91 16.6.3.1 autobuffer and buffer chaining ..................................16-92 16.6.3.2 idma parameter ram memory map ..........................16-93 16.6.3.3 idma status registers ...............................................16-95 16.6.3.4 idma mask registers .................................................16-96 16.6.3.5 idma buffer descriptors .............................................16-97 16.6.3.6 idma commands .....................................................16-101 16.6.3.7 starting idma ...........................................................16-102 16.6.3.8 requesting idma transfers .....................................16-102 16.6.3.9 level-sensitive mode ...............................................16-102 16.6.3.10 edge-sensitive mode ................................................16-102 16.6.3.11 idma operand transfers ..........................................16-103 16.6.3.11.1 transfer identification ...................................16-103 16.6.3.11.2 dual-address mode .....................................16-103 16.6.3.11.3 single-address mode (fly-by transfers) .....16-104 16.6.3.11.4 single-buffer burst fly-by mode ..................16-106 16.6.3.12 idma status registers .............................................16-110 16.6.3.13 idma mask registers ...............................................16-111 16.6.3.14 single-buffer timing .................................................16-111 16.6.3.15 download sequence ...............................................16-112 16.6.3.16 bus exceptions .........................................................16-113 16.7 the serial interface with time-slot assigner ..................................16-113 16.7.1 features ...............................................................................16-115 16.7.2 configuring the time-slot assigner ......................................16-115 16.7.3 enabling connections to the time-slot assigner .................16-118 16.7.4 serial interface ram operation ...........................................16-118 16.7.4.1 one multiplexed channel with static frames ...........16-119
table of contents (continued) paragraph page number title number xvi mpc823e reference manual motorola 16.7.4.2 one multiplexed channel with dynamic frames...... 16-120 16.7.4.3 two multiplexed channels with static frames.......... 16-121 16.7.4.4 two multiplexed channels with dynamic frames.... 16-122 16.7.4.5 programming the serial interface ram entries ........ 16-123 16.7.4.6 serial interface ram dynamic changes .................. 16-126 16.7.5 serial interface programming model .................................... 16-129 16.7.5.1 serial interface global mode register ...................... 16-129 16.7.5.2 serial interface mode register ................................. 16-130 16.7.5.3 serial interface clock route register ...................... 16-137 16.7.5.4 serial interface command register ......................... 16-140 16.7.5.5 serial interface status register ................................ 16-141 16.7.5.6 serial interface ram pointer register ...................... 16-142 16.7.5.6.1 sirp indication when rdm = 00 ................ 16-143 16.7.5.6.2 sirp indication when rdm = 01 ................ 16-144 16.7.5.6.3 sirp when rdm = 10 ................................. 16-144 16.7.5.6.4 sirp when rdm = 11 ................................. 16-144 16.7.6 idl interface operation ........................................................ 16-145 16.7.6.1 idl interface implementation ................................... 16-146 16.7.6.2 programming the idl interface ................................ 16-149 16.7.6.2.1 idl interface programming example ........... 16-150 16.7.7 gci interface operation ....................................................... 16-151 16.7.7.1 gci activation/deactivation procedure .................... 16-152 16.7.7.2 programming the gci interface ................................ 16-153 16.7.7.2.1 normal mode ............................................... 16-153 16.7.7.2.2 scit mode ................................................... 16-153 16.7.7.3 gci interface programming example ....................... 16-154 16.7.8 nonmultiplexed serial interface configuration ..................... 16-155 16.8 the baud rate generators ............................................................. 16-158 16.8.1 autobaud operation ............................................................. 16-160 16.8.2 baud rate generator configuration registers .................... 16-161 16.8.3 uart baud rate examples ................................................. 16-163 16.9 the serial communication controllers ........................................... 16-165 16.9.1 features ............................................................................... 16-167 16.9.2 the general sccx mode registers ..................................... 16-168 16.9.3 protocol-specific mode register .......................................... 16-178 16.9.4 data synchronization register ............................................. 16-179 16.9.5 transmit-on-demand register ............................................. 16-179 16.9.6 sccx buffer descriptor operation ....................................... 16-180 16.9.7 sccx parameter ram memory map ................................... 16-184 16.9.8 handling interrupts in the sccs .......................................... 16-189 16.9.8.1 interrupt handling in the scc event register .......... 16-189 16.9.8.2 interrupt handling in the scc mask register ........... 16-189
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xvii 16.9.8.3 interrupt handling in the scc status register .........16-189 16.9.9 initializing the serial communication controllers .................16-190 16.9.10 controlling sccx timing ......................................................16-191 16.9.10.1 synchronous protocols .............................................16-191 16.9.10.2 asynchronous protocols ...........................................16-195 16.9.11 digital phase-locked loop operation ..................................16-195 16.9.11.1 encoding and decoding data with a dpll ...............16-198 16.9.12 clock glitches ......................................................................16-199 16.9.13 dpll and serial infrared encoder/decoder .........................16-200 16.9.14 disabling the sccs on-the-fly ............................................16-201 16.9.14.1 disabling the entire sccx transmitter .....................16-201 16.9.14.2 disabling part of the sccx transmitter ....................16-201 16.9.14.3 disabling the entire sccx receiver .........................16-202 16.9.14.4 disabling part of the sccx receiver ........................16-202 16.9.14.5 switching protocols ..................................................16-202 16.9.15 the sccs in uart mode ....................................................16-203 16.9.15.1 features ....................................................................16-204 16.9.15.2 normal asynchronous mode ....................................16-205 16.9.15.3 synchronous mode ...................................................16-205 16.9.15.4 sccx uart parameter ram memory map .............16-206 16.9.15.5 programming the sccx in uart mode ...................16-208 16.9.15.6 sccx uart commands ..........................................16-209 16.9.15.7 recognizing addresses in sccx uart mode .........16-210 16.9.15.8 sccx uart control characters ..............................16-211 16.9.15.9 wake-up timer .........................................................16-213 16.9.15.10 break support ...........................................................16-213 16.9.15.11 sending a break .......................................................16-214 16.9.15.12 sending a preamble .................................................16-214 16.9.15.13 fractional stop bits ...................................................16-215 16.9.15.14 sccx uart controller errors ..................................16-217 16.9.15.15 sccx uart mode register .....................................16-220 16.9.15.16 sccx uart receive buffer descriptors ..................16-223 16.9.15.17 sccx uart transmit buffer descriptor ...................16-227 16.9.15.18 sccx uart event register .....................................16-230 16.9.15.19 sccx uart mask register ......................................16-232 16.9.15.20 sccx uart status register ....................................16-233 16.9.15.21 scc2 uart programming example ........................16-233 16.9.15.22 s-record programming example .............................16-235 16.9.16 the sccs in hdlc mode ....................................................16-236 16.9.16.1 features ....................................................................16-237 16.9.16.2 sccx hdlc channel frame transmission process .....................................................................16-237
table of contents (continued) paragraph page number title number xviii mpc823e reference manual motorola 16.9.16.3 sccx hdlc channel frame reception process ..... 16-238 16.9.16.4 sccx hdlc parameter ram memory map ............. 16-239 16.9.16.5 programming the sccs in hdlc mode ................... 16-241 16.9.16.6 sccx hdlc commands .......................................... 16-242 16.9.16.7 sccx hdlc controller errors .................................. 16-243 16.9.16.8 sccx hdlc mode register ..................................... 16-245 16.9.16.9 sccx hdlc receive buffer descriptor ................... 16-247 16.9.16.10 sccx hdlc transmit buffer descriptor .................. 16-251 16.9.16.11 sccx hdlc event register ..................................... 16-253 16.9.16.12 sccx hdlc mask register ..................................... 16-256 16.9.16.13 sccx hdlc status register .................................... 16-257 16.9.16.14 scc2 hdlc programming example #1 ................... 16-258 16.9.16.15 scc2 hdlc programming example #2 ................... 16-259 16.9.17 the hdlc bus controller .................................................... 16-260 16.9.17.1 features ................................................................... 16-262 16.9.17.2 accessing the hdlc bus ......................................... 16-263 16.9.17.2.1 improving performance ................................ 16-264 16.9.17.2.2 delaying rts mode ..................................... 16-265 16.9.17.2.3 using the time-slot assigner ...................... 16-266 16.9.17.3 hdlc bus memory map and programming ............. 16-267 16.9.17.3.1 hdlc bus controller programming example ........................................................ 16-267 16.9.18 the sccs in appletalk mode .............................................. 16-268 16.9.18.1 operating the localtalk bus .................................... 16-268 16.9.18.2 features ................................................................... 16-269 16.9.18.3 connecting to appletalk .......................................... 16-270 16.9.18.4 programming the sccs in appletalk mode ............. 16-271 16.9.18.5 sccx appletalk programming example .................. 16-273 16.9.19 the sccx in asynchronous hdlc mode ............................ 16-273 16.9.19.1 features ................................................................... 16-273 16.9.19.2 sccx async hdlc channel frame transmission process .............................................. 16-273 16.9.19.3 sccx async hdlc channel frame reception process ..................................................................... 16-274 16.9.19.4 transmitter transparency encoding ........................ 16-271 16.9.19.5 receiver transparency decoding ............................ 16-271 16.9.19.6 exceptions to rfc 1549 ........................................... 16-273 16.9.19.7 sccx async hdlc implementation ...................... 16-273 16.9.19.8 sccx async hdlc parameter ram memory map ............................................................. 16-274 16.9.19.9 configuring the sccx async hdlc parameters .... 16-276 16.9.19.10 sccx async hdlc commands ............................. 16-277
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xix 16.9.19.11 sccx async hdlc controller errors .....................16-278 16.9.19.12 programming the sccx async hdlc controller ....16-279 16.9.19.12.1 scc async hdlc mode register .............16-279 16.9.19.12.2 sccx async hdlc receive buffer descriptor ......................................................16-280 16.9.19.12.3 sccx async hdlc transmit buffer descriptor ......................................................16-284 16.9.19.12.4 sccx async hdlc event register ...........16-284 16.9.19.12.5 differences between hdlc and async hdlc ...............................................16-286 16.9.19.12.6 sccx async hdlc programming guide ...16-286 16.9.20 the scc2 in irda mode .......................................................16-287 16.9.20.1 low-speed irda protocol ..........................................16-288 16.9.20.2 middle-speed irda protocol .....................................16-289 16.9.20.3 high-speed irda protocol ........................................16-290 16.9.20.3.1 4ppm data encoding ...................................16-290 16.9.20.3.2 data link layer ............................................16-291 16.9.20.4 serial infrared interaction pulses ..............................16-293 16.9.20.5 programming model .................................................16-294 16.9.20.5.1 scc2 infrared mode register ......................16-294 16.9.20.5.2 scc2 infrared serial interaction pulse control register ............................................16-296 16.9.20.5.3 low-speed irda programming guide ..........16-297 16.9.20.5.4 middle-speed irda programming example ........................................................16-298 16.9.20.5.5 high-speed irda programming example .....16-300 16.9.21 the sccx in transparent mode ..........................................16-301 16.9.21.1 features ....................................................................16-302 16.9.21.2 sccx transparent channel frame transmission process .....................................................................16-302 16.9.21.3 sccx transparent channel frame reception process .....................................................................16-303 16.9.21.4 achieving synchronization in transparent mode ......16-303 16.9.21.4.1 inline synchronization pattern .....................16-304 16.9.21.4.2 external synchronization signals .................16-305 16.9.21.4.3 transparent synchronization example ........16-306 16.9.21.5 sccx transparent parameter ram memory map ....16-307 16.9.21.6 sccx transparent commands .................................16-307 16.9.21.7 sccx transparent controller errors .........................16-309 16.9.21.8 sccx transparent mode register ............................16-309 16.9.21.9 sccx transparent receive buffer descriptor ..........16-310 16.9.21.10 sccx transparent transmit buffer descriptor .........16-312
table of contents (continued) paragraph page number title number xx mpc823e reference manual motorola 16.9.21.11 sccx transparent event register ........................... 16-314 16.9.21.12 sccx transparent mask register ............................ 16-316 16.9.21.13 sccx transparent status register .......................... 16-316 16.9.21.14 scc2 transparent programming example .............. 16-317 16.9.22 the sccx in ethernet mode ................................................ 16-318 16.9.22.1 features ................................................................... 16-319 16.9.22.2 ethernet on the mpc823e ....................................... 16-320 16.9.22.3 understanding ethernet on the mpc823e ................ 16-321 16.9.22.4 connecting the mpc823e to the eest .................... 16-321 16.9.22.5 sccx ethernet channel frame transmission process ..................................................................... 16-323 16.9.22.6 sccx ethernet channel frame reception process ..................................................................... 16-324 16.9.22.7 sccx ethernet parameter ram memory map ......... 16-326 16.9.22.8 configuring the sccx ethernet parameters ............. 16-330 16.9.22.9 sccx ethernet commands ...................................... 16-330 16.9.22.10 sccx ethernet address recognition ....................... 16-332 16.9.22.11 hash table algorithm ............................................... 16-334 16.9.22.12 interpacket gap time ............................................... 16-335 16.9.22.13 handling collisions ................................................... 16-335 16.9.22.14 loopback and full-duplex operation ....................... 16-335 16.9.22.15 sccx ethernet controller errors .............................. 16-336 16.9.23 programming the sccx ethernet controller ........................ 16-337 16.9.23.1 sccx ethernet mode register ................................. 16-337 16.9.23.2 sccx ethernet receive buffer descriptor ................ 16-340 16.9.23.3 sccx ethernet transmit buffer descriptor ............... 16-343 16.9.23.4 sccx ethernet event register ................................. 16-346 16.9.23.5 sccx ethernet mask register .................................. 16-348 16.9.23.6 sccx ethernet status register ................................ 16-348 16.9.23.7 scc2 ethernet programming example .................... 16-348 16.10 universal serial bus controller ....................................................... 16-350 16.10.1 features ............................................................................... 16-352 16.10.2 controller limitations ........................................................... 16-352 16.10.3 usb controller pin functions and clocking ......................... 16-353 16.10.4 transmission and reception process .................................. 16-355 16.10.4.1 out token ............................................................... 16-356 16.10.4.2 in token ................................................................... 16-357 16.10.4.3 setup token ........................................................... 16-357 16.10.4.4 sof token ............................................................... 16-358 16.10.4.5 pre token ............................................................. 16-358 16.10.5 usb controller parameter ram memory map .................... 16-358 16.10.6 usb commands .................................................................. 16-363
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xxi 16.10.7 usb controller errors ...........................................................16-364 16.10.8 usb controller programming model ....................................16-365 16.10.8.1 usb mode register ..................................................16-365 16.10.8.2 usb receive buffer descriptor. ...............................16-366 16.10.8.3 usb transmit buffer descriptor. ..............................16-369 16.10.8.4 usb slave address register ....................................16-371 16.10.8.5 usb command register ..........................................16-372 16.10.8.6 usb endpoint configuration registers 0C3 ..............16-373 16.10.8.7 usb buffer descriptor ring ......................................16-374 16.10.8.8 usb event register ..................................................16-376 16.10.8.9 usb mask register ..................................................16-377 16.10.8.10 usb status register .................................................16-377 16.10.8.11 usb controller initialization example (function mode) ........................................................................16-378 16.10.9 using the usb controller as a host .....................................16-380 16.10.9.1 usb controller initialization example (host mode) ..............................................................16-380 16.11 the serial management controllers ...............................................16-382 16.11.1 features ...............................................................................16-384 16.11.2 general smcx mode register .............................................16-384 16.11.3 smcx buffer descriptor operation .......................................16-384 16.11.4 smc general parameter ram memory map .......................16-385 16.11.5 disabling the smcs on-the-fly ............................................16-390 16.11.5.1 disabling the entire smcx transmitter .....................16-391 16.11.5.2 disabling part of the smcx transmitter ...................16-391 16.11.5.3 disabling the entire smcx receiver .........................16-391 16.11.5.4 disabling part of the smcx receiver .......................16-392 16.11.5.5 switching protocols ..................................................16-392 16.11.6 the smcx in uart mode ....................................................16-392 16.11.6.1 features ....................................................................16-393 16.11.6.2 smcx uart channel transmission process ..........16-393 16.11.6.3 smcx uart channel reception process ................16-394 16.11.6.4 smcx uart parameter ram memory map ............16-394 16.11.6.5 programming the smcx uart controller ................16-395 16.11.6.6 smcx uart commands ..........................................16-396 16.11.6.7 sending a break .......................................................16-396 16.11.6.8 sending a preamble .................................................16-397 16.11.6.9 smcx uart controller errors ..................................16-397 16.11.6.10 smcx uart mode register .....................................16-398 16.11.6.11 smcx uart receive buffer descriptor ...................16-399 16.11.6.12 smcx uart transmit buffer descriptor ..................16-403 16.11.6.13 smcx uart event register .....................................16-405
table of contents (continued) paragraph page number title number xxii mpc823e reference manual motorola 16.11.6.14 smcx uart mask register ..................................... 16-407 16.11.6.15 smc1 uart controller programming example ....... 16-407 16.11.6.16 handling interrupts in the smcx uart controller .... 16-408 16.11.7 the smcx in transparent mode .......................................... 16-409 16.11.7.1 features ................................................................... 16-409 16.11.7.2 smcx transparent channel transmission process ..................................................................... 16-409 16.11.7.3 smcx transparent channel reception process....... 16-410 16.11.7.4 using the smsynx pin for synchronization ............. 16-411 16.11.7.5 using the time-slot assigner for synchronization .... 16-413 16.11.7.6 smcx transparent controller parameter ram memory map ............................................................. 16-415 16.11.7.7 smcx transparent commands ................................ 16-415 16.11.7.8 smcx transparent controller errors ........................ 16-416 16.11.7.9 smcx transparent mode register ........................... 16-416 16.11.7.10 smcx transparent receive buffer descriptor ......... 16-418 16.11.7.11 smcx transparent transmit buffer descriptor ........ 16-420 16.11.7.12 smcx transparent event register ........................... 16-422 16.11.7.13 smcx transparent mask register ........................... 16-423 16.11.7.14 smcx transparent nmsi programming example..... 16-423 16.11.7.15 smc1 transparent tsa programming example....... 16-424 16.11.7.16 handling interrupts in the smcx .............................. 16-425 16.11.8 the smcx in gci mode ....................................................... 16-425 16.11.8.0.1 smcx gci monitor channel transmission process ......................................................... 16-426 16.11.8.0.2 smcx gci monitor channel reception process ......................................................... 16-426 16.11.8.1 handling the smcx circuit interface channel .......... 16-426 16.11.8.1.1 smcx gci circuit interface channel transmission process ................................... 16-426 16.11.8.1.2 smcx gci circuit interface channel reception process ........................................ 16-426 16.11.8.2 smcx gci parameter ram memory map ................ 16-427 16.11.8.3 smcx gci commands ............................................. 16-430 16.11.8.4 smcx gci mode register ........................................ 16-431 16.11.8.5 smcx gci event register ........................................ 16-432 16.11.8.6 smcx gci mask register ........................................ 16-433 16.12 the serial peripheral interface ....................................................... 16-433 16.12.1 features ............................................................................... 16-434 16.12.2 spi clocking and pin functions ........................................... 16-435 16.12.3 the spi transmission and reception process .................... 16-436 16.12.3.1 multimaster operation .............................................. 16-437
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xxiii 16.12.3.2 spi parameter ram memory map ...........................16-438 16.12.3.3 spi commands .........................................................16-441 16.12.3.4 spi buffer descriptor ring ........................................16-442 16.12.4 programming the serial peripheral interface .......................16-443 16.12.4.1 spi mode register ....................................................16-443 16.12.4.1.1 spi examples with different len values.....16-445 16.12.4.1.2 spi receive buffer descriptor .....................16-447 16.12.4.1.3 spi transmit buffer descriptor ....................16-449 16.12.4.2 spi command register ............................................16-447 16.12.4.3 spi event register ...................................................16-452 16.12.4.4 spi mask register ....................................................16-453 16.12.5 spi master programming example ......................................16-453 16.12.6 spi slave programming example ........................................16-454 16.12.7 handling interrupts in the spi ..............................................16-455 16.13 the i 2 c controller ...........................................................................16-456 16.13.1 features ...............................................................................16-456 16.13.2 i 2 c controller clocking and pin functions ...........................16-457 16.13.3 i 2 c controller transmission and reception process ...........16-458 16.13.3.1 i 2 c master mode .......................................................16-459 16.13.3.1.1 master write .................................................16-459 16.13.3.1.2 master read .................................................16-460 16.13.3.1.3 i 2 c loopback configuration .........................16-461 16.13.3.2 i 2 c slave mode .........................................................16-465 16.13.3.2.1 write to master .............................................16-462 16.13.3.2.2 read from master ........................................16-462 16.13.4 i 2 c parameter ram memory map ........................................16-463 16.13.5 i 2 c commands .....................................................................16-466 16.13.6 the i 2 c buffer descriptor ring .............................................16-468 16.13.7 programming the i 2 c controller ...........................................16-468 16.13.7.1 i 2 c mode register ....................................................16-469 16.13.7.2 i 2 c receive buffer descriptor ...................................16-469 16.13.7.3 i 2 c transmit buffer descriptor ..................................16-471 16.13.7.4 i 2 c address register ................................................16-473 16.13.7.5 i 2 c baud rate generator register ...........................16-474 16.13.7.6 i 2 c command register .............................................16-474 16.13.7.7 i 2 c event register ....................................................16-475 16.13.7.8 i 2 c mask register .....................................................16-476 16.13.8 i 2 c controller initialization sequence ...................................16-476 16.14 the parallel i/o ports ......................................................................16-477 16.14.1 features ...............................................................................16-478 16.14.2 port a pin functionality ........................................................16-478 16.14.3 the port a registers ...........................................................16-480
table of contents (continued) paragraph page number title number xxiv mpc823e reference manual motorola 16.14.3.1 port a open-drain register ...................................... 16-480 16.14.3.2 port a data register ................................................. 16-480 16.14.3.3 port a data direction register ................................. 16-481 16.14.3.4 port a pin assignment register ............................... 16-481 16.14.4 port a example configurations ............................................ 16-482 16.14.5 port b pin functionality ........................................................ 16-484 16.14.6 the port b registers ............................................................ 16-485 16.14.6.1 port b open-drain register ...................................... 16-485 16.14.6.2 port b data register ................................................. 16-486 16.14.6.3 port b data direction register. ................................ 16-487 16.14.6.4 port b pin assignment register ............................... 16-488 16.14.7 port b configuration example .............................................. 16-489 16.14.8 port c pin functionality ........................................................ 16-494 16.14.9 port c registers ................................................................... 16-491 16.14.9.1 port c data register ................................................ 16-492 16.14.9.2 port c data direction register ................................. 16-492 16.14.9.3 port c pin assignment register ............................... 16-493 16.14.9.4 port c special options register ............................... 16-493 16.14.9.5 port c interrupt control register .............................. 16-495 16.14.10 port d pin functionality ........................................................ 16-496 16.14.11 port d registers ................................................................... 16-497 16.14.11.1 port d data register ................................................ 16-497 16.14.11.2 port d data direction register ................................. 16-497 16.14.11.3 port d pin assignment register. .............................. 16-498 16.15 the cpm interrupt controller .......................................................... 16-498 16.15.1 features ............................................................................... 16-500 16.15.2 cpm interrupt source priorities ........................................... 16-500 16.15.2.1 usb and sccx relative priority ............................... 16-501 16.15.2.2 highest priority interrupt ........................................... 16-501 16.15.2.3 nested interrupts ...................................................... 16-503 16.15.3 masking interrupt sources in the cpm ................................ 16-503 16.15.4 generating and calculating an interrupt vector ................... 16-504 16.15.5 programming the cpm interrupt controller .......................... 16-506 16.15.5.1 cpm interrupt configuration register ...................... 16-506 16.15.5.2 cpm interrupt pending register ............................... 16-508 16.15.5.3 cpm interrupt mask register ................................... 16-509 16.15.5.4 cpm interrupt in-service register ............................ 16-510 16.15.5.5 cpm interrupt vector register ................................. 16-511 16.15.6 interrupt handling examples ................................................ 16-511 16.15.6.1 pc6 interrupt handler example ................................ 16-511 16.15.6.2 usb interrupt handler example ............................... 16-512
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xxv section 17 pcmcia interface 17.1 features ..............................................................................................17-1 17.2 system configuration ..........................................................................17-1 17.3 pcmcia signals .................................................................................17-3 17.3.1 the pcmcia cycle control signals .........................................17-3 17.3.2 the pcmcia input port signals ...............................................17-5 17.3.3 the pcmcia output port signals ............................................17-6 17.3.4 other pcmcia signals .............................................................17-6 17.4 pcmcia operation .............................................................................17-7 17.4.1 memory-only cards .................................................................17-7 17.4.2 i/o cards ..................................................................................17-7 17.4.3 interrupts ..................................................................................17-8 17.4.4 power control ...........................................................................17-8 17.4.5 reset and three-state control ................................................17-8 17.4.6 dma .........................................................................................17-8 17.5 programming the pcmcia interface ...................................................17-9 17.5.1 pcmcia interface input pins register .....................................17-9 17.5.2 pcmcia interface status change register ...........................17-11 17.5.3 pcmcia interface enable register ........................................17-13 17.5.4 pcmcia interface general control register b ......................17-15 17.5.5 pcmcia base registers ........................................................17-16 17.5.6 pcmcia option registers ......................................................17-17 17.6 pcmcia controller timing examples ...............................................17-22 section 18 lcd controller 18.1 features ..............................................................................................18-1 18.1.1 lcd technology .......................................................................18-2 18.1.2 types of lcd interfaces ...........................................................18-3 18.1.2.1 passive lcd interface ..................................................18-4 18.1.2.2 active lcd interface .....................................................18-5 18.1.2.3 smart panel lcd interface ...........................................18-5 18.2 the mpc823e lcd controller ............................................................18-6 18.3 lcd controller operation ....................................................................18-8 18.3.1 fifo control .............................................................................18-9 18.3.2 pixel generation .....................................................................18-10 18.3.2.1 grayscale ....................................................................18-10 18.3.2.2 color ...........................................................................18-12 18.3.3 horizontal control ...................................................................18-13
table of contents (continued) paragraph page number title number xxvi mpc823e reference manual motorola 18.3.4 vertical control ....................................................................... 18-13 18.3.5 frame control ........................................................................ 18-13 18.3.6 dma control ........................................................................... 18-13 18.3.7 timing control ........................................................................ 18-14 18.3.8 contrast and brightness control ............................................ 18-14 18.3.9 the lcd interface .................................................................. 18-14 18.3.9.1 single-scan and dual-scan panels ........................... 18-15 18.3.9.2 passive interface ........................................................ 18-15 18.3.9.3 active interface ........................................................... 18-17 18.3.9.4 analog interface ......................................................... 18-19 18.3.10 system considerations .......................................................... 18-19 18.3.10.1 bus bandwidth ............................................................ 18-19 18.3.10.2 bus latency ................................................................ 18-20 18.4 register model .................................................................................. 18-21 18.4.1 lcd controller configuration register ................................... 18-21 18.4.2 lcd horizontal control register ............................................ 18-23 18.4.3 lcd vertical configuration register ...................................... 18-25 18.4.4 lcd frame buffer a start address register ......................... 18-27 18.4.5 lcd frame buffer b start address register ......................... 18-28 18.4.6 lcd status register .............................................................. 18-29 18.4.7 color ram operation modes ................................................. 18-30 18.4.7.1 one bit per pixel monochrome mode ........................ 18-30 18.4.7.2 two bits per pixel grayscale mode ........................... 18-32 18.4.7.3 four bits per pixel grayscale mode ........................... 18-33 18.4.7.4 passive four and eight bits per pixel color mode .... 18-35 18.4.7.5 active four and eight bits per pixel color mode ......... 18-36 18.4.8 lcd panel connection examples .......................................... 18-37 section 19 video controller 19.1 features .............................................................................................. 19-2 19.2 operation ............................................................................................ 19-2 19.2.1 the video controller clock ...................................................... 19-3 19.2.2 fifo and dma control ............................................................ 19-4 19.2.3 image sizes ............................................................................. 19-4 19.3 register model .................................................................................... 19-5 19.3.1 video controller configuration register ................................... 19-5 19.3.2 video status register .............................................................. 19-7 19.3.3 video command register ........................................................ 19-8 19.3.4 video background color buffer register ................................. 19-9 19.3.5 video frame configuration register (set 0) .......................... 19-10
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xxvii 19.3.6 video frame buffer a start address register (set 0) ............19-11 19.3.7 video frame buffer b start address register (set 0) ............19-12 19.3.8 video frame configuration register (set 1) ..........................19-13 19.3.9 video frame buffer a start address register (set 1) ............19-14 19.3.10 video frame buffer b start address register (set 1) ............19-15 19.4 video controller ram array ..............................................................19-16 19.4.1 video ram word format .......................................................19-17 19.5 programming examples ....................................................................19-19 19.5.1 ntsc example .......................................................................19-20 19.5.1.1 ntsc programming procedure example ...................19-22 19.5.2 pal example ..........................................................................19-24 19.5.2.1 pal programming procedure example ......................19-26 section 20 development capabilities and interface 20.1 features ..............................................................................................20-1 20.2 program flow tracking .......................................................................20-2 20.2.1 basic operation ........................................................................20-3 20.2.1.1 the internal hardware ..................................................20-3 20.2.1.1.1 special case queue flush information ...........20-5 20.2.1.1.2 program trace in debug mode ........................20-5 20.2.1.1.3 sequential instructions marked as indirect branch ...............................................................20-5 20.2.1.2 the external hardware .................................................20-5 20.2.1.2.1 back trace .......................................................20-6 20.2.1.2.2 window trace ..................................................20-6 20.2.1.2.3 synchronizing the trace window to the internal core events .........................................20-6 20.2.1.2.4 detecting the trace window start address ......20-7 20.2.1.2.5 detecting vsync assertion/negation .............20-7 20.2.1.2.6 detecting the trace window end address .......20-7 20.2.1.3 compression of cancelled instructions ........................20-8 20.2.2 controlling instruction fetch show cycles ...............................20-8 20.3 generating watchpoints and breakpoints ..........................................20-8 20.3.1 internal watchpoints and breakpoints ......................................20-9 20.3.1.1 restrictions .................................................................20-12 20.3.1.2 byte and half-word working modes ..........................20-12 20.3.1.3 context-dependent filter ............................................20-14 20.3.1.4 ignore first match option ...........................................20-15 20.3.1.5 generating compare types .......................................20-15 20.3.2 basic operation ......................................................................20-16
table of contents (continued) paragraph page number title number xxviii mpc823e reference manual motorola 20.3.2.1 instruction support ..................................................... 20-16 20.3.2.2 load/store support .................................................... 20-17 20.3.2.3 counter support ......................................................... 20-18 20.3.2.4 trap enable programming ......................................... 20-20 20.4 hardware development system interface ........................................ 20-20 20.4.1 trap enable mode .................................................................. 20-22 20.4.2 debug mode ........................................................................... 20-22 20.4.2.1 debug mode enable vs. debug mode disable ........... 20-24 20.4.2.2 entering debug mode ................................................. 20-24 20.4.2.3 checkstop state and debug mode ............................ 20-27 20.4.2.4 saving the machine state in debug mode ................. 20-28 20.4.2.5 running in debug mode ............................................. 20-28 20.4.2.6 exiting debug mode ................................................... 20-28 20.4.3 the development interface port ............................................ 20-29 20.4.3.1 development serial clock .......................................... 20-29 20.4.3.2 development serial data in ........................................ 20-29 20.4.3.3 development serial data out ..................................... 20-29 20.4.3.4 freeze ........................................................................ 20-30 20.4.3.5 development interface port registers ........................ 20-30 20.4.3.5.1 development interface port shift register ..... 20-30 20.4.3.5.2 trap enable control register ........................ 20-31 20.4.3.5.3 decoding the development interface port registers ......................................................... 20-31 20.4.3.6 development port serial communication ................... 20-31 20.4.3.6.1 clock mode selection .................................... 20-31 20.4.3.7 trap enable mode ...................................................... 20-32 20.4.3.8 debug mode ............................................................... 20-37 20.5 software monitor debugger .............................................................. 20-40 20.5.1 freeze indication (frz) ......................................................... 20-41 20.6 programming the development port registers ................................ 20-41 20.6.1 protecting the development port registers ........................... 20-41 20.6.2 development port registers .................................................. 20-42 20.6.2.1 comparator aCd value registers .............................. 20-42 20.6.2.2 comparator eCf value registers ............................... 20-43 20.6.2.3 comparator gCh value registers .............................. 20-44 20.6.2.4 breakpoint address register ...................................... 20-44 20.6.2.5 instruction support control register .......................... 20-45 20.6.2.6 load/store support comparators control register..... 20-48 20.6.2.7 load/store support and-or control register .......... 20-50 20.6.2.8 breakpoint counter a value and control register ...... 20-53 20.6.2.9 breakpoint counter b value and control register ...... 20-54 20.6.3 debug mode registers .......................................................... 20-55
table of contents (continued) paragraph page number title number motorola mpc823e reference manual xxix 20.6.3.1 interrupt cause register .............................................20-55 20.6.3.2 debug enable register ...............................................20-57 20.6.4 development port data register ............................................20-60 section 21 ieee 1149.1 test access port 21.1 the tap controller .............................................................................21-3 21.2 the boundary scan register ..............................................................21-4 21.3 the instruction register ....................................................................21-19 21.3.1 the external test instruction .................................................21-19 21.3.2 the sample/preload instruction ..............................................21-20 21.3.3 the bypass instruction ...........................................................21-20 21.3.4 the clamp instruction .............................................................21-20 21.3.5 the hi-z instruction .................................................................21-20 21.4 mpc823e restrictions ......................................................................21-21 section 22 dc electrical specifications 22.1 maximum ratings (gnd = 0v) ............................................................22-1 22.2 thermal characteristics ......................................................................22-2 22.3 power considerations .........................................................................22-2 22.4 dc electrical characteristics (vcc = 3.0 - 3.6 v) ...............................22-4 section 23 mechanical specifications and ordering information 23.1 ordering information ..........................................................................23-1 23.2 pin assignmentspbgatop view .................................................23-2 23.3 pbga package dimensions ...............................................................23-3 section 24 terminology appendix a serial communication performance a.1 channel combinations ......................................................................... a-2 a.2 example #1 .......................................................................................... a-4 a.3 example #2 .......................................................................................... a-4
table of contents (continued) paragraph page number title number xxx mpc823e reference manual motorola a.4 example #3 ...........................................................................................a-4 appendix b mpc823e instruction set b.1 instruction formats ..............................................................................b-1 b.2 split-field notation ................................................................................b-1 b.3 instruction fields ...................................................................................b-2 b.4 notations and conventions ...................................................................b-3 b.5 the mpc823e instruction set ...............................................................b-6
motorola mpc823e reference manual xxxi list of illustrations figure page number title number section 6 introduction 1-1. mpc823e block diagram .................................................................................1-7 1-2. mpc823e system configuration ....................................................................1-13 section 7 external signals 2-1. mpc823e signal pinout ...................................................................................2-1 section 4 reset 4-1. reset configuration basic scheme .................................................................4-7 4-2. reset configuration sampling scheme for short poreset assertion .........4-8 4-3. reset configuration sampling scheme for long poreset assertion ..........4-8 4-4. reset configuration sampling timing requirements ......................................4-9 section 5 clocks and power control 5-1. clock source and distribution ..........................................................................5-2 5-2. crystal oscillator ............................................................................................5-10 5-3. clock module diagram ...................................................................................5-11 5-4. spll block diagram ......................................................................................5-12 5-5. clock dividers ................................................................................................5-15 5-6. mpc823e clocks timing diagram .................................................................5-16 5-7. selecting the general system clock ..............................................................5-17 5-8. divided system clocks timing diagram ........................................................5-18 5-9. mpc823e clocks for division factor 2 .........................................................5-18 5-10. clkout divider ............................................................................................5-19 5-11. brgclk divider ............................................................................................5-19 5-12. syncclk divider ..........................................................................................5-20 5-13. lcdclk divider .............................................................................................5-21 5-14. lcd clock timing diagram ............................................................................5-21 5-15. mpc823e power rails and texp status ......................................................5-24 5-16. external power supply scheme .....................................................................5-26 5-17. register lock mechanism ..............................................................................5-28
list of illustrations (continued) figure page number title number xxxii mpc823e reference manual motorola 5-18. mpc823e low-power mode flowchart ......................................................... 5-29 section 6 the powerpc core 6-1. block diagram of the core ............................................................................... 6-3 6-2. instruction flow conceptual diagram .............................................................. 6-3 6-3. basic instruction pipeline timing diagram ...................................................... 6-4 6-4. sequencer data path ....................................................................................... 6-5 6-5. history buffer queue ....................................................................................... 6-9 6-6. load/store unit functional block diagram .................................................... 6-26 6-7. number of bus cycles needed for unaligned, single register fixed-point load/store instructions ............................................................... 6-28 6-8. number of bus cycles needed for string instruction execution .................. 6-30 section 8 intruction execution timing 8-1. example of a data cache load ....................................................................... 8-4 8-2. example of a writeback arbitration .................................................................. 8-5 8-3. another example of a writeback arbitration .................................................... 8-5 8-4. example of a private writeback bus load ....................................................... 8-6 8-5. example of an external load ........................................................................... 8-7 8-6. example of a full history buffer ...................................................................... 8-8 8-7. example of branch folding .............................................................................. 8-9 8-8. example of branch prediction ........................................................................ 8-10 section 9 instruction cache 9-1. instruction cache organization block diagram ............................................... 9-3 9-2. cache data path block diagram ..................................................................... 9-4 section 10 data cache 10-1. data cache organization ............................................................................... 10-2 10-2. cache data path block diagram ................................................................... 10-3 section 11 memory management unit 11-1. block diagram of effective-to-real address translation for 4k pages ........ 11-3
list of illustrations (continued) figure page number title number motorola mpc823e reference manual xxxiii 11-2. two level translation table when md_ctr(twam) = 1 ............................11-6 11-3. two level translation table when md_ctr(twam) = 0 ............................11-7 11-4. organization of the memory management unit registers ...........................11-15 section 12 system interface unit 12-1. system configuration and protection logic ...................................................12-4 12-2. mpc823e interrupt structure .........................................................................12-5 12-3. interrupt table handling example ................................................................12-11 12-4. real-time clock block diagram ..................................................................12-17 12-5. periodic interrupt timer block diagram .......................................................12-22 12-6. software watchdog timer service state diagram .......................................12-26 12-7. software watchdog timer block diagram ...................................................12-27 section 13 external bus interface 13-1. input sample window ....................................................................................13-2 13-2. mpc823e bus signals ...................................................................................13-3 13-3. basic flow diagram of a single beat read cycle .........................................13-9 13-4. single beat read cycleCbasic timingCzero wait states ............................13-10 13-5. single beat read cycleCbasic timingCone wait state ..............................13-11 13-6. basic flow diagram of a single beat write cycle .......................................13-12 13-7. single beat write cycleCbasic timingCzero wait states ............................13-13 13-8. single beat write cycle of one wait state ..................................................13-14 13-9. single beat, 32-bit data, write cycle from a 16-bit port size ....................13-15 13-10. basic flow diagram of a burst read cycle ................................................13-17 13-11. burst-read cycleC32-bit port sizeCzero wait state ...................................13-18 13-12. burst-read cycleC32-bit port sizeCone wait state ....................................13-19 13-13. burst-read cycleC32-bit port sizeCwait states between beats ................13-20 13-14. basic flow diagram of a burst write cycle .................................................13-21 13-15. burst-read cycleC16-bit port sizeCone wait state between beats ..........13-22 13-16. burst-write cycleC32-bit port sizeCzero wait states .................................13-23 13-17. burst-inhibit cycleC32-bit port size .............................................................13-24 13-18. internal operand representation .................................................................13-25 13-19. interface to different port size devices ......................................................13-26 13-20. bus arbitration flowchart .............................................................................13-28 13-21. basic bus busy connection .........................................................................13-29 13-22. bus arbitration timing diagram ...................................................................13-30 13-23. internal bus arbitration state machine .........................................................13-31 13-24. termination signals protocol basic connection ..........................................13-37
list of illustrations (continued) figure page number title number xxxiv mpc823e reference manual motorola 13-25. termination signals protocol timing diagram ............................................. 13-37 13-26. reservation on local bus ........................................................................... 13-39 13-27. reservation on multilevel bus hierarchy .................................................... 13-41 13-28. retry transfer timingCinternal arbiter ..................................................... 13-43 13-29. retry transfer timingCexternal arbiter .................................................... 13-44 13-30. retry on burst cycle ................................................................................... 13-45 section 14 endian modes 14-1. general mpc823e system diagram .............................................................. 14-2 section 15 memory controller 15-1. memory controller block diagram (single upm) ........................................... 15-3 15-2. memory controller machine selection ........................................................... 15-4 15-3. simple system configuration ......................................................................... 15-5 15-4. basic memory controller operation ............................................................... 15-7 15-5. gpcm memory device interface ................................................................. 15-29 15-6. gpcm memory device basic timing (acs = 00, csnt = 1, and trlx = 0) .................................................................................................... 15-30 15-7. gpcm peripheral device interface .............................................................. 15-31 15-8. gpcm peripheral device basic timing (acs = 10 or 11 and trlx = 0) .................................................................................................... 15-31 15-9. mpc823e gpcmCrelaxed timingCread access (acs = 10 or 11, scy = 1, and trlx = 1) .............................................................................. 15-32 15-10. mpc823e gpcmCrelaxed timingCwrite access (acs = 10 or 11, scy = 0, csnt = 0, and trlx = 1) ............................................................ 15-33 15-11. mpc823e gpcmCrelaxed timingCwrite access (acs = 10 or 11, scy = 0, csnt = 1, and trlx = 1) ............................................................ 15-33 15-12. mpc823e gpcmCrelaxed timingCwrite access (acs = 00, scy = 0, csnt = 1, and trlx = 1) ........................................................................... 15-34 15-13. gpcm read followed by write (ehtr = 0) ............................................... 15-35 15-14. gpcm write followed by read (ehtr = 1) ............................................... 15-35 15-15. gpcm read followed by read from different banks (ehtr = 1) ............ 15-36 15-16. gpcm read followed by read from same bank (ehtr = 1) .................. 15-36 15-17. gpcm to sram configuration .................................................................... 15-38 15-18. asynchronous external master configuration for gpcm-handled memory devices .......................................................................................... 15-38 15-19. asynchronous external master, gpcm-handled memory access timing (trlx = 0) ....................................................................................... 15-39
list of illustrations (continued) figure page number title number motorola mpc823e reference manual xxxv 15-20. user-programmable machine block diagram ..............................................15-40 15-21. ram array indexing .....................................................................................15-41 15-22. memory periodic timer request block diagram .........................................15-42 15-23. upm clock scheme one (division factor = 1) ............................................15-44 15-24. upm clock scheme two (division factor = 2) ............................................15-45 15-25. upm signals timing example one (division factor = 1, ebdf = 00) .........15-46 15-26. upm signals timing example two (division factor = 2, ebdf = 01) .........15-47 15-27. ram array and signal generation ...............................................................15-48 15-28. csx signal selection ....................................................................................15-55 15-29. bsx signal selection ....................................................................................15-56 15-30. early gpl5 control ......................................................................................15-58 15-31. address multiplex timing .............................................................................15-60 15-32. upm read access data sampling ..............................................................15-64 15-33. wait mechanism timing for internal and external synchronous masters ........................................................................................................15-65 15-34. wait mechanism timing for an external asynchronous master .................15-66 15-35. synchronous external master access .........................................................15-69 15-36. asynchronous external master access ........................................................15-70 15-37. synchronous external master interconnect example ..................................15-72 15-38. synchronous external masterCburst read access to page mode dram ...........................................................................................................15-73 15-39. asynchronous external master interconnect example ................................15-74 15-40. asynchronous external master timing example .........................................15-75 15-41. page mode dram interface connection .....................................................15-76 15-42. single beat read access to page mode dram ........................................15-78 15-43. single beat write access to page mode dram .........................................15-79 15-44. burst read access to page mode dram (no loop) ...............................15-80 15-45. burst read access to page mode dram (loop) .....................................15-81 15-46. burst write access to page mode dram (no loop) ................................15-82 15-47. burst write access to page mode dram (loop) .......................................15-83 15-48. refresh cycle (cas before ras) to page mode dram ............................15-84 15-49. exception cycle ...........................................................................................15-85 15-50. optimized dram burst read access ..........................................................15-87 15-51. edo dram interface connection ................................................................15-88 15-52. edo dram single beat read access ........................................................15-90 15-53. edo dram single beat write access ........................................................15-91 15-54. edo dram burst read access ..................................................................15-92 15-55. edo dram burst write access ..................................................................15-93 15-56. edo dram refresh cycle (cas before ras) ...........................................15-94 15-57. edo dram exception cycle .......................................................................15-95 15-58. blank worksheet for a upm .........................................................................15-96
list of illustrations (continued) figure page number title number xxxvi mpc823e reference manual motorola section 16 communication processor module 16-1. cpm block diagram ....................................................................................... 16-3 16-2. example of a pda application ....................................................................... 16-4 16-3. risc microcontroller block diagram ............................................................. 16-5 16-4. dual-port ram block diagram .................................................................... 16-13 16-5. dual-port ram memory map ....................................................................... 16-14 16-6. risc timer table ram usage .................................................................... 16-18 16-7. dsp functionality implementation ............................................................... 16-26 16-8. dsp function descriptor operation ............................................................. 16-28 16-9. circular buffer .............................................................................................. 16-29 16-10. dsp implementation example ..................................................................... 16-35 16-11. core and cpm implementation .................................................................... 16-37 16-12. fir1 implementation example ..................................................................... 16-39 16-13. fir1 coefficients and sample data buffers ................................................ 16-39 16-14. fir2 implementation example ..................................................................... 16-42 16-15. fir2 coefficients and sample data buffers ................................................ 16-43 16-16. fir2 implementation example ..................................................................... 16-46 16-17. fir3 coefficients and sample data buffers ................................................ 16-47 16-18. fir5 implementation example ..................................................................... 16-50 16-19. fir5 coefficients and sample data buffers ................................................ 16-51 16-20. fir6 implementation example ..................................................................... 16-54 16-21. fir6 coefficients and sample data buffers ................................................ 16-55 16-22. iir implementation example ........................................................................ 16-57 16-23. iir coefficients and sample data buffers ................................................... 16-58 16-24. mod implementation example .................................................................... 16-60 16-25. mod table and sample data buffers ......................................................... 16-60 16-26. demod implementation example ............................................................... 16-62 16-27. demod modulation table and sample data buffers .................................. 16-63 16-28. lms1 implementation example ................................................................... 16-65 16-29. lms1 coefficients and sample data buffers ............................................... 16-65 16-30. lms2 implementation example ................................................................... 16-67 16-31. lms2 coefficients and sample data buffers ............................................... 16-68 16-32. wadd implementation example ................................................................. 16-70 16-33. wadd modulation table and sample data buffers .................................... 16-71 16-34. timer block diagram ................................................................................... 16-74 16-35. timer cascaded mode block diagram ........................................................ 16-76 16-36. sdma data paths ........................................................................................ 16-83 16-37. sdma bus arbitration .................................................................................. 16-84 16-38. idma buffer descriptor ring ........................................................................ 16-91 16-39. single-address, peripheral write, asynchronous ta ................................ 16-103 16-40. single-address, peripheral write, synchronous ta .................................. 16-104
list of illustrations (continued) figure page number title number motorola mpc823e reference manual xxxvii 16-41. single-address, peripheral read, synchronous ta ..................................16-105 16-42. idma single-address burst read or write ................................................16-111 16-43. serial interface block diagram ...................................................................16-113 16-44. various configurations with the tdm channel .........................................16-116 16-45. enabling connections through the serial interface ...................................16-117 16-46. configuring the tdm with static frames ...................................................16-118 16-47. configuring the tdm with dynamic frames ..............................................16-119 16-48. configuring two tdms with static frames .................................................16-120 16-49. configuring two tdms with dynamic frames ...........................................16-121 16-50. using the swtr bit ...................................................................................16-122 16-51. serial interface ram dynamic changes ....................................................16-127 16-52. example of one clock delay from sync to data (rfsdx = 01) ................16-132 16-53. example of no delay from sync to data (rfsdx = 00) ............................16-132 16-54. example of clock edge (ce) effect when dscx = 0 ................................16-133 16-55. example of clock edge (ce) effect when dscx = 1 ................................16-133 16-56. example of frame transmission reception when rfsdx or tfsdx = 0 and cd = 1 .................................................................................................16-134 16-57. example of cex = 0 and fex interaction, xfsd = 0 .................................16-135 16-58. idl bus application example .....................................................................16-144 16-59. idl terminal adaptor .................................................................................16-146 16-60. idl bus signals ..........................................................................................16-147 16-61. gci bus signals .........................................................................................16-150 16-62. bank of clocks ...........................................................................................16-155 16-63. baud rate generator block diagram .........................................................16-157 16-64. serial communication controller block diagram .......................................16-164 16-65. sccx memory structure ............................................................................16-180 16-66. rtsx output delays asserted for synchronous protocols ........................16-189 16-67. ctsx output delays asserted for synchronous protocols ........................16-190 16-68. ctsx lost in synchronous protocols .........................................................16-191 16-69. using cdx to control synchronous protocol reception ............................16-192 16-70. dpll receiver block diagram ...................................................................16-195 16-71. dpll transmitter block diagram ...............................................................16-194 16-72. dpll encoding examples .........................................................................16-196 16-73. serial irda link ..........................................................................................16-198 16-74. uart character format ............................................................................16-201 16-75. two uart multidrop mode configuration examples .................................16-209 16-76. scc2 uart receive buffer descriptor example ......................................16-221 16-77. sccx uart interrupt event example .......................................................16-227 16-78. sccx hdlc framing structure .................................................................16-234 16-79. hdlc address recognition example ........................................................16-238 16-80. scc2 hdlc receive buffer descriptor example ......................................16-245 16-81. hdlc interrupt event example ..................................................................16-251
list of illustrations (continued) figure page number title number xxxviii mpc823e reference manual motorola 16-82. typical hdlc bus multimaster configuration ............................................ 16-258 16-83. typical hdlc bus single-master configuration ........................................ 16-259 16-84. detecting an hdlc bus collision .............................................................. 16-260 16-85. example of a nonsymmetrical duty cycle ................................................. 16-261 16-86. hdlc bus transmission line configuration ............................................. 16-262 16-87. delayed rtsx mode .................................................................................. 16-263 16-88. hdlc bus time-slot assigner transmission line configuration .............. 16-263 16-89. localtalk frame format ............................................................................ 16-265 16-90. connecting the mpc823e to appletalk ..................................................... 16-267 16-91. async hdlc frame structure ................................................................. 16-270 16-92. reception flowchart .................................................................................. 16-272 16-93. serial irda link .......................................................................................... 16-287 16-94. low-speed irda data format .................................................................... 16-288 16-95. middle speed packet format ..................................................................... 16-289 16-96. middle-speed irda data format ................................................................ 16-289 16-97. one complete symbol ............................................................................... 16-290 16-98. high-speed packet format ........................................................................ 16-291 16-99. preamble field symbol format ................................................................. 16-291 16-100.start flag symbol format ......................................................................... 16-291 16-101.stop flag symbol format .......................................................................... 16-296 16-102.high-speed irda data format .................................................................. 16-296 16-103.serial infrared interaction pulse waveform ............................................... 16-297 16-104.sending transparent frames between each mpc823e .......................... 16-310 16-105.ethernet frame format ............................................................................. 16-322 16-106.ethernet block diagram ............................................................................ 16-324 16-107.connecting the mpc823e to ethernet ....................................................... 16-326 16-108.ethernet address recognition flowchart .................................................. 16-337 16-109.ethernet receive buffer descriptor example ............................................ 16-344 16-110.ethernet interrupt events example ........................................................... 16-351 16-111.usb controller block diagram .................................................................. 16-355 16-112.usb interface ............................................................................................ 16-353 16-113.usb controller operating modes .............................................................. 16-355 16-114.usb buffer descriptor ring ....................................................................... 16-375 16-115.serial management controller block diagram .......................................... 16-383 16-116.smcx memory format .............................................................................. 16-385 16-117.smcx uart frame format ...................................................................... 16-393 16-118.smcx uart receive buffer descriptor example ..................................... 16-402 16-119.smcx uart interrupt example ................................................................ 16-406 16-120.smsynx pin synchronization ................................................................... 16-412 16-121.time-slot assigner synchronization ......................................................... 16-413 16-122.spi block diagram .................................................................................... 16-434 16-123.spi memory format .................................................................................. 16-442
list of illustrations (continued) figure page number title number motorola mpc823e reference manual xxxix 16-124.spi transfer format if cp is set to 0 ........................................................16-446 16-125.spi transfer format if cp is set to 1 ........................................................16-446 16-126.i 2 c controller block diagram .....................................................................16-456 16-127.i 2 c timing ..................................................................................................16-458 16-128.byte write to device with internal addresses ............................................16-459 16-129.byte write to device without internal addresses .......................................16-459 16-130.byte read from device with internal addresses .......................................16-460 16-131.byte read from device without internal addresses ..................................16-460 16-132.i 2 c memory format ...................................................................................16-467 16-133.parallel block diagram for pa15 ..............................................................16-482 16-134.parallel block diagram for pa14 ..............................................................16-483 16-135.mpc823e interrupt structure .....................................................................16-499 16-136.interrupt request masking ........................................................................16-504 section 17 pcmcia interface 17-1. system with one pcmcia socket .................................................................17-2 17-2. internal dma request logic ..........................................................................17-9 17-3. pcmcia single beat read cycle (prs = 0, psst = 1, psl = 3, psht = 1) ....................................................................................................17-22 17-4. pcmcia single beat read cycle (prs = 0, psst = 2, psl = 4, psht = 1) ....................................................................................................17-23 17-5. pcmcia single beat read cycle (prs = 0, psst = 1, psl = 3, psht = 0) ....................................................................................................17-24 17-6. pcmcia single beat write cycle (prs = 2, psst = 1, psl = 3, psht = 1) ....................................................................................................17-25 17-7. pcmcia single beat write cycle (prs = 3, psst = 1, psl = 4, psht = 3) ....................................................................................................17-26 17-8. pcmcia single beat write with wait (prs = 3, psst = 1, psl = 3, psht = 0) ....................................................................................................17-27 17-9. pcmcia single beat read with wait (prs = 3, psst = 1, psl = 3, psht = 1) ....................................................................................................17-28 17-10. pcmcia i/o read of a 16-bit slave port (pps = 1, prs = 3, psst = 1, psl = 2, psht = 0) .....................................................................................17-29 17-11. pcmcia i/o read of an 8-bit slave port (pps = 1, prs = 3, psst = 1, psl = 2, psht = 0 .......................................................................................17-30 17-12. pcmcia dma read cycle (prs = 4, psst = 1, psl = 3, psht = 0) ........17-31
list of illustrations (continued) figure page number title number xl mpc823e reference manual motorola section 18 lcd controller 18-1. lcd panel ...................................................................................................... 18-2 18-2. lcd subsystem ............................................................................................. 18-3 18-3. passive interfaces .......................................................................................... 18-4 18-4. active (tft) interface .................................................................................... 18-5 18-5. the mpc823e lcd system ........................................................................... 18-6 18-6. lcd controller block diagram ....................................................................... 18-7 18-7. lcd functional module ................................................................................. 18-8 18-8. grayscale generation .................................................................................. 18-11 18-9. color generation .......................................................................................... 18-12 18-10. single-scan and dual-scan lcd panels ..................................................... 18-15 18-11. passive interface timing diagram ............................................................... 18-16 18-12. active interface timing diagram .................................................................. 18-18 18-13. color ram transparent translation for one-bit per pixel mode ................ 18-31 18-14. color ram entries for two bits per pixel mode .......................................... 18-32 18-15. color ram entries for four bits per pixel (grayscale) ................................ 18-34 section 19 video controller 19-1. typical mpc823e video system ................................................................... 19-1 19-2. video controller block diagram ..................................................................... 19-3 19-3. output timing example ................................................................................. 19-4 19-4. video ram array block diagram ................................................................. 19-16 19-5. interlaced ntsc format .............................................................................. 19-20 19-6. ntsc horizontal timing .............................................................................. 19-21 19-7. interlaced pal format ................................................................................. 19-24 19-8. pal horizontal timing ................................................................................. 19-25 section 20 development capabilities and interface 20-1. watchpoint and breakpoint support in the core .......................................... 20-10 20-2. example 2 false detect on watchpoint/breakpoint ..................................... 20-14 20-3. instruction support general structure ......................................................... 20-16 20-4. load/store support general structure ........................................................ 20-19 20-5. relationship between the cpu and debug mode ....................................... 20-21 20-6. debug mode logic implementation ............................................................. 20-23 20-7. debug mode reset configuration timing diagram ..................................... 20-25 20-8. development port/background development mode connector pinout options ........................................................................................................ 20-30
list of illustrations (continued) figure page number title number motorola mpc823e reference manual xli 20-9. asynchronous clocked serial communications timing diagram ................20-33 20-10. synchronous self-clocked serial communications timing diagram ..........20-34 20-11. enabling clock mode following reset timing diagram ..............................20-35 20-12. download procedure code example ...........................................................20-39 20-13. slow download procedure loop ..................................................................20-40 20-14. fast download procedure loop ...................................................................20-40 section 21 ieee 1149.1 test access port 21-1. test logic block diagram ..............................................................................21-2 21-2. tap controller state machine ........................................................................21-3 21-3. output pin cell (o.pin) ...................................................................................21-4 21-4. observe-only input pin cell (i.obs) ...............................................................21-5 21-5. output control cell (io.ctl) ..........................................................................21-5 21-6. general arrangement of bidirectional pin cells .............................................21-6 21-7. bypass register ...........................................................................................21-20
motorola mpc823e reference manual xliii list of tables table page number title number section 2 external signals 2-1. signal descriptions ..........................................................................................2-2 2-2. pin breakout ...................................................................................................2-13 section 3 memory map 3-1. mpc823e internal memory map ......................................................................3-1 section 4 reset 4-1. possible reset results ....................................................................................4-1 section 5 clocks and power control 5-1. power-on reset clock configuration ............................................................5-13 5-2. reset clock source configuration .................................................................5-22 5-3. tmbclk dividers ...........................................................................................5-23 5-4. xfc capacitor values based on the mf field ..............................................5-23 5-5. mpc823e power supply ................................................................................5-25 5-6. key registers .................................................................................................5-27 5-7. mpc823e low-power modes ........................................................................5-31 section 6 the powerpc core 6-1. branch prediction policy ..................................................................................6-6 6-2. before and after interrupts............................................................................... 6-8 6-3. special ports to machine state register bits .................................................6-11 6-4. interrupt latency ............................................................................................6-11 6-5. instruction-related interrupt detection order ................................................6-14 6-6. interrupt priority mapping ...............................................................................6-15 6-7. standard special-purpose registers .............................................................6-16 6-8. standard timebase register mapping ...........................................................6-16 6-9. additional special-purpose registers ............................................................6-17
list of tables (continued) table page number title number motorola mpc823e reference manual xliv 6-10. other control registers .................................................................................6-19 6-11. encoding special registers located outside the core .................................6-19 6-12. load/store instructions timing ......................................................................6-30 6-13. value summary of the dar, bar, and dsisr registers ............................6-31 section 7 powerpc architecture compliance 7-1. offset of first instruction by interrupt type ......................................................7-8 section 8 instruction execution timing 8-1. instruction execution timing ............................................................................8-1 section 11 memory management unit 9-1. number of effective address bits replaced by real address bits ...............11-8 10-1. number of identical entries required in the level one table .......................11-8 11-1. number of identical entries required in the level two table .......................11-8 section 12 system interface unit 12-1. priority of system interface unit interrupt sources ........................................12-6 12-2. multiplexing control ......................................................................................12-29 section 13 external bus interface 13-1. bus interface signals .....................................................................................13-4 13-2. data bus requirements for read cycles ...................................................13-26 13-3. data bus contents for write cycles .............................................................13-27 13-4. burst/tsize encoding ..............................................................................13-33 13-5. address space definitions ...........................................................................13-34 13-6. termination signal protocol .........................................................................13-46 section 14 endian modes 14-1. little-endian effective address modification for individual aligned scalar .............................................................................................................14-1
list of tables (continued) table page number title number xlv mpc823e reference manual motorola 14-2. endian mode programming for core data structures .................................. 14-1 14-3. little-endian program/data path between the register and 32-bit memory .......................................................................................................... 14-3 14-4. little-endian program/data path between the register and 16-bit memory .......................................................................................................... 14-4 14-5. little-endian program/data path between the register and 8-bit memory .......................................................................................................... 14-4 section 15 memory controller 15-1. memory controller register usage ................................................................ 15-8 15-2. gpcm strobe signal behavior .................................................................... 15-28 15-3. boot bank field values after reset ............................................................. 15-37 15-4. start address locations ............................................................................... 15-55 15-5. enabling byte-selects .................................................................................. 15-58 15-6. mxmr loop bit usage ................................................................................. 15-60 15-7. address multiplexing .................................................................................... 15-61 15-8. ama/amb definition for dram interface ................................................... 15-62 15-9. gpl_x5 signal (pin) behavior ..................................................................... 15-72 15-10. upma register settings .............................................................................. 15-78 15-11. upmb register settings .............................................................................. 15-90 section 16 communication processor module 16-1. ram microcode configurations ..................................................................... 16-9 16-2. risc microcontroller commands ................................................................ 16-11 16-3. parameter ram memory map ..................................................................... 16-16 16-4. risc timer table parameter ram memory map ....................................... 16-19 16-5. pwm channel pin assignments .................................................................. 16-22 16-6. dsp functions ............................................................................................. 16-27 16-7. dsp parameter ram memory map ............................................................. 16-31 16-8. fir1 parameter packet ............................................................................... 16-41 16-9. fir2 parameter packet ............................................................................... 16-45 16-10. fir3 parameter packet ............................................................................... 16-49 16-11. fir5 parameter packet ............................................................................... 16-53 16-12. fir6 parameter packet ............................................................................... 16-57 16-13. iir parameter packet ................................................................................... 16-59 16-14. mod parameter packet ............................................................................... 16-62 16-15. demod parameter packet .......................................................................... 16-64 16-16. lms1 parameter packet .............................................................................. 16-67
list of tables (continued) table page number title number motorola mpc823e reference manual xlvi 16-17. lms2 parameter packet ..............................................................................16-70 16-18. wadd parameter packet ............................................................................16-72 16-19. wadd functions ..........................................................................................16-73 16-20. dsp functions execution times ..................................................................16-73 16-21. idma parameter ram memory map ...........................................................16-93 16-22. single-buffer mode parameter ram map ..................................................16-107 16-23. typical baud rates of asynchronous communication ..............................16-163 16-24. sccx parameter ram memory map for all protocols ..............................16-185 16-25. preamble patterns for decoding methods .................................................16-197 16-26. sccx uart parameter ram memory map ..............................................16-206 16-27. sccx hdlc parameter ram memory map ..............................................16-239 16-28. sccx async hdlc parameter ram memory map .................................16-278 16-29. sccx transparent parameter ram memory map .....................................16-311 16-30. sccx ethernet parameter ram memory map ..........................................16-330 16-31. usb pin functionality ................................................................................16-358 16-32. usb out token reception .........................................................................16-360 16-33. usb in token reception ............................................................................16-361 16-34. usb parameter ram memory map ...........................................................16-362 16-35. endpoint parameters block ........................................................................16-364 16-36. smcx (uart and transparent) parameter ram memory map ................16-391 16-37. smcx uart parameter ram memory map ..............................................16-399 16-38. smcx gci parameter ram memory map .................................................16-432 16-39. spi parameter ram memory map .............................................................16-443 16-40. i 2 c controller parameter ram memory map .............................................16-468 16-41. port a pin assignment ...............................................................................16-484 16-42. port b pin assignment ...............................................................................16-489 16-43. port c pin assignment ...............................................................................16-494 16-44. port d pin assignment ...............................................................................16-501 16-45. prioritization of cpm interrupt sources ......................................................16-507 16-46. encoding the interrupt vector ....................................................................16-510 section 17 pcmcia interface 17-1. card enable as driven by the mpc823e .......................................................17-3 17-2. host programming for memory cards ...........................................................17-7 17-3. host programming for i/o cards ..................................................................17-7 section 18lcd controller 18-1. lcdclk programming ................................................................................18-14 18-2. horizontal pixel count programming ...........................................................18-24 18-3. vertical pixel count programming ...............................................................18-26
list of tables (continued) table page number title number xlvii mpc823e reference manual motorola 18-4. lcd panel connection ................................................................................ 18-37 section 19 video controller 19-1. video ram array loaded with ntsc example ........................................... 19-23 19-2. video ram word loaded with pal example .............................................. 19-27 section 20 development capabilities and interface 20-1. vf instruction type encoding ........................................................................ 20-4 20-2. detecting the trace buffer starting point ...................................................... 20-7 20-3. fetch show cycle types ............................................................................... 20-8 20-4. instruction watchpoints programming options ............................................ 20-17 20-5. load/store data events ............................................................................... 20-18 20-6. load/store watchpoints programming options ........................................... 20-18 20-7. checkstop state and debug mode .............................................................. 20-27 20-8. trap enable data shifted into dps register ............................................... 20-36 20-9. d ebug port command shifted into the dps register ........................... 20-36 20-10. status/data shifted out of dps register .................................................... 20-37 20-11. debug instructions/data shifted into the dps register .............................. 20-38 20-12. development support register protection ................................................... 20-41 section 21 ieee 1149.1 test access port 21-1. boundary scan bit definition ......................................................................... 21-7 21-2. instruction decoding .................................................................................... 21-19 appendix a serial communication performance a-1. mpc823e performance table .........................................................................a-3
motorola mpc823e reference manual 1-1 introduction 1 section 1 introduction the mpc823e microprocessor is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of portable electronic products. it is a version of the low-cost mpc823 with larger instruction and data caches, which will provide for greater powerpc core performance. the mpc823e microprocessor particularly excels in low-power, portable, image capture, and personal communication products. it integrates a high-performance embedded powerpc ? core with a communication processor module that uses a specialized risc processor for imaging and communication. the communication processor module can perform embedded signal processing functions for image compression and decompression and supports seven serial channelstwo serial communication controllers, two serial management controllers, one i 2 c port, one universal serial bus channel, and one serial peripheral interface. this two-processor architecture consumes power more efficiently than traditional architectures because the communication processor module frees the core from peripheral responsibilities like imaging and communication. 1.1 features the following list summarizes the main features of the mpc823e: ? embedded powerpc core provides 99mips (using dhrystone 2.1) or 172k dhrystones 2.1 at 75mhz o single-issue, 32-bit version of the powerpc core (fully compatible with the powerpc architecture definition) with 32 x 32-bit fixed-point registers o low power consumption, 2.2v internal, 3.3v i/o boundary with microprocessor core, caches, memory management, and i/o in operation o performs branch folding, branch prediction with conditional prefetch, without conditional execution o 8k data cache and 16k instruction cache o four-way instruction cache and two-way data cache are set-associative, physical address, 4-word line burst, lru replacement algorithm, lockable online granularity o memory management units with 32-entry translation lookaside buffers (tlbs) and fully associative instruction and data tlbs o memory management units support multiple page sizes of 4k, 16k, 512k and 8m (1k protection granularity at the 4k page size); 16 virtual address spaces and 16 protection groups ? advanced on-chip emulation debug mode
introduction 1-2 mpc823e reference manual motorola introduction 1 ? data bus dynamic bus sizing for 8-,16-, and 32-bit buses o supports traditional 68k big-endian, traditional x86 little-endian, and powerpc little-endian memory systems o twenty-six external address lines ? completely static design (0C75mhz operation) ? communication processor module o embedded 32-bit risc microcontroller architecture for flexible i/o o interfaces to powerpc core through on-chip 8k dual-access ram and virtual (serial) dma channels on a dedicated dma accelerator o continuous mode transmission and reception on all serial and parallel channels o twenty serial dma (sdma) channels for reception and transmission on all serial and parallel cpm channels o programmable memory-to-memory and memory-to-i/o (including flyby) dma provided by virtual dma support o 99mips @ 75mhz o protocols supported by rom or download microcode and the hardware serial communication controllers include, but are not limited to, the digital portions of: ethernet/ieee 802.3 (cs/cdma) hdlc/sdlc and hdlc bus appletalk signalling system #7 (ram microcode option) universal asynchronous receiver transmitter (uart) synchronous uart (usart) totally transparent mode with/without crc asynchronous hdlc irda version 1.1 serial infrared (scc2 only) basic rate isdn (bri) in conjunction with serial management controller channels v.38bis 33.6kbaud modem primary rate isdn o 16 x 16-bit multiply accumulate (mac) hardware one operation per clock two clock latency and one clock blockage operates concurrently with other instructions uses dma controller to burst data directly into register file without interacting with the powerpc core o dsp functions are supported by rom or download microcode and the communication processor module dsp capabilities, include but are no limited to jpeg compression/decompression ? four independent baud rate generators and two input clock pins for supplying clocks to the scc and smc serial channels
introduction motorola mpc823e reference manual 1-3 introduction 1 ? two serial communication controllers o ethernet/ieee 802.3 support (10mbps and full-duplex operation) o geoport support o hdlc bus implements an hdlc-based local area network o universal asynchronous receiver transmitter (uart) o synchronous uart o serial infrared (irda) supporting a maximum of 4mbps (scc2 only) o totally transparent. frame based with optional cyclical redundancy check o maximum serial data rate of 66mbps at 75mhz ? one dedicated high-speed serial channel for the universal serial bus (usb) o supports usb slave mode at a maximum of 12mbps with four usb endpoints (one for control and three for data) ? two serial management controllers with externally accessible pins o provides management for bri devices as general circuit interface control functions in tdm channels o low-speed uart, transparent and codec interfaces ? one serial peripheral interface o supports master and slave modes o supports multimaster operation on the same bus ? one i 2 c ? (microwire-compatible) interface that supports master and slave modes ? serial interface with a time-slot assigner o allows serial communication controllers and serial management controllers to be used in multiplexed and/or nonmultiplexed operation o supports t1, cept, pcm highway, isdn basic rate, isdn primary rate, user-defined o 1- or 8-bit resolution o allows independent transmit and receive routing, frame synchronization, and dynamic clocking modification capability o eight programmable strobes can be used to generate wave patterns o software-configurable for internal interconnection of cpm serial channels ? four independent 16-bit timers that can be configured as two 32-bit timers. ? interrupts o seven external interrupt request (irq) lines o one nonmaskable interrupt o twelve port pins with interrupt capability o ten internal interrupt sources o programmable highest priority request
introduction 1-4 mpc823e reference manual motorola introduction 1 ? memory controller (eight banks) o contains complete dram controller o each bank can be a chip-select or ras to support a dram bank o a maximum of 30 wait states per memory bank can be programmed o glueless interface to dram single in-line memory modules, static ram, electrically programmable read-only memory, flash eprom or synchronous dram o four cas lines, four we lines, and one oe line o boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) o variable block sizes32k to 256m o selectable write protection ? system integration unit o hardware bus monitor o software watchdog timer o periodic interrupt timer o low-power stop mode o clock synthesizer o on-chip bus arbitration logic o powerpc decrementer o powerpc timebase o real-time clock o reset controller ? video/lcd controller o video controller supports digital tft lcd panels and analog ntsc/pal displays sequential rgb, 4:4:4, and 4:2:2 yc r c b (ccir 601) digital component video formats ccir-656 compatible 8-bit interface port horizontal sync, vertical sync, field and blanking timing generation with half-clock resolution and programmable polarity supports interlace/noninterlace scanning methods programmable display active area programmable background color for inactive area glueless interface for most digital video encoders uses burst read dma cycles for maximum bus performance end-of-frame interrupt generation
introduction motorola mpc823e reference manual 1-5 introduction 1 o lcd controller 1-, 2-, or 4-bit per pixel grayscale mode using advanced frame rate control (frc) algorithm 4-, 8-, 9-, or 12-bit parallel output to lcd displays programmable display active area nonsplit- or vertically split-screen support uses burst read dma cycles for maximum bus performance end-of-frame interrupt generation data for splits2+2 or 4+4 parallel bits (x+x refers to x bits each for lower and upper screens in parallel) built-in color ram with 256 12-bit entries programmable wait time between lines and frames panel voltage control adjustments for contrast set with on-chip timers programmable polarity for all lcd interface signals uses burst read dma cycles for maximum bus performance end-of-frame interrupt generation ? single-socket pcmcia-ata interface o master interface, release 2.1-compliant o single pcmcia socket o eight memory or i/o windows available o eight general-purpose i/o pins and two general-purpose output-only pins are available when the pcmcia controller is not in operation ? low-power support modes o normal highCall units are fully powered at high clock frequency o normal lowCall units are fully powered at low clock frequency o dozeCcore functional units are disabled, except timebase, decrementer, pll, memory controller, real-time clock, lcd, and communication processor module o sleepCall units are disabled, except real-time clock, periodic interrupt timer, timebase, and decrementer. pll is active for fast wake-up o deep sleepCall units are disabled including pll, but not the real-time clock and periodic interrupt timer, timebase, and decrementer o power-downall units are disabled including pll, but not the real-time clock and periodic interrupt timer, timebase, and decrementer. saves more power than other modes. the state of certain registers may be preserved. o can be dynamically shifted between high and low frequency operation
introduction 1-6 mpc823e reference manual motorola introduction 1 ? development capabilities and interface o program flow tracking instruction show cycle data show cycle branching exception traps o watchpoints and breakpoints four hardware breakpoints five watchpoint sources o simple hardware interface high-speed data transfer internal status pins freeze indication o rich control register set ? ieee 1149.1 test access port (jtag) ? 3.3v operation with 5v ttl compatibility for the jtag and communication processor module port pins and 3.3v for all others. ? 256-pin plastic ball grid array (bga) packaging 1.2 architecture the mpc823e microprocessor uses a dual-processor architecture design approach with large data and instruction caches to provide high performance using a general-purpose risc integer processor and a special-purpose 32-bit scalar risc communication processor module. the peripherals are uniquely designed for communication requirements and can provide embedded signal processing functions for communication and user interface enhancements and the i/o support needed for high-speed digital communications. the mpc823e is comprised of four main modules that interface with the 32-bit internal bus: ? the embedded powerpc core ? the system interface unit ? the communication processor module ? lcd controller the mpc823e block diagram is illustrated in figure 1-1.
introduction motorola mpc823e reference manual 1-7 introduction 1 figure 1-1. mpc823e block diagram extended powerpc core instruction int_biu ext_biu memory controller e_bus instruction system functions system interface unit pcmcia interface lcd data mmu data cache timers master interrupt controller slave parallel i/o dual-port scc2 smc1 smc2 i 2 c usb spi serial interface and time-slot assigner risc microcontroller peripheral bus cpm local bus alu crc register file mac sequencer rom ram baud rate generators communication interface interface processor core interface cache mmu scc3
introduction 1-8 mpc823e reference manual motorola introduction 1 1.2.1 the embedded powerpc core the powerpc core complies with standard powerpc architecture. it has a fully static design that consists of three functional blocksthe integer block, hardware multiplier/divider, and load/store block. the core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. its interface to the internal and external buses is 32 bits. the core uses a two-instruction load/store queue, four-instruction prefetch queue, and a six-instruction history buffer. it performs branch folding and branch prediction with conditional prefetch, but without conditional execution. with single bus cycles, the core can operate on 32-bit external operands and with critical-word-first in multiple bus cycles. the powerpc integer block supports 32 x 32-bit fixed-point general-purpose registers and can execute one integer instruction per clock cycle. the powerpc core is integrated with the memory management units, an instruction cache, and a data cache. the memory management units (mmus) provide 32-entry, fully-associative instruction and data tlbs, with multiple page sizes of 4k (1k protection), 16k, 512k, and 8m. they support 16 virtual address spaces and 16 protection groups. special registers are available to support software tablewalk and update. the instruction cache is 16k, four-way, set-associative with physical addressing. it allows single-cycle accesses on hit with no added latency for miss. it is four words per line and supports burst line fill using an lru replacement algorithm. the cache can be locked on a line basis for application critical routines. the data cache is 8k, four-way, set-associative with physical addressing. it allows single-cycle accesses on hit with one added clock latency for miss. it has four words per line and supports burst line fill using an lru replacement algorithm. the cache can be locked on a line basis for application critical data and can be programmed to support copyback or writethrough mode via the memory management unit. the cache-inhibit mode can be programmed per mmu page. the powerpc core, with its instruction and data caches, can deliver approximately 99mips at 75mhz (using dhrystone 2.1) or 172k dhrystones, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of 94%. 1.2.2 the system interface unit the system interface unit supports traditional 68k big-endian memory systems, traditional x86 little-endian memory systems, and powerpc little-endian memory systems. it also provides power management functions, reset control, a powerpc decrementer, powerpc timebase, and real-time clock. although the powerpc core is a 32-bit device internally, it can be configured to operate with an 8-, 16-, or 32-bit data bus. regardless of the system bus size, dynamic bus sizing is supported, which allows 8-, 16-, and 32-bit peripherals and memory to coexist on a 32-bit system bus. the memory controller supports up to eight memory banks with glueless interfaces to dram, sram, eprom, flash eprom, sdram, edo and other peripherals with two-clock initial access to external sram and bursting support. it provides variable block sizes between 32k and 256m. the memory controller has 0 to 20 wait states for each bank of memory and can use address type matching to qualify each memory bank access. it provides four byte-enable signals for varying width devices, one output-enable signal, and one boot chip-select that is available at reset.
introduction motorola mpc823e reference manual 1-9 introduction 1 the dram interface supports 8-, 16-, and 32-bit ports and uses a programmable state machine to support almost any memory interface. memory banks can be defined in depths of 256k, 512k, 1m, 2m, 4m, 8m, 16m, 32m, or 64m for all port sizes. in addition, the memory depth can be defined as 64k and 128k for 8-bit memory or 128m and 256m for 32-bit memory. the dram controller supports page mode access for successive transfers within bursts. although the mpc823e supports a glueless interface to dram, the capacitance of the system bus may require that there be external buffers. the refresh unit provides cas before ras , a programmable refresh timer, refresh active during external reset, disable refresh modes, and stacking for a maximum of seven refresh cycles. 1.2.3 the communication processor module the communication processor module (cpm) contains features that allow the mpc823e microprocessor to excel in imaging, personal communication, and low-power applications. these features are divided into three categories: ? dsp processing ? communication processing ? twelve serial dma channels and two independent dma channels the mpc823es embedded dsp function allows the communication processor module to execute imaging algorithms in parallel with the powerpc core to achieve maximum performance with very little power. the dsp can execute one 16x16 mac on every clock cycle. it has preprogrammed filtering functions like fir, mod, demod, iir, and downloadable imaging functions for jpeg image compression and decompression. these functions are also used by modem and speech recognition programs. the robust communication features of the mpc823e are provided by the communication processor module. these features include a risc microcontroller with multiply accumulate (mac) hardware, two serial communication controllers (sccs), two serial management controllers (smcs), one dedicated serial channel for the universal serial bus (usb), one inter-integrated circuit (i 2 c) port, one serial peripheral interface (spi), 8k dual-port ram, an interrupt controller, a time-slot assigner, and four independent baud rate generators. twenty serial dma channels support the sccs, smcs, usb channel, spi, and i 2 c controllers. the independent dmas give you two channels for general-purpose dma usage. they offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. the risc microcontroller is the only block that can access the idma registers directly. the cpu can only access them indirectly via a buffer descriptor.
introduction 1-10 mpc823e reference manual motorola introduction 1 1.2.4 the video/lcd controller the mpc823e has a dual-purpose video/lcd controller that shares common dual-port memory. you can only run one of the controllers at a time. 1.2.4.1 the video controller. the video controller can be used to drive a digital ntsc/pal encoder or a wide variety of digital lcd panels. the frame buffer is stored in system memory in the form of an orthogonal matrixrows and columns. the 24-bit color data is organized as pixel components whether it is sequential rgb or yc r c b . each pixel component is represented by a byte. the video controller uses a dedicated dma channel to read the display data from the frame buffer and drive it to the video interface. it also generates the required timing signals such as horizontal sync, vertical sync, field, and blanking. refer to section 19 video controller for more information. 1.2.4.2 the lcd controller. the lcd controller provides extremely versatile lcd support for 8-bit color, monochrome or 4/16-level grayscale, color tft (12 bits, 4x3 rgb), and passive color (xstn) 4/8 bit data. the controller supports 4- or 8-bit single-scan, 2+2- bit dual-scan, or 4+4-bit dual-scan. it is programmable for frame rate, number of pixels per line, and number of lines per frame. the panel voltage is programmable through the duty cycle for contrast adjustments implemented in the communication processor module program. display data is stored in your own memory space and is transferred into the controller using the dma channel. refer to section 18 lcd controller for more information. 1.3 the pcmcia-ata controller the pcmcia-ata interface is a master controller that is compliant with version 2.1 of the pcmcia standard. the interface supports one independent pcmcia socket with the required external transceivers or buffers. it provides eight memory or i/o windows that can be allocated to the socket. if the pcmcia port is not being used as a card interface, it can provide eight general-purpose pins and two output-only pins with interrupt capability.
introduction motorola mpc823e reference manual 1-11 introduction 1 1.4 power management the mpc823e microprocessor supports a wide range of power management features, including normal high, normal low, doze, sleep, deep-sleep, and power-down modes. in normal high mode, the mpc823e microprocessor is fully powered with all internal units operating at the full speed of the processor. normal low mode is the same as normal high, except it operates at a much lower frequency. there is a doze mode determined by a clock divider that allows the operating system to reduce the operational frequency of the processor. doze mode disables core functional units except the timebase, decrementer, pll, memory controller, real-time clock, lcd controller, and communication processor module. sleep mode is a lower power mode that disables everything except the real-time clock, timebase, decrementer, and periodic interrupt timer, thus leaving the pll active for quick wake-up. the deep-sleep mode then disables the pll for lower power, but slower wake-up. power-down mode disables all logic in the processor, except the minimum logic required to restart the device. it saves the most power, but requires the longest wake-up time. 1.5 system debug support the mpc823e microprocessor contains an advanced debug interface that provides superior debug capabilities without any loss of speed. it supports six watchpoint pins that can be combined with eight internal comparators, four of which operate on the effective address of the address bus. the other four comparators are splittwo comparators operate on the effective address on the data bus and two comparators operate on the data on the data bus. the mpc823e microprocessor can compare using the =, 1 , <, and > conditions to generate watchpoints. each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events. 1.6 applications the mpc823e microprocessor is specifically designed to be a general-purpose, low-cost entry point to the motorola embedded powerpc family for systems in which advanced guis, communications, and high-level real-time operating systems are used. the device excels in applications that require the performance of single-issue powerpc core with a moderate amount of data and instruction cache. it provides all the basic features of glueless memory connections along with functional serial connectivity, a graphical lcd, and a video display controller. the mpc823e excels in low-power and portable applications because of its extensive power-down modes and low normal operation current.
introduction 1-12 mpc823e reference manual motorola introduction 1 1.7 differences between mpc823 (rev 1) and mpc823e the following modifications were made to the mpc823 revision 1 to create the mpc823e: ? core operation was increased to 99mips @ 75mhz or 172k dhyrstones ? the instruction cache was increased to 16k ? there are twenty serial dma channels for reception and transmission ? the data cache was increased to 8k ? the instruction and data memory management units each consist of 32 tlb entries ? a time-division multiplex channel (tdmb) was added to the serial interface 1.8 mpc823e glueless system design the mpc823e was primarily designed to make it easy for you to interface a microprocessor with other system components. figure 1-2 illustrates a system configuration that contains one flash eprom and yet supports dram simm and one sram. although the mpc823e supports a glueless interface to dram, the capacitance of the system bus may require that there be external buffers. from a logic standpoint, however, a glueless system is maintained.
introduction motorola mpc823e reference manual 1-13 introduction 1 figure 1-2. mpc823e system configuration ce oe w address we data address ras cas [0:3] data mpc823e cs1 we[ 0:3] rd/ wr gpl1/ oe address data cs0 ce oe w ce oe address we data ce oe 8-bit boot eprom/flash dram sram we0 cs2 parity[0:3] parity[0:3]
motorola mpc823e reference manual 2-1 external signals 2 section 2 external signals this section briefly describes each of the mpc823e input and output signals. figure 2-1. mpc823e signal pinout mpc823e 26 1 6 32 4 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 vddsyn/vsssyn/vsssyn1/vddh/vddl/vss/kapwr usbrxd/pa[15] usboe/pa[14] rxd2/pa[13] txd2/pa[12] smrxd2/l1txda/pa[9] smtxd2/l1rxda/pa[8] tin1/l1rclka/brgo1/clk1/pa[7] tin3/l1rclkb/tout1/clk2/pa[6] tin2/l1tclka/brgo2/clk3/pa[5] tin4/l1tclkb/tout2/clk4/pa[4] lcd_a/spisel/pb[31] spiclk/txd3/pb[30] spimosi/rxd3/pb[29] brgo3/spimiso/pb[28] brgo1/i2csda/pb[27] brgo2/i2cscl/pb[26] smtxd1/txd3/pb[25] smrxd1/l1rxdb/rxd3/pb[24] smsyn1/sdack1/l1tsyncb/cts3/pb[23] lcd_b/l1st1/pb[19] l1st2/rts2/pb[18] lcd_c/l1st3/pb[17] l1st4/l1rqa/pb[16] l1st5/l1txdb/dreq1/pc[15] l1st6/rts2/dreq2/pc[14] l1st7/rts3/pc[13] l1st8/l1rqa/pc[12] usbrxp/pc[11] usbrxn/tgate1/pc[10] cts2/pc[9] tgate1/cd2/pc[8] usbtxp/pc[7] usbtxn/pc[6] sdack1/l1tsynca/pc[5] l1rsynca/cd3/pc[4] ld8/vd7/pd[15] ld7/vd6/pd[14] ld6/vd5/pd[13] ld5/vd4/pd[12] ld4/vd3/pd[11] ld3/vd2/pd[10] ld2/vd1/pd[9] ld1/vd0/pd[8] frame/vsync/pd[5] lcd_ac/loe/blank/pd[6] ld0/field/pd[7] load/hsync/pd[4] shift/clk/clk/pd[3] tms tdi/dsdi tck/dsck trst tdo/dsdo a[6:31] tsiz0/reg tsiz1 rd/wr burst bdip/gpl_b5 ts ta tea bi irq2/rsv irq4/kr/retry/spkrout d[0:31] dp[0:3]/irq[3:6] br bg bb irq6/frz irq[0:1] irq7 cs[0:5] cs6/ce1_b cs7/ce2_b we0/bs_ab0/iord we1/bs_ab1/iowr we2/bs_ab2/pcoe we3/bs_ab3/pcwe gpl_a0/gpl_b0 gpl_a1/gpl_b1/oe gpl_a[2:3]/gpl_b[2:3] gpl_a4/upwaita/as gpl_b4/upwaitb gpl_a5 poreset rstconf hreset sreset xtal extal xfc clkout extclk ale_b/dsck/at1 wait_b ip_b[0:1]/iwp[0:1]/vfls[0:1] ip_b2/iois16_b/at2 ip_b3/iwp2/vf2 ip_b4/lwp0/vf0 ip_b5/lwp1/vf1 ip_b6/dsdi/at0 ip_b7/ptr/at3 modck1/op2/sts modck2/op3/dsdo 1 smsyn2/sdack2/l1rsyncb/pb[22] 1 texp
external signals 2-2 mpc823e reference manual motorola external signals 2 2.1 the system bus signals the mpc823e system bus signals consist of all the lines that interface with the external bus. many of these lines perform different functions, depending on how you assign them. the following input and output signals are identified by their mnemonic name and each signals pin number can be found in figure 2-1. table 2-1. signal descriptions signal pin number description a[6:31] see table 2-2 for pin breakout. address bus this bidirectional three-state signal provides the address for the current bus cycle. a6 is the most-significant signal for this bus. the signal is output when an internal master on the mpc823e initiates a transaction on the external bus. the signal is input when an external master initiates a transaction on the bus and it is sampled internally to allow the memory controller/pcmcia interface to control the accessed slave device. tsiz0 reg f15 transfer size 0 when accessing a slave in the external bus, this three-state signal is used (together with tsiz1) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. this signal is input when an external master initiates a transaction on the bus and it is sampled internally to allow the memory controller/pcmcia interface to control the accessed slave device. reg when the access is initiated by an internal master to a slave under control of the pcmcia interface, this signal is output to indicate which space in the pcmcia card is currently accessed. tsiz1 e15 transfer size 1 this three-state signal is used (with tsiz0) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. this signal is driven by the mpc823e when it is the owner of the bus. it is input when an external master initiates a transaction on the bus and it is sampled internally to allow the memory controller/pcmcia interface to control the accessed slave device. rd/wr c13 read write this three-state signal is driven by the bus master to indicate the direction of the buss data transfer. a logic one indicates a read from a slave device and a logic zero indicates a write to a slave device. this signal is driven by the mpc823e when it is the owner of the bus. it is input when an external master initiates a transaction on the bus and is sampled internally to allow the memory controller/ pcmcia interface to control the accessed slave device. burst b10 burst transaction this three-state signal is driven by the bus master to indicate that the current initiated transfer is a burst one. this signal is driven by the mpc823e when it is the owner of the bus. it is input when an external master initiates a transaction on the bus; this signal and is sampled internally to allow the memory controller/pcmcia interface to control the accessed slave device. bdip gpl_b 5 a13 burst data in progress when accessing a slave device in the external bus, the master on the bus asserts this signal to indicate that the data beat in front of the current one is the one requested by the master. this signal is negated prior to the expected last data beat of the burst transfer. general-purpose line b5 this signal is used by the memory controller when the user programmable machine b (upmb) takes control of the slave access. ts d10 transfer start this three-state signal is asserted by the bus master to indicate the start of a bus cycle that transfers data to or from a slave device. this signal is driven by the master only when it has gained ownership of the bus. every master should negate this signal before the bus relinquishes. a pull-up resistor should be connected to this signal to prevent a slave device from detecting a spurious bus accessing it when no master is taking ownership of the bus. this signal is sampled by the mpc823e when it is not the owner of the external bus to allow the memory controller/pcmcia interface to control the accessed slave device. it indicates that an external synchronous master initiated a transaction.
external signals motorola mpc823e reference manual 2-3 external signals 2 ta a12 transfer acknowledge this bidirectional three-state signal indicates that the slave device addressed in the current transaction has accepted the data transferred by the master (write) or has driven the data bus with valid data (read). the signal behaves as an output when the pcmcia memory controller takes control of the transaction. the only exception occurs when the memory controller is controlling the slave access by means of the gpcm and the corresponding option register is instructed to wait for an external assertion of the transfer acknowledge line. every slave device should negate the ta signal after the end of the transaction and immediately three-state it to avoid contentions on the line if a new transfer is initiated addressing other slave devices. a pull-up resistor should be connected to this signal to keep a master device from detecting the assertion of this signal when no slave is addressed in a transfer or when the address detection for the addressed slave is slow. tea c11 transfer error acknowledge this open-drain signal indicates that a bus error occurred in the current transaction. it is driven asserted by the mpc823e when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. the assertion of tea causes the termination of the current bus cycle, thus ignoring the state of ta . bi b12 burst inhibit this bidirectional three-state signal indicates that the slave device addressed in the current burst transaction is unable to support burst transfers. the signal behaves as an output when the pcmcia memory controller takes control of the transaction. when the mpc823e drives out the signal for a specific transaction, it asserts or negates bi during the transaction according to the value you specify in the appropriate control registers. it negates the signal after the end of the transaction and immediately three-states it to avoid contentions if a new transfer is initiated addressing other slave devices. rsv irq2 d9 reservation this three-state signal is output by the mpc823e in conjunction with the address bus to indicate that the internal core initiated a transfer as a result of a stwcx or lwarx instruction. interrupt request 2 this input is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. irq4 kr retry spkrout b7 interrupt request 4 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. it should be noted that the interrupt request signal that is sent to the interrupt controller is the logical and of this signal (if defined to function as irq4 ) and the dp1/irq4 (if defined to function as irq4 ). kill reservation this input is used as a part of the storage reservation protocol when the mpc823e initiated a transaction as the result of a stwcx instruction. retry this input is used by the slave device to indicate that it is unable to accept the transaction. the mpc823e has to relinquish the ownership of the bus and initiate the transaction again after winning again in the bus arbitration. speaker out this output signal is used to provide a digital audio waveform to be driven to the systems speaker. d[0:31] see table 2-2 for pin breakout. data bus this bidirectional three-state signal provides the general-purpose data path between the mpc823e and all other devices. although the data path is a maximum of 32 bits wide, it can be dynamically sized to support 8-, 16-, or 32-bit transfers. d0 is the most-significant bit of the data bus. dp0 irq 3 c3 data parity 0 this bidirectional three-state signal provides parity generation and checking for the data bus lane d[0:7] by transferring to a slave device initiated by the mpc823e. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. interrupt request 3 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. dp1 irq4 d4 data parity 1 this bidirectional three-state signal provides parity generation and checking for the data bus lane d[8:15] by transferring to a slave device initiated by the mpc823e. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. interrupt request 4 this input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. it should be noted that the interrupt request signal that is sent to the interrupt controller is the logical and of this signal (if defined to function as irq4 ) and the kr/spkrout/ irq4 if defined to function as irq4 . table 2-1. signal descriptions (continued) signal pin number description
external signals 2-4 mpc823e reference manual motorola external signals 2 dp2 irq5 d3 data parity 2 this bidirectional three-state signal provides parity generation and checking for the data bus lane d[16:23] by transferring to a slave device initiated by the mpc823e. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. interrupt request 5 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. dp3 irq6 c2 data parity 3 this bidirectional three-state signal provides parity generation and checking for the data bus lane d[24:31] by transferring to a slave device initiated by the mpc823e. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. interrupt request 6 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. it should be noted that the interrupt request signal that is sent to the interrupt controller is the logical and of this signal (if defined to function as irq6 ) and the frz/irq6 if defined to function as irq6 . br b11 bus request this bidirectional signal is asserted low when a possible master is requesting ownership of the bus. when the mpc823e is configured to operate with the internal arbiter, this signal is configured as an input. however, when the mpc823e is configured to operate with an external arbiter, this signal is configured as an output and asserted every time a new transaction is intended to be initiated and no parking on the bus is granted. bg c10 bus grant this bidirectional signal is asserted low when the arbiter of the external bus grants the specific master ownership of the bus. when the mpc823e is configured to operate with the internal arbiter, this signal is configured as an output and asserted every time the external master asserts the br signal and its priority request is higher than any of the internal sources requiring the initiation of a bus transfer. however, when the mpc823e is configured to operate with an external arbiter, this signal is configured as an input. bb a11 bus busy this bidirectional signal is asserted low by a master to show that it owns the bus. the mpc823e asserts this signal after the bus arbiter grants it bus ownership and the bb signal is negated. irq6 frz a10 interrupt request 6 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. it should be noted that the interrupt request signal that is sent to the interrupt controller is the logical and of this signal (if defined to function as irq6 ) and the dp3/irq6 (if defined to function as irq6 .) freeze this output signal is asserted to indicate that the internal core is in debug mode. irq0 n1 interrupt request 0 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. it causes a non-maskable interrupt to the core. irq1 n2 interrupt request 1 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. irq7 n3 interrupt request 7 this input signal is one of the eight external signals that can request (by means of the internal interrupt controller) a service routine from the core. cs [0:5] see table 2-2 for pin breakout. chip select these output signals enable peripheral or memory devices at programmed addresses if they are appropriately defined in the memory controller. cs0 can be configured to be the global chip-select for the boot device. cs6 ce1_b c14 chip select 6 this output signal enables a peripheral or memory device at a programmed address if defined appropriately in the br6 and or6 of the memory controller. card enable 1 slot b this output signal enables even byte transfers when accesses to the pcmcia slot b are handled by the pcmcia interface. table 2-1. signal descriptions (continued) signal pin number description
external signals motorola mpc823e reference manual 2-5 external signals 2 cs7 ce2_b b15 chip select 7 this output signal enables a peripheral or memory device at a programmed address if defined appropriately in the br7 and or7 registers of the memory controller. card enable 2 slot b this output signal enables odd byte transfers when accesses to the pcmcia slot b are handled by the pcmcia interface. we0 bs_ab0 iord d16 write enable 0 this output signal is asserted when a write access to an external slave controlled by the gpcm in the memory controller is initiated by the mpc823e. we0 is asserted if the data lane d[0:7] contains valid data to be stored by the slave device. byte select 0 on upma or upmb this output signal is asserted as required by the upma or upmb in the memory controller whenever you program it. in a read or write transfer, the signal is only asserted if the data lane d[0:7] contains valid data. i/o device read this output signal is asserted when the mpc823e initiates a read access to a region controlled by the pcmcia interface. the signal is only asserted if the access is to a pc card i/o space. we1 bs_ab1 iowr e16 write enable 1 this output signal is asserted when the mpc823e initiates a write access to an external slave controlled by the gpcm in the memory controller. we1 is asserted if the data lane d[8:15] contains valid data to be stored by the slave device. byte select 1 on upma or upmb this output signal is asserted as required by the upma or upmb in the memory controller whenever you program it. in a read or write transfer, the signal is only asserted if the data lane d[8:15] contains valid data. i/o device write this output signal is asserted when the mpc823e initiates a write access to a region controlled by the pcmcia interface. the signal is only asserted if the access is to a pc card i/o space. we2 bs_ab2 pcoe d15 write enable 2 this output signal is asserted when the mpc823e initiates a write access to an external slave controlled by the gpcm in the memory controller. we2 is asserted if the data lane d[16:23] contains valid data to be stored by the slave device. byte select 2 on upma or upmb this output signal is asserted as required by the upma or upmb in the memory controller whenever you program it. in a read or write transfer, the signal is only asserted if the data lane d[16:23] contains valid data. pcmcia output enable this output signal is asserted when the mpc823e initiates a read access to a memory region under the control of the pcmcia interface. we3 bs_ab3 pcwe f13 write enable 3 this output signal is asserted when the mpc823e initiates a write access to an external slave controlled by the gpcm in the memory controller. we3 is asserted if the data lane d[24:31] contains valid data to be stored by the slave device. byte select 3 on upma or upmb this output signal is asserted as required by the upma or upmb in the memory controller whenever you program it. in a read or write transfer, the signal is only asserted if the data lane d[24:31] contains valid data. pcmcia write enable this output signal is asserted when the mpc823e initiates a write access to a memory region controlled by the pcmcia interface. gpl_a0 gpl_b0 e13 general-purpose line 0 on upma this output signal reflects the value specified in the upma in the memory controller when an external transfer to a slave is controlled by the user programmable machine a (upma). general-purpose line 0 on upmb this output signal reflects the value specified in the upmb in the memory controller when an external transfer to a slave is controlled by the user programmable machine b (upmb). gpl_a1 gpl_b1 oe c16 general-purpose line 1 on upma this output signal reflects the value specified in the upma in the memory controller when an external transfer to a slave is controlled by the user programmable machine a (upma). general-purpose line 1 on upmb this output signal reflects the value specified in the upmb in the memory controller when an external transfer to a slave is controlled by the user programmable machine b (upmb). output enable this output signal is asserted when the mpc823e initiates a read access to an external slave controlled by the gpcm in the memory controller. table 2-1. signal descriptions (continued) signal pin number description
external signals 2-6 mpc823e reference manual motorola external signals 2 gpl_a 2 gpl_b 2 cs2 c15 general-purpose line 2 on upma this output signal reflects the value specified in the upma in the memory controller when an external transfer to a slave is controlled by the user programmable machine a (upma). general-purpose line 2 on upmb this output signal reflects the value specified in the upmb in the memory controller when an external transfer to a slave is controlled by the user programmable machine b (upmb). chip select 2 this output signal enables a peripheral or memory device at a programmed address if defined appropriately in the br2 and or2 registers of the memory controller. gpl_a 3 gpl_b 3 cs3 d14 general-purpose line 3 on upma this output signal reflects the value specified in the upma in the memory controller when an external transfer to a slave is controlled by the user programmable machine a (upma). general-purpose line 3 on upmb this output signal reflects the value specified in the upmb in the memory controller when an external transfer to a slave is controlled by the user programmable machine b (upmb). chip select 3 this output signal enables a peripheral or memory device at a programmed address if defined appropriately in the br3 and or3 registers of the memory controller. gpl_a4 upwaita as d11 general-purpose line 4 on upma this output signal reflects the value specified in the upma in the memory controller when an external transfer to a slave is controlled by the user programmable machine a (upma). user programmable machine wait a this input signal is sampled when you need it and when an access to an external slave is controlled by the upma in the memory controller. address strobe this input pin is driven by an external asynchronous master to indicate a valid address on the a[6:31] lines. the memory controller in the mpc823e will synchronize this signal and control the memory device addressed if it is recognized to be under its control. gpl_b 4 upwaitb b13 general-purpose line 4 on upmb this output signal reflects the value specified in the upmb in the memory controller when an external transfer to a slave is controlled by the user programmable machine b (upmb). user programmable machine wait b this input signal is sampled when you need it and when an access to an external slave is controlled by the upmb in the memory controller. gpl_a5 c12 general-purpose line 5 on upma this output signal reflects the value specified in the upma in the memory controller when an external transfer to a slave is controlled by the user programmable machine a (upma). this signal can also be controlled by the upmb. poreset b3 power-on reset when asserted, this input signal causes the mpc823e to enter the power-on reset state. rstconf c5 reset configuration this input signal is sampled by the mpc823e during the assertion of the hreset signal. if it is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. when this signal is negated, the default configuration mode is adopted by the mpc823e. notice that the initial base address of internal registers is determined in this sequence. hreset b5 hard reset this open drain line, when asserted, causes the mpc823e to enter the hard reset state. sreset b4 soft reset this open drain line, when asserted, causes the mpc823e to enter the soft reset state. xtal a4 external crystal this output signal is one of the connections to an external crystal for the internal oscillator circuitry. extal a5 external crystal this signal is one of the connections to an external crystal for the internal oscillator circuitry. xfc b2 external filter capacitance this input signal is the connection pin to an external capacitor filter for the pll circuitry. clkout d1 clkout this output signal is the clock system frequency. extclk a6 external clock this input signal is the external input clock from an external source. table 2-1. signal descriptions (continued) signal pin number description
external signals motorola mpc823e reference manual 2-7 external signals 2 texp d5 timer expired this output signal reflects the status of the texps bit of the plprcr register in the clock interface. wait_b c4 wait slot b this input signal, if asserted low, causes the completion of a transaction to be delayed on the pcmcia-controlled slot b. ale_b dsck at1 b8 address latch enable b this output signal is asserted when the mpc823e initiates an access to a region under the control of the pcmcia socket b interface. development serial clock this input signal is the clock for the debug port interface. address type 1 this bidirectional three-state signal is driven by the mpc823e when it initiates a transaction on the external bus. when the transaction is initiated by the internal core, it indicates if the transfer is for problem or privilege state. ip_b0 iwp0 vfls0 a8 input port b 0 this input signal is sensed by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. instruction watchpoint 0 this output signal reports the detection of an instruction watchpoint in the program flow executed by the internal core. visible history buffer flushes status this output signal is output by the mpc823e when you need program instructions flow tracking. it reports the number of instructions flushed from the history buffer in the internal core. ip_b1 iwp1 vfls1 c8 input port b 1 this input signal is sensed by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. instruction watchpoint 1 this output signal reports the detection of an instruction watchpoint in the program flow executed by the internal core. visible history buffer flushes status this output signal is output by the mpc823e when you need program instructions flow tracking. it reports the number of instructions flushed from the history buffer in the internal core. ip_b2 iois16_b at2 d7 input port b 2 this input signal is sensed by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. i/o device b is 16 bits port size this input signal is monitored by the mpc823e when a pcmcia interface transaction is initiated to an i/o region in socket b within the pcmcia space. address type 2 this bidirectional three-state signal is driven by the mpc823e when it initiates a transaction on the external bus. when the transaction is initiated by the internal core, it indicates if the transfer is instruction or data. ip_b3 iwp2 vf2 a9 input port b 3 this input signal is monitored by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. instruction watchpoint 2 this output signal reports the detection of an instruction watchpoint in the program flow executed by the internal core. visible instruction queue flush status this output signal, together with vf0 and vf1, is output by the mpc823e when you need program instruction flow tracking. vfx reports the number of instructions flushed from the instruction queue in the internal core. ip_b4 lwp0 vf0 b9 input port b 4 this input signal is monitored by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. load/store watchpoint 0 this output signal reports the detection of a data watchpoint in the program flow executed by the internal core. visible instruction queue flushes status this output signal, together with vf1 and vf2, is output by the mpc823e when you need program instructions flow tracking. vf reports the number of instructions flushed from the instruction queue in the internal core. ip_b5 lwp1 vf1 c9 input port b 5 this input signal is monitored by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. load/store watchpoint 1 this output signal reports the detection of a data watchpoint in the program flow executed by the internal core. visible instruction queue flushes status this output signal, together with vf0 and vf2, is output by the mpc823e when you need program instructions flow tracking. vf reports the number of instructions flushed from the instruction queue in the internal core. table 2-1. signal descriptions (continued) signal pin number description
external signals 2-8 mpc823e reference manual motorola external signals 2 ip_b6 dsdi at0 c7 input port b 6 this input signal is sensed by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. development serial data input this input signal is the data in for the debug port interface. address type 0 this bidirectional three-state signal is driven by the mpc823e when it initiates a transaction on the external bus. if high (1), the transaction is the cpm. if low (0), the transaction initiator is the core. ip_b7 ptr at3 d8 input port b 7 this input signal is monitored by the mpc823e and its value and changes are reported in the pipr and pscr registers of the pcmcia interface. program trace this output signal is asserted by the mpc823e to indicate that an instruction fetch is taking place in order to allow program flow tracking. address type 3 this bidirectional three-state signal is driven by the mpc823e when it initiates a transaction on the external bus. when the transaction is initiated by the internal core, it indicates if the transfer is reserved for data transfers or a program trace indication for instructions fetch. modck1 op2 sts d6 mode clock 1 this input signal is sampled at poreset negation to configure the pll/clock mode of operation. output port 2 this output signal is generated by the mpc823e as a result of a write to the pgcrb register in the pcmcia interface. special transfer start this output signal is driven by the mpc823e to indicate the beginning of a transaction on the external bus or an internal transaction in show cycle mode. modck2 op3 dsdo b6 mode clock 2 this input signal is sampled at poreset negation to configure the pll/clock mode of operation. output port 3 this output signal is generated by the mpc823e as a result of a write to the pgcrb register in the pcmcia interface. development serial data output this output signal is the data out of the debug port interface. pa[15] usbrxd p16 general-purpose i/o port a bit 15 bit 15 of the general-purpose i/o port a. usbrxd the receive data input signal for the usb. pa[14] usboe r15 general-purpose i/o port a bit 14 bit 14 of the general-purpose i/o port a. usboe the output enable signal for the usb transmitter. pa[13] rxd2 r14 general-purpose i/o port a bit 13 bit 13 of the general-purpose i/o port a. rxd2 the receive data input signal for serial communication controller 2. pa[12] txd2 r13 general-purpose i/o port a bit 12 bit 12 of the general-purpose i/o port a. txd2 the transmit data output signal for serial communication controller 2. txd2 has open-drain capability. pa[9] l1txda smrxd2 n10 general-purpose i/o port a bit 11 bit 9 of the general-purpose i/o port a. l1txda the transmit data output signal for the serial interface time-division multiplex port a. this signal has open-drain capability. smrxd2 the serial management controller 2 receive data pin. pa[8] l1rxda smtxd2 t9 general-purpose i/o port a bit 8 bit 8 of the general-purpose i/o port a. l1rxda the receive data input signal for the serial interface time-division multiplex port a. smtxd2 the serial management controller 2 transmit data pin. pa[7] clk1 tin1 l1rclka brgo1 t8 general-purpose i/o port a bit 7 bit 7 of the general-purpose i/o port a. clk1 this input signal is one of the four clock pins that can be used to clock the serial communication controllers, serial management controllers, and usb. tin1 the timer 1 external clock pin. l1rclka the receive clock for the serial interface time-division multiplex port a. brgo1 the output clock of brg1. pa[6] clk2 tout1 tin3 l1rclkb p8 general-purpose i/o port a bit 6 bit 6 of the general-purpose i/o port a. clk2 this input signal is one of the four clock pins that can be used to clock the serial communication controllers, serial management controllers, and usb. tout1 the timer 1 output pin. tin3 the timer 3 external clock pin. l1rclkb the receive clock for the serial interface time-division multiplex port b. table 2-1. signal descriptions (continued) signal pin number description
external signals motorola mpc823e reference manual 2-9 external signals 2 pa[5] clk3 tin2 l1tclka brgo2 t6 general-purpose i/o port a bit 5 bit 5 of the general-purpose i/o port a. clk3 this input signal is one of the four clock pins that can be used to clock the serial communication controllers, serial management controllers, and usb. tin2 the timer 2 external clock input pin. l1tclka the transmit clock for the serial interface time-division multiplex port a. brgo2 the output clock of brg2. pa[4] clk4 tout2 tin4 l1tclkb r6 general-purpose i/o port a bit 4 bit 4 of the general-purpose i/o port a. clk4 this input signal is one of the four clock pins that can be used to clock the serial communication controllers, serial management controllers, and usb. tout2 the timer 2 output pin. tin4 the timer 4 external clock pin. l1tclkb the transmit clock for the serial interface time-division multiplex port a. pb[31] spisel lcd_a n14 general-purpose i/o port b bit 31 bit 31 of the general-purpose i/o port b. spisel the serial peripheral interface slave select input pin. lcd_a this is one of the lcd controllers three extension data bits, which are used to drive an active lcd panel. when using a 12-bit bus instead of a 9-bit bus, the lcd_a signal is the least-significant bit of the red 4-bit code. the red portion of the bus consists of ld[0:2] and lcd_a. pb[30] spiclk txd3 p15 general-purpose i/o port b bit 30 bit 30 of the general-purpose i/o port b. spiclk the serial peripheral interface output clock when it is configured as a master or serial peripheral interface input clock when it is configured as a slave. txd3 the transmit data output signal for serial communication controller 3. txd3 has open-drain capability. pb[29] spimosi rxd3 p14 general-purpose i/o port b bit 29 bit 29 of the general-purpose i/o port b. spimosi the serial peripheral interface output data when it is configured as a master or serial peripheral interface input data when it is configured as a slave. rxd3 the receive data input signal for serial communication controller 3. pb[28] spimiso brgo3 t15 general-purpose i/o port b bit 28 bit 28 of the general-purpose i/o port b. spimiso the serial peripheral interface input data when it is configured as a master or serial peripheral interface output data when it is configured as a slave. brgo3 the output clock of brg3. pb[27] i2csda brgo1 t14 general-purpose i/o port b bit 27 bit 27 of the general-purpose i/o port b. i2csda the i 2 c serial data pin. this pin is bidirectional and should be configured as an open-drain output. brgo1 the output clock of brg1. pb[26] i2cscl brgo2 p12 general-purpose i/o port b bit 26 bit 26 of the general-purpose i/o port b. i2cscl the i 2 c serial clock pin. this pin is bidirectional and should be configured as an open-drain output. brgo2 the output clock of brg2. pb[25] smtxd1 txd3 n11 general-purpose i/o port b bit 25 bit 25 of the general-purpose i/o port b. smtxd1 the serial management controller 1 transmit data output pin. txd3 the transmit data output signal for serial communication controller 3. txd3 has open-drain capability. pb[24] smrxd1 rxd3 l1rxdb t11 general-purpose i/o port b bit 24 bit 24 of the general-purpose i/o port b. smrxd1 the serial management controller 1 receive data input pin. rxd3 the receive data input signal for serial communication controller 3. l1rxdb the receive data input signal for the serial interface time-division multiplex port b. pb[23] smsyn1 cts3 sdack1 l1rsyncb t10 general-purpose i/o port b bit 23 bit 23 of the general-purpose i/o port b. smsyn1 the serial management controller 1 external sync input pin. cts3 the clear to send modem line for serial communication controller 3. sdack1 the sdma acknowledge 1 output pin that is used as a peripheral interface signal for idma emulation. l1rsyncb the transmit sync input for the serial interface time-division multiplex port b. table 2-1. signal descriptions (continued) signal pin number description
external signals 2-10 mpc823e reference manual motorola external signals 2 pb[22] smsyn2 sdack2 l1tsyncb r9 general-purpose i/o port b bit 22 bit 22 of the general-purpose i/o port b. smsyn2 the serial management controller 2 external sync input pin. sdack2 the sdma acknowledge 2 output pin that is used as a peripheral interface signal for idma emulation. l1tsyncb the receive sync input for the serial interface time-division multiplex port b. pb[19] l1st1 lcd_b r7 general-purpose i/o port b bit 19 bit 19 of the general-purpose i/o port b. l1st1 one of eight output strobes that can be generated by the serial interface. lcd_b this is one of the lcd controllers three extension data bits, which are used to drive an active lcd panel. when using a 12-bit bus instead of a 9-bit bus, the lcd_b signal is the least-significant bit of the green 4-bit code. the green portion of the bus consists of ld[3:5] and lcd_b. pb[18] rts2 l1st2 p7 general-purpose i/o port b bit 18 bit 18 of the general-purpose i/o port b. rts2 the request to send modem signal for serial communication controller 2. l1st2 one of eight output strobes that can be generated by the serial interface. pb[17] l1st3 lcd_c n7 general-purpose i/o port b bit 17 bit 17 of the general-purpose i/o port b. l1st3 one of eight output strobes that can be generated by the serial interface. lcd_c this is one of the lcd controllers three extension data bits, which are used to drive an active lcd panel. when using a 12-bit bus instead of a 9-bit bus, the lcd_c signal is the least-significant bit of the blue 4-bit code. the blue portion of the bus consists of ld[6:8] and lcd_c. pb[16] l1rqa l1st4 r5 general-purpose i/o port b bit 16 bit 16 of the general-purpose i/o port b. l1rqa the d-channel request signal for the serial interface time-division multiplex port a. l1st4 one of eight output strobes that can be generated by the serial interface. pc[15] dreq1 l1st5 l1txdb r16 general-purpose i/o port c bit 15 bit 15 of the general-purpose i/o port c. dreq1 the idma channel 1 request input signal. l1st5 one of eight output strobes that can be generated by the serial interface. l1txdb the transmit data input signal for the serial interface time-division multiplex port b. pc[14] dreq2 rts2 l1st6 t16 general-purpose i/o port c bit 14 bit 14 of the general-purpose i/o port c. dreq2 the idma channel 2 request input signal. rts2 the request to send modem signal for serial communication controller 2. l1st6 one of eight output strobes that can be generated by the serial interface. pc[13] l1st7 rts3 p13 general-purpose i/o port c bit 13 bit 13 of the general-purpose i/o port c. l1st7 one of eight output strobes that can be generated by the serial interface. rts3 the request to send modem signal for serial communication controller 3. pc[12] l1rqa l1st8 t13 general-purpose i/o port c bit 12 bit 12 of the general-purpose i/o port c. l1rqa the d-channel request signal for the serial interface time-division multiplex port a. l1st8 one of eight output strobes that can be generated by the serial interface. pc[11] usbrxp r10 general-purpose i/o port c bit 11 bit 11 of the general-purpose i/o port c. usbrxp used with usbrxn, this signal is used by the usb to detect a single-ended zero and the interconnection speed. pc[10] tgate1 usbrxn p9 general-purpose i/o port c bit 10 bit 10 of the general-purpose i/o port c. tgate1 the timer1/timer2 gate signal. usbrxn used with usbrxp, this signal is used by the usb to detect a single-ended zero and the interconnection speed. pc[9] cts2 r8 general-purpose i/o port c bit 9 bit 9 of the general-purpose i/o port c. cts2 the clear to send modem line for serial communication controller 2. pc[8] cd2 tgate1 n8 general-purpose i/o port c bit 8 bit 8 of the general-purpose i/o port c. cd2 the carrier detect modem line for serial communication controller 2. tgate1 the timer1/timer2 gate signal. table 2-1. signal descriptions (continued) signal pin number description
external signals motorola mpc823e reference manual 2-11 external signals 2 pc[7] usbtxp t5 general-purpose i/o port c bit 7 bit 7 of the general-purpose i/o port c. usbtxp this output signal, in conjunction with usbtxn, are the transmit lines of the usb. pc[6] usbtxn n6 general-purpose i/o port c bit 6 bit 6 of the general-purpose i/o port c. usbtxn this output signal, in conjunction with usbtxp, are the transmit lines of the usb. pc[5] l1tsynca sdack1 cts3 p6 general-purpose i/o port c bit 5 bit 5 of the general-purpose i/o port c. l1tsynca the transmit sync input for the serial interface time-division multiplex port a. sdack1 the sdma acknowledge 1output pin that is used as a peripheral interface signal for idma emulation. cts3 the clear to send modem line for serial communication controller 3. pc[4] l1rsynca cd3 t4 general-purpose i/o port c bit 4 bit 4 of the general-purpose i/o port c. l1rsynca the receive sync input for the serial interface time-division multiplex port a. cd3 the carrier detect modem line for serial communication controller 3. pd[15] ld8 vd7 r4 general-purpose i/o port d bit 15 bit 15 of the general-purpose i/o port d. ld8 one of the 12 data bus bits used to drive the lcd panel. vd7 one of the data bus bits of the video controller used for driving the video encoder. pd[14] ld7 vd6 t3 general-purpose i/o port d bit 14 bit 14 of the general-purpose i/o port d. ld7 one of the 12 data bus bits used to drive the lcd panel. vd6 one of the data bus bits of the video controller used for driving the video encoder. pd[13] ld6 vd5 p5 general-purpose i/o port d bit 13 bit 13 of the general-purpose i/o port d. ld6 one of the 12 data bus bits used to drive the lcd panel. vd5 one of the data bus bits of the video controller used for driving the video encoder. pd[12] ld5 vd4 r3 general-purpose i/o port d bit 12 bit 12 of the general-purpose i/o port d. ld5 one of the 12 data bus bits used to drive the lcd panel. vd4 one of the data bus bits of the video controller used for driving the video encoder. pd[11] ld4 vd3 n5 general-purpose i/o port d bit 11 bit 11 of the general-purpose i/o port d. ld4 one of the 12 data bus bits used to drive the lcd panel. vd3 one of the data bus bits of the video controller used for driving the video encoder. pd[10] ld3 vd2 t2 general-purpose i/o port d bit 10 bit 10 of the general-purpose i/o port d. ld3 one of the 12 data bus bits used to drive the lcd panel. vd2 one of the data bus bits of the video controller used for driving the video encoder. pd[9] ld2 vd1 p4 general-purpose i/o port d bit 9 bit 9 of the general-purpose i/o port d. ld2 one of the 12 data bus bits used to drive the lcd panel. vd1 one of the data bus bits of the video controller used for driving the video encoder. pd[8] ld1 vd0 t1 general-purpose i/o port d bit 8 bit 8 of the general-purpose i/o port d. ld1 one of the 12 data bus bits used to drive the lcd panel. vd0 one of the data bus bits of the video controller used for driving the video encoder. pd[7] ld0 field r2 general-purpose i/o port d bit 7 bit 7 of the general-purpose i/o port d. ld0 one of the 12 data bus bits used to drive the lcd panel. field the line the video controller uses to signal which of the two fields is the current one. table 2-1. signal descriptions (continued) signal pin number description
external signals 2-12 mpc823e reference manual motorola external signals 2 pd[6] lcd_ac loe blank r1 general-purpose i/o port d bit 6 bit 6 of the general-purpose i/o port d. lcd_ac this output signal from the lcd controller toggles once every programmable number of frames. it is used with passive panels. loe the output enable signal that is used with tft panels. blank the video controller uses this signal to let the video encoder know that the current cycle is a blank type. pd[5] frame vsync p2 general-purpose i/o port d bit 5 bit 5 of the general-purpose i/o port d. frame the output signal from the video controller that marks the beginning of a new frame. vsync the output signal from the lcd controller that marks the beginning of a new frame. pd[4] load hsync p3 general-purpose i/o port d bit 4 bit 4 of the general-purpose i/o port d. load the output signal from the video controller that marks the beginning of a new display line. hsync the output signal from the lcd controller that marks the beginning of a new frame. pd[3] shift/clk clk n4 general-purpose i/o port d bit 3 bit 3 of the general-purpose i/o port d. shift/clk this output signal is used to generate the shift clock timing to the lcd panel when using the lcd controller. the direction is defined when you program it. clk when the video controller is used, the clk function can either be an output clock to drive the video encoder or an external input clock from the video encoder to drive the video controller. the direction is defined when you program it. power supply see table 2-2 for pin breakout. vddl power supply of the internal logic. vddh power supply of the i/o buffers and certain parts of the clock control. vddsyn power supply of the phase-locked loop circuitry. vsssyn power supply of the phase-locked loop ground. vsssyn1 power supply of the phase-locked loop ground. gnd power supply ground. kapwr power supply of the internal oscillator, real-time clock, periodic interrupt timer, decrementer, and timebase. tck dsck t12 test clock this input signal is the clock of the jtag interface. development serial clock this input signal is the clock for the debug port interface. tms r12 test mode select this input signal controls the tap machine sequence in the jtag interface. tdi dsdi r11 test data input this input signal is the data in the jtag interface. development serial data input this input signal is the data for the debug port interface. tdo dsdo n12 test data output this three-state output signal is the data out of the jtag interface. development serial data output this output signal is the data out of the debug port interface. trst p11 test reset this input signal is the asynchronous reset of the tap machine on the jtag interface. n/c see table 2-2 for pin breakout. no connect these pins are not connected. table 2-1. signal descriptions (continued) signal pin number description
external signals motorola mpc823e reference manual 2-13 external signals 2 table 2-2. pin breakout signal pin number address bus pins a6 m13 a7 n15 a8 n16 a9 m15 a10 l13 a11 m16 a12 m14 a13 l14 a14 l15 a15 l16 a16 k14 a17 k13 a18 g13 a19 k15 a20 j15 a21 j14 a22 g14 a23 h15 a24 h13 a25 h14 a26 f14 a27 k16 a28 g16 a29 h16 a30 g15 a31 f16
external signals 2-14 mpc823e reference manual motorola external signals 2 data bus pins d0 m1 d1 l1 d2 j2 d3 j1 d4 l2 d5 h1 d6 f1 d7 e1 d8 m2 d9 k2 d10 k3 d11 k1 d12 m4 d13 m3 d14 j3 d15 j4 d16 h2 d17 k4 d18 h3 d19 g2 d20 g3 d21 f2 d22 h4 d23 l4 d24 f3 d25 g4 d26 e4 d27 l3 d28 f4 d29 e2 d30 d2 d31 e3 table 2-2. pin breakout (continued) signal pin number
external signals motorola mpc823e reference manual 2-15 external signals 2 chip select pins cs0 d12 cs1 a14 cs2 b14 cs3 a15 cs4 b16 cs5 d13 cs6 c14 cs7 b15 power supply pins vddh e5C12, f5, f12, g5, g12, h5, h12, j5, j12, k5, k12, l5, l12, m5Cm12 vddl a7, g1, j16, t7 vddsyn b1 kapwr a3 vsssyn a1 vsssyn1 a2 gnd f6Cf11, g6Cg11, h6Ch11, j6Cj11, k6Ck11, l6Cl11 no connect pins n/c a16, c1, c6, e14, j13, n9, n13, p1, p10 table 2-2. pin breakout (continued) signal pin number
motorola mpc823e reference manual 3-1 memory map 3 section 3 memory map this section discusses the internal memory map (including key registers) of the mpc823e. each memory resource is mapped within a contiguous block of 16k storage. the location of this block within the global 4g real storage space can be mapped on 64k resolution through an implementation specific special register called the internal memory map register (immr). refer to section 12.12.1.2 internal memory map register for more information. table 3-1. mpc823e internal memory map internal address register size (in bits) page number location system interface unit 000 siumcrsiu module configuration register 32 12-30 004 sypcrsystem protection control register 32 12-35 008 to 00d resreserved 00e swsrsoftware service register 16 12-27 010 sipendsiu interrupt pending register 32 12-7 014 simasksiu interrupt mask register 32 12-8 018 sielsiu interrupt edge/level register 32 12-9 01c sivecsiu interrupt vector register 32 12-10 020 tesrtransfer error status register 32 12-36 024 to 02f resreserved 030 sdcrsdma configuration register 32 16-85 034 to 07f resreserved pcmcia 080 pbr0pcmcia interface base register 0 32 17-16 084 por0pcmcia interface option register 0 32 17-17 088 pbr1pcmcia interface base register 1 32 17-16 08c por1pcmcia interface option register 1 32 17-17 090 pbr2pcmcia interface base register 2 32 17-16 094 por2pcmcia interface option register 2 32 17-17 098 pbr3pcmcia interface base register 3 32 17-16
memory map 3-2 mpc823e reference manual motorola memory map 3 09c por3pcmcia interface option register 3 32 17-17 0a0 pbr4pcmcia interface base register 4 32 17-16 0a4 por4pcmcia interface option register 4 32 17-17 0a8 pbr5pcmcia interface base register 5 32 17-16 0ac por5pcmcia interface option register 5 32 17-17 0b0 pbr6pcmcia interface base register 6 32 17-16 0b4 por6pcmcia interface option register 6 32 17-17 0b8 pbr7pcmcia interface base register 7 32 17-16 0bc por7pcmcia interface option register 7 32 17-17 0c0 to 0e3 resreserved 0e4 pgcrbpcmcia interface general control register b 32 17-15 0e8 pscrpcmcia interface status change register 32 17-11 0ec to 0ef resreserved 0f0 piprpcmcia interface input pins register 32 17-9 0f4 to 0f7 resreserved 0f8 perpcmcia interface enable register 32 17-13 0fc to 0ff resreserved memory controller 100 br0base register bank 0 32 15-9 104 or0option register bank 0 32 15-11 108 br1base register bank 1 32 15-9 10c or1option register bank 1 32 15-11 110 br2base register bank 2 32 15-9 114 or2option register bank 2 32 15-11 118 br3base register bank 3 32 15-9 11c or3option register bank 3 32 15-11 120 br4base register bank 4 32 15-9 124 or4option register bank 4 32 15-11 128 br5base register bank 5 32 15-9 12c or5option register bank 5 32 15-11 130 br6base register bank 6 32 15-9 134 or6option register bank 6 32 15-11 table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map motorola mpc823e reference manual 3-3 memory map 3 138 br7base register bank 7 32 15-9 13c or7option register bank 7 32 15-11 140 to 163 resreserved 164 marmemory address register 32 15-26 168 mcrmemory command register 32 15-17 16c to 16f resreserved 170 mamrmachine a mode register 32 15-19 174 mbmrmachine b mode register 32 15-22 178 mstatmemory status register 16 15-15 17a mptprmemory periodic timer prescaler 16 15-27 17c mdrmemory data register 32 15-26 180 to 1ff resreserved system integration timers 200 tbscrtimebase status and control register 16 12-16 204 tbrefutimebase reference register upper 32 12-15 208 tbrefltimebase reference register lower 32 12-15 20c to 21f resreserved 220 rtcscreal-time clock status and control register 16 12-18 224 rtcreal-time clock register 32 12-19 228 rtsecreal-time clock alarm seconds register 32 12-20 22c rtcalreal-time clock alarm register 32 12-21 230 to 23f resreserved 240 piscrperiodic interrupt status and control register 16 12-23 244 pitcperiodic interrupt timer count register 32 12-24 248 pitrperiodic interrupt timer register 32 12-25 24c to 27f resreserved clocks and reset 280 sccrsystem clock and reset control register 32 5-3 284 plprcrpll, low-power and reset control register 32 5-7 288 rsrreset status register 32 4-5 28c to 2ff resreserved table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map 3-4 mpc823e reference manual motorola memory map 3 system integration timers keys 300 tbscrktimebase status and control register key 32 5-27 304 tbreffuktimebase reference register upper key 32 5-27 308 tbrefflktimebase reference register lower key 32 5-27 30c tbktimebase and decrementer register key 32 5-27 310 to 31f resreserved 320 rtcsckreal-time clock status and control register key 32 5-27 324 rtckreal-time clock register key 32 5-27 328 rtseckreal-time alarm seconds key 32 5-27 32c rtcalkreal-time alarm register key 32 5-27 330 to 33f resreserved 340 piscrkperiodic interrupt status and control register key 32 5-27 344 pitckperiodic interrupt count register key 32 5-27 348 to 37f resreserved clocks and reset keys 380 sccrksystem clock control key 32 5-27 384 plprcrkpll, low power and reset control register key 32 5-27 388 rsrkreset status register key 32 5-27 38c to 7ff resreserved video controller 800 vccrvideo controller configuration register 16 19-5 802 to 803 resreserved 16 804 vsrvideo status register 8 19-7 805 resreserved 8 806 vcmrvideo controller command register 8 19-8 807 resreserved 8 808 vbcbvideo background color buffer register 32 19-9 80c to 80f resreserved 16 810 vfcr0video frame configuration register (set 0) 32 19-10 814 vfaa0video frame buffer a start address register (set 0) 32 19-11 818 vfba0video frame buffer b start address register (set 0) 32 19-12 table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map motorola mpc823e reference manual 3-5 memory map 3 81c vfcr1video frame configuration register (set 1) 32 19-13 820 vfaa1video frame buffer a start address register (set 1) 32 19-14 824 vfba1video frame buffer b start address register (set 1) 32 19-15 828 to 83f resreserved lcd controller 840 lccrlcd panel configuration register 32 18-21 844 lchcrlcd horizontal control register 32 18-23 848 lcvcrlcd vertical configuration register 32 18-25 84c to 84f resreserved 850 lcfaalcd frame buffer a start address 32 18-27 854 lcfbalcd frame buffer b start address 32 18-28 858 lcsrlcd status register 8 18-29 859 to 85f resreserved i 2 c controller 860 i2modi 2 c mode register 8 16-468 864 i2addi 2 c address register 8 16-473 868 i2brgi 2 c baud rate generator register 8 16-474 86c i2comi 2 c command register 8 16-474 870 i2ceri 2 c event register 8 16-475 874 i2cmri 2 c mask register 8 16-476 875 to 8ff resreserved dma controller 900 to 903 resreserved 904 sdarsdma address register 32 16-89 908 sdsrsdma status register (dsp interrupts) 8 16-87 909 to 90b resreserved 90c sdmrsdma mask register (dsp interrupts) 8 16-34, 16-88 90d to 90f resreserved 910 idsr1idma1 status register 8 16-94 911 to 913 resreserved table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map 3-6 mpc823e reference manual motorola memory map 3 914 idmr1idma1 mask register 8 16-95 915 to 917 resreserved 918 idsr2idma2 status register 8 16-94 919 to 91b resreserved 91c idmr2idma2 mask register 8 16-95 91d to 92f resreserved communications processor module interrupt controller 930 civrcpm interrupt vector register 16 16-512 932 to 93f resreserved 940 cicrcpm interrupt configuration register 32 16-507 944 ciprcpm interrupt pending register 32 16-509 948 cimrcpm interrupt mask register 32 16-510 94c cisrcpm interrupt in-service register 32 16-511 parallel ports 950 padirport a data direction register 16 16-481 952 paparport a pin assignment register 16 16-481 954 paodrport a open-drain register 16 16-480 956 padatport a data register 16 16-480 958 to 95f resreserved 960 pcdirport c data direction register 16 16-493 962 pcparport c pin assignment register 16 16-494 964 pcsoport c special options register 16 16-494 966 pcdatport c data register 16 16-493 968 pcintport c interrupt control register 16 16-496 96a to 96f resreserved 970 pddirport d data direction register 16 16-498 972 pdparport d pin assignment register 16 16-499 974 resreserved 976 pddatport d data register 16 16-498 978 to 97f resreserved table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map motorola mpc823e reference manual 3-7 memory map 3 cpm timers 980 tgcrtimer global configuration register 16 16-77 982 to 98f resreserved 990 tmr1timer1 mode register 16 16-78 992 tmr2timer2 mode register 16 16-78 994 trr1timer1 reference register 16 16-79 996 trr2timer2 reference register 16 16-79 998 tcr1timer1 capture register 16 16-80 99a tcr2timer2 capture register 16 16-80 99c tcn1timer1 counter register 16 16-80 99e tcn2timer2 counter register 16 16-80 9a0 tmr3timer3 mode register 16 16-78 9a2 tmr4timer4 mode register 16 16-78 9a4 trr3timer3 reference register 16 16-79 9a6 trr4timer4 reference register 16 16-79 9a8 tcr3timer3 capture register 16 16-80 9aa tcr4timer4 capture register 16 16-80 9ac tcn3timer3 counter register 16 16-80 9ae tcn4timer4 counter register 16 16-80 9b0 ter1timer1 event register 16 16-81 9b2 ter2timer2 event register 16 16-81 9b4 ter3timer3 event register 16 16-81 9b6 ter4timer4 event register 16 16-81 9b8 to 9bf resreserved communication processor module 9c0 cpcrcommunication processor module command register 16 16-9 9c2 to 9c3 resreserved 16 9c4 to 9c7 rccr/rmdsrisc controller configuration register and risc microcode development support control register 32 16-7 9c8 to 9cb resreserved 32 9cc rctr1risc controller trap register 1 16 9ce rctr2risc controller trap register 2 16 table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map 3-8 mpc823e reference manual motorola memory map 3 9d0 rctr3risc controller trap register 3 16 9d2 rctr4risc controller trap register 4 16 9d4 to 9d5 resreserved 9d6 rterrisc timer event register 16 16-23 9d8 to 9d9 resreserved 9da to 9db rtmrrisc timer mask register 16 16-23 9dc to 9ef resreserved baud rate generators 9f0 brgc1brg1 configuration register 32 16-160 9f4 brgc2brg2 configuration register 32 16-160 9f8 brgc3brg3 configuration register 32 16-160 9fc brgc4brg4 configuration register 32 16-160 universal serial bus a00 usmodusb mode register 8 16-365 a01 usadrusb slave address register 8 16-371 a02 uscomusb command register 8 16-372 a03 resreserved 8 a04 usep0usb endooint configuration 0 register 16 16-373 a06 usep1usb endooint configuration 1 register 16 16-373 a08 usep2usb endooint configuration 2 register 16 16-373 a0a usep3usb endooint configuration 3 register 16 16-373 a0c to a0f resreserved a10 usberusb event register 16 16-376 a12 resreserved 16 a14 usbmrusb mask register 16 16-377 a16 resreserved 8 a17 usbsusb status register 8 16-377 a18 to a1f resreserved table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map motorola mpc823e reference manual 3-9 memory map 3 serial communication controller 2 a20 gsmr_lscc2 general mode low register 32 16-166 a24 gsmr_hscc2 general mode high register 32 16-166 a28 psmrscc2 protocol-specific mode register 16 16-176 16-217 (uart) 16-242 (hdlc) 16-279 (ahdlc) 16-309 (trans) a2a to a2b resreserved 16 a2c todrscc2 transmit-on-demand register 16 16-177 a2e dsrscc2 data synchronization register 16 16-177 a30 sccescc2 event register 16 16-187 16-227 (uart) 16-250 (hdlc) 16-284 (ahdlc) 16-314 (trans) a32 resreserved 16 a34 sccmscc2 mask register 16 16-187 16-229 (uart) 16-253 (hdlc) 16-316 (trans) a36 resreserved 8 a37 sccsscc2 status register 8 16-187 16-230 (uart) 16-254 (hdlc) 16-316 (trans) a38 irmodescc2 infra-red mode register 16 16-294 a3a irsipscc2 infra-red serial interaction pulse control register 16 16-296 a3c to a3f resreserved serial communication controller 3 a40 gsmr_l scc3 general mode low register 32 16-166 a44 gsmr_h scc3 general mode high register 32 16-166 a48 psmrscc3 protocol-specific mode register 16 16-176 16-217 (uart) 16-242 (hdlc) 16-279 (ahdlc) 16-309 (trans) a4a-a4b reserved 16 a4c todrscc3 transmit-on-demand register 16 16-177 a4e dsrscc3 data synchronization register 16 16-177 table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map 3-10 mpc823e reference manual motorola memory map 3 a50 sccescc3 event register 16 16-187 16-227 (uart) 16-250 (hdlc) 16-284 (ahdlc) 16-314 (trans) a52-a53 reserved 16 a54 sccmscc3 mask register 16 16-187 16-229 (uart) 16-253 (hdlc) 16-316 (trans) a56 reserved 8 a57 sccsscc3 status register 8 16-187 16-230 (uart) 16-254 (hdlc) 16-316 (trans) a58-a81 reserved serial management controller 1 a82 smcmrsmc mode register 16 16-384 16-398 (uart) 16-416 (trans) 16-431 (gci) a84 resreserved 16 a86 smcesmc event register 8 16-405 (uart) 16-422 (trans) 16-432 (gci) a87 to a89 resreserved a8a smcmsmc mask register 8 16-407 (uart 16-423 (trans) 16-433 (gci) a8b to a91 resreserved serial management controller 2 a92 smcmrsmc mode register 16 16-384 16-398 (uart) 16-416 (trans) 16-431 (gci) a94 resreserved 16 a96 smcesmc event register 8 16-405 (uart) 16-422 (trans) 16-432 (gci) a97 to a99 resreserved a9a smcmsmc mask register 8 16-407 (uart 16-423 (trans) 16-433 (gci) a9b to a9f resreserved table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map motorola mpc823e reference manual 3-11 memory map 3 serial peripheral interface aa0 spmodespi mode register 16 16-443 aa2 resreserved 16 aa6 spiespi event register 8 16-452 aa7 to aa9 resreserved aaa spimspi mask register 8 16-453 aab resreserved 16 aad spcomspi command register 8 16-451 aae to ab7 resreserved port b ab8 pbdirport b data direction register 32 16-488 abc pbparport b pin assignment register 32 16-489 ac0 pbodrport b open-drain register 32 16-485 ac4 pbdatport b data register 32 16-487 serial interface ae0 simodeserial interface mode register 32 16-129 ae4 sigmrserial interface global mode register 8 16-128 ae5 resreserved 8 ae6 sistrserial interface status register 8 16-140 ae7 sicmrserial interface command register 8 16-139 ae8 to aeb resreserved aec sicrserial interface clock route register 32 16-136 af0 sirpserial interface ram pointer register 32 16-141 af4 to aff resreserved specialized ram b00 to bff vcramvideo controller ram array 256 bytes 19-16 c00 to dff siramserial interface ram 512 bytes 16-122 e00 to fff lcolrlcd color ram 512 bytes 18-30 1000 to 1fff resreserved table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
memory map 3-12 mpc823e reference manual motorola memory map 3 dual-port ram 2000 to 2fff dpramdual-port ram 4,096 bytes 3000 to 3bff dpramdual-port ram expansion 3c00 to 3fff pramparameter ram 1,024 bytes table 3-1. mpc823e internal memory map (continued) internal address register size (in bits) page number location
motorola mpc823e reference manual 4-1 reset 4 section 4 reset the reset block of the mpc823e has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. the memory controller, system protection logic, interrupt controller, and parallel i/o pins are initialized only on hard reset. soft reset initializes the internal logic while maintaining the system configuration. table 4-1. possible reset results reset source reset effect reset logic and pll state reset system config reset clock module reset hreset pin driven debug port config other internal logic reset sreset pin driven power-on reset ??????? external hard reset loss-of-lock software watchdog check stop debug port hard reset jtag reset ?????? external soft reset debug port soft reset ? ??? note: ? indicates that the logic circuitry is reset or the appropriate pin is driven by the source. indicates that the logic circuitry is not affected.
reset 4-2 mpc823e reference manual motorola reset 4 4.1 types of reset the mpc823e has several types of inputs to the reset logic: ? power-on reset ? external hard reset ? internal hard reset o loss of lock o software watchdog reset o checkstop reset o debug port hard reset o jtag reset ? external soft reset ? internal soft reset o debug port soft reset o jtag soft reset all of these reset sources are fed into the reset controller and, depending on the source of the reset, different actions are taken. the reset status register reflects the last source to cause a reset. 4.1.1 power-on reset poreset (power-on reset) is an active low input pin. in a system with power-down low-power mode, this pin must only be activated when a voltage in the keep-alive power (kapwr) rail fails. when this pin is asserted, the modck bits are sampled and the phase-locked loop multiplication factor and pitrtclk and tmbclk sources are changed to their default values. when this pin is negated, internal modck values are unchanged. the poreset pin must be asserted for a minimum of 3 microseconds. after detecting this assertion, the mpc823e enters the power-on reset state and stays there until the following events occur: ? the internal pll enters the lock state and the system clock is active ? the poreset pin is negated when poreset is asserted, the mpc823e enters the power-on reset (por) state in which sreset and hreset are asserted by the core. when the mpc823e remains in por, the extension counter of 512 is reset, and the modck pins are sampled when por pin is negated. after the negation of poreset and the pll locks, the core enters the state of internal initiated hreset and continues driving the hreset and sreset pins for 512 cycles. when the timer expires, which is usually after the 512 cycles, the configuration is sampled from the data pins and the core stops driving the pins. an external pull-up resistor should drive the hreset and sreset pins high. after the pins are negated, a 16-cycle period passes before the presence of an external (hard/soft) reset is tested. refer to section 4.3.1 hard reset for more information.
reset motorola mpc823e reference manual 4-3 reset 4 4.1.2 external hard reset hreset (hard reset) is a bidirectional, active low i/o pin. the mpc823e can only detect an external assertion of hreset if it occurs while the mpc823e is not asserting reset. during hreset , sreset is asserted. hreset is an open-collector type of pin. sreset (soft reset) is a bidirectional, active low i/o pin. the mpc823e can only detect an external assertion of sreset if it occurs while the mpc823e is not asserting reset. the sreset is also an open-collector type of pin. when an external hreset is asserted, the core starts driving the hreset and sreset for 512 cycles. when the timer expires, after 512 cycles, the configuration is sampled from the data pins and the core stops driving the hreset and sreset pins. an external pull-up resistor should drive the pins high and once they are negated, a 16-cycle period passes before the presence of an external (hard/soft) reset is tested. refer to section 4.3.1 hard reset for more information. 4.1.3 internal hard reset when the core finds a reason to assert hreset, it starts driving the hreset and sreset pins for 512 cycles. when the timer expires, after the 512 cycles, the configuration is sampled from data pins and the core stops driving the pins. an external pull-up resistor should drive the hreset and sreset pins high and once they are negated a 16-cycle period passes before the presence of an external (hard/soft) reset is tested. refer to section 4.3.1 hard reset for more information. the causes of internal hard reset are as follows: ? loss of lock ? software watchdog reset ? checkstop reset ? debug port hard reset ? jtag reset 4.1.3.1 loss of lock. if the pll detects a loss of lock, erroneous external bus operation occurs if synchronous external devices use the core input clock. erroneous operation could also occur if devices with a pll use the core clockout. this source of reset can be asserted if the lolre bit in the pll low-power and reset control register is set. the enabled pll loss-of-lock event generates an internal hard reset sequence. 4.1.3.2 software watchdog reset. after the core watchdog counts to zero, a software watchdog reset is asserted. the enabled software watchdog event then generates an internal hard reset sequence. 4.1.3.3 checkstop reset. if the core enters a checkstop state and the checkstop reset is enabled, the checkstop reset is asserted. the enabled checkstop event then generates an internal hard reset sequence.
reset 4-4 mpc823e reference manual motorola reset 4 4.1.3.4 debug port hard reset. when the development port receives a hard reset request from the development tool, an internal hard reset sequence is generated. in this case, the development tool must reconfigure the debug port. see section 20.2.1.2.6 detecting the trace window end address for more information. 4.1.3.5 jtag reset. when the jtag logic asserts the jtag soft reset signal, an internal soft reset sequence will be generated. 4.1.4 external soft reset when an external sreset is asserted, the core starts driving the sreset pin. when the timer expires, after 512 cycles, the debug port configuration is sampled from the dsdi and dsck pins and the core stops driving the pin. an external pull-up resistor should drive it high and once it is negated a 16-cycle period passes before the presence of an external soft reset is tested. 4.1.5 internal soft reset when the core finds a reason to assert sreset, it starts driving the sreset pin. when the timer expires, after 512 cycles, the debug port configuration is sampled from the dsdi and dsck pins and the core stops driving the sreset pin. an external pull-up resistor should drive the pin high and once it is negated a 16-cycle period passes before the presence of an external soft reset is tested. jtag and the debug port cause an internal soft reset. 4.1.5.1 debug port soft reset. when the development port receives a soft reset request from the development tool, an internal soft reset sequence is generated. in this case the development tool must reconfigure the debug port. see section 20.2.1.2.6 detecting the trace window end address for more information. if the dsck pin is asserted during sreset negation, the processor will take a breakpoint exception and go directly to debug mode, instead of fetching the reset vector. note: it is recommended that you connect trst to ground (if you don't use jtag) or to poreset through a diode. the problem with the connection to hreset is that if at power up the jtag logic blocks the poreset signal from propagating into the chip (since the logic is not initialized yet), this will prevent hreset from asserting, which leaves the jtag logic (and the whole device) uninitialized.
reset motorola mpc823e reference manual 4-5 reset 4 4.2 reset status register the 32-bit reset status register (rsr) is powered by the keep-alive power supply. as shown in section 3 memory map , it is memory-mapped into the mpc823e system interface unit register map and receives its default reset values at power-on reset. ehrsexternal hard reset status this bit is cleared by a power-on reset. when an external hard reset event is detected, this bit is set and remains that way until the software clears it. the ehrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no external hard reset event occurred. 1 = an external hard reset event occurred. esrsexternal soft reset status this bit is cleared by a power-on reset. when an external soft reset event is detected, this bit is set and remains that way until the software clears it. the esrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no external soft reset event occurred. 1 = an external soft reset event occurred. llrsloss-of-lock reset status this bit is cleared by a power-on reset. when a loss-of-lock event is enabled by the lolre bit in the plprcr is detected, this bit is set and remains that way until the software clears it. the llrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no enabled loss-of-lock reset event occurred. 1 = an enabled loss-of-lock reset event occurred. rsr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ehrs esrs llrs swrs csrs dbhrs dbsrs jtrs reserved reset 11000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w
reset 4-6 mpc823e reference manual motorola reset 4 swrssoftware watchdog reset status this bit is cleared by a power-on reset. when a software watchdog expire event occurs, this bit is set and remains that way until the software clears it. the swrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no software watchdog reset event occurred. 1 = a software watchdog reset event occurred. csrscheck stop reset status this bit is cleared by a power-on reset. when the core enters the checkstop state and the checkstop reset is enabled by the csr bit in the plprcr, this bit is set and remains that way until the software clears it. the csrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no enabled checkstop reset event occurred. 1 = an enabled checkstop reset event occurred. dbhrsdebug port hard reset status this bit is cleared by a power-on reset. when the debug port hard reset request is set, this bit is set and remains that way until the software clears it. the dbhrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no debug port hard reset request occurred. 1 = a debug port hard reset request occurred. dbsrsdebug port soft reset status this bit is cleared by a power-on reset. when the debug port soft reset request is set, this bit is set and remains that way until the software clears it. the dbsrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no debug port soft reset request occurred. 1 = a debug port soft reset request occurred. jtrsjtag reset status this bit is cleared by a power-on reset. when the jtag reset request is set, this bit is set and remains that way until the software clears it. the jtrs bit can be negated by writing a 1, but a write of zero has no effect on it. 0 = no jtag reset event occurred. 1 = a jtag reset event occurred. bits 8C31reserved these bits are reserved and must be set to 0.
reset motorola mpc823e reference manual 4-7 reset 4 4.3 how to configure reset in normal operation, you can configure reset with a hard reset. however, to configure the development port you must use a soft reset. 4.3.1 hard reset when a hard reset event occurs, the mpc823e reconfigures its hardware system as well as the development port configuration. the logical value of the bits that determine its initial mode of operation are sampled either from the data bus or from an internal default constant (d[0:31]=x00000000). if, at sampling time, rstconf is asserted, the configuration is sampled from the data bus. otherwise, it is sampled from the internal default. while hreset and rstconf are asserted, the mpc823e pulls the data bus low through a weak resistor (2-4k). you can overwrite this default by driving high to the appropriate bit, as shown in figure 4-1. figures 4-2 through 4-4 illustrate how reset configuration works when poreset is asserted. while the poreset input signal is being asserted, the core assumes the default reset configuration that changes when poreset is negated or the clkout signal starts oscillating. in this last case, the hardware configuration is sampled every nine clock cycles on the rising edge of the clkout. the setup time required for the data bus is 15 cycles and the maximum rise time of hreset must be less than six clock cycles. for more information, see section 4.3.2 soft reset . mpc823e figure 4-1. reset configuration basic scheme hreset dx (data line) rstconf mux configuration word
reset 4-8 mpc823e reference manual motorola reset 4 figure 4-2. reset configuration sampling scheme for short poreset assertion figure 4-3. reset configuration sampling scheme for long poreset assertion clkout poreset hreset rstconf intporeset default rstconf controlled tsup d[0:31] clkout poreset hreset rstconf intporeset default rstconf controlled tsup d[0:31]
reset motorola mpc823e reference manual 4-9 reset 4 figure 4-4. reset configuration sampling timing requirements clkout hreset rstconf data 12345678910111213141516 maximum time of reset recognition reset configuration word maximum setup time of reset recognition 17 sample data configuration sample data configuration sample data configuration
reset 4-10 mpc823e reference manual motorola reset 4 4.3.1.1 hard reset configuration word. the hard reset configuration word is sampled from the data bus. at reset, the bits will determine the default values of the corresponding bits in the siumcr, immr, and msr. earbexternal arbitration if this bit is set (1), external arbitration is assumed. if it is cleared (0), then internal arbitration is performed. see section 12 system interface unit for more information. iipinitial interrupt prefix this bit defines the initial value of the msr ip immediately after reset. the msr ip bit defines the interrupt table location. if iip is zero (default), the msr ip initial value is one, but if it is sampled one, the msr ip initial value is zero. bits 2, 6, and 15reserved these bits are reserved and must be left open. bdisboot disable 0 = the memory controller is activated after reset so that it matches all addresses. 1 = the memory controller is not activated after reset, but it is cleared. bpsboot port size this field defines the port size of the boot device. 00 = 32-bit port size. 01 = 8-bit port size. 10 = 16-bit port size. 11 = reserved. hard reset configuration word bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field earb iip res bdis bps res isb dbgc dbpc ebdf res default 00000000000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved default 0 note: the default value is due to the internal pull-down resistor on the data bus.
reset motorola mpc823e reference manual 4-11 reset 4 isbinitial internal space base select this field defines the initial value of the immr bits 0-15 and determines the base address of the internal memory space. make sure that the immr is not in the interrupt address space (iip). 00 = 0x00000000. 01 = 0x00f00000. 10 = 0xff000000. 11 = 0xfff00000. dbgcdebug pins configuration this field configures the functionality of the following pins. 00 = ip_b[0:1]/iwp[0:1]/vfls[0:1] functions as ip_b[0:1]. ip_b3/iwp2/vf2 functions as ip_b3. ip_b4/lwp0/vf0 functions as ip_b4. ip_b5/lwp1/vf1 functions as p_b5. op2/modck1/sts functions as op2. ale_b/dsck/at1 functions as ale_b. ip_b2/at2 functions as ip_b2. ip_b6/dsdi/at0 functions as ip_b6. ip_b7/ptr /at3 functions as ip_b7. op3/modck2/dsdo functions as op3. 01 = ip_b[0:1]/iwp[0:1]/vfls[0:1] functions as iwp[0:1]. ip_b3/iwp2/vf2 functions as iwp2. ip_b4/lwp0/vf0 functions as lwp0. ip_b5/lwp1/vf1 functions as lwp1. op2/modck1/sts functions as sts . ale_b/dsck/at1 functions as at1. ip_b2/at2 functions as at2. ip_b6/dsdi/at0 functions as at0. ip_b7/ptr /at3 functions as at3. op3/modck2/dsdo functions as op3. 10 = reserved. 11 = ip_b[0:1]/iwp[0:1]/vfls[0:1] functions as vfls[0:1]. ip_b3/iwp2/vf2 functions as vf2. ip_b4/lwp0/vf0 functions as vf0. ip_b5/lwp1/vf1 functions as vf1. op2/modck1/sts functions as sts . ale_b/dsck/at1 functions as at1. ip_b2/at2 functions as at2. ip_b6/dsdi/at0 functions as at0. ip_b7/ptr /at3 functions as at3. op3/modck2/dsdo functions as op3.
reset 4-12 mpc823e reference manual motorola reset 4 dbpcdebug port pins configuration this field configures the following pins on the active development port. 00 = ale_b/dsck/at1 functions as defined by dbgc. ip_b6/dsdi/at0 functions as defined by dbgc. op3/modck2/dsdo functions as defined by dbgc. ip_b7/ptr /at3 functions as defined by dbgc. tck/dsck functions as dsck. tdi/dsdi functions as dsdi. tdo/dsdo functions as dsdo. 01 = ale_b/dsck/at1 functions as defined by dbgc. ip_b6/dsdi/at0 functions as defined by dbgc. op3/modck2/dsdo functions as defined by dbgc. ip_b7/ptr /at3 functions as defined by dbgc. tck/dsck functions as tck. tdi/dsdi functions as tdi. tdo/dsdo functions as tdo. 10 = reserved. 11 = ale_b/dsck/at1 functions as dsck. ip_b6/dsdi/at0 functions as dsdi. op3/modck2/dsdo functions as dsdo. ip_b7/ptr /at3 functions as ptr. tck/dsck functions as tck. tdi/dsdi functions as tdi. tdo/dsdo functions as tdo. ebdfexternal bus division factor these bits define the frequency division factor between gclk1/gclk2 and gclk1_50/gclk2_50. clkout is similar to gclk2_50. gclk2_50 and gclk1_50 are used by the system interface unit and memory controller to interface with the external system. the ebdf bits (described in section 5.2.1 system clock and reset control register ) are initialized during hreset using the hard reset configuration mechanism. 4.3.2 soft reset when a soft reset event occurs, the mpc823e reconfigures the development port.
motorola mpc823e reference manual 5-1 clocks and power 5 control section 5 clocks and power control the mpc823e clock system provides many different timing options for all on-chip and external devices. it contains phase-locked loop circuitry and frequency dividers that generate programmable clock timing for baud rate generators, timers, the lcd controller, and a variety of low-power mode options. the programmable phase-locked loop, called the system phase-locked loop (spll) in the mpc823e, generates the overall system operating frequency. you can program the spll in integer multiples of the input clock frequency. the minimum internal operating frequency is 15mhz. to generate the system operating frequencies, divide by a power of two divider. the clock sources to the timebase, decrementer, real-time clock, and periodic interrupt counter are generated by the mpc823e clock module. for additional timer information, refer to section 12 system interface unit . the mpc823e has a variety of programmable modes that allow your system to operate at its highest level, and yet it still gives you the option of operating in a power-saving mode. figure 5-1 illustrates the internal clock source and distribution that includes the spll, clock dividers, drivers, and main clock oscillator. 5.1 features the following list summarizes the main features of the mpc823e clocks and power control system: ? contains system phase-locked loop (spll) ? clock dividers are provided for low-power modes and internal clocks ? contains five major power-saving modes: o normal, doze, sleep, deep sleep, and power-down. normal and doze have both high and low modes of operation. ? able to operate the core at low voltage for various power-saving modes
clocks and power control 5-2 mpc823e reference manual motorola clocks and power 5 control figure 5-1. clock source and distribution spll gclk1/gclk2 gclk1c/gclk2c vcoout clkout 2:1 mux clkout xfc tmbclk tmbclk vddsyn driver driver main clock xtal extal 2:1 mux rtc /pit clock and driver oscillator (oscm) 2:1 mux tbclk ( ? 4 or ? 16 ) modck[1:2] pitrtclk brgclk extclk lcdclk syncclk gclk2 tbs (sccr) rtsel gclk1_50/gclk2_50 low-power drivers dividers clock oscclk ? 4 ? 512 2:1 mux rtdiv
clocks and power control motorola mpc823e reference manual 5-3 clocks and power 5 control 5.2 register model 5.2.1 system clock and reset control register the spll has a 32-bit control register that is powered by keep-alive power. the system clock and reset control register (sccr) is memory-mapped into the mpc823e system interface units register map. bits 0 and 3C5reserved these bits are reserved and must be set to 0. comclock output module this field controls the output buffer strength of the clkout pin. when both bits are set, the clkout pin is held in the high state. these bits can be dynamically changed without generating spikes on the clkout pin. if the clkout pin is not connected to external circuits, both bits are must be set to minimize noise and power dissipation. the com field is cleared by hard reset. 00 = clock output enabled full-strength buffer. 01 = clock output enabled half-strength output buffer. 10 = reserved. 11 = clock output disabled. sccr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res com reserved tbs rtdiv rtsel crqen prqen reserved ebdf res hreset # 0 ###00 0 ? 0 por 00 0 0 ** 00 0 ? 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x280 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field res dfsync dfbrg dfnl dfnh dflcd dfalcd hreset 0000000 por 0000000 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x282 note: hreset is hard reset and por is power-on reset. = undefined and # = unaffected. * rtdiv depends on the combination of modck1and modck2. rtsel depends on modck1. see table 5-2 for more information. ? this field is set according to the default of the hard reset configuration word.
clocks and power control 5-4 mpc823e reference manual motorola clocks and power 5 control tbstimebase source this bit determines the clock source that drives the timebase and decrementer. 0 = timebase frequency source is oscclk divided by 4 or 16. 1 = timebase frequency source is gclk2 divided by 16. rtdivreal-time clock divide this bit indicates if the clock, the crystal oscillator or main clock oscillator, to the real-time clock and periodic interrupt timer is divided by 4 or 512. at power-on reset this bit is cleared if the modck1 and modck2 signals are low. 0 = the clock is divided by 4. 1 = the clock is divided by 512. rtselreal-time clock select this bit selects the crystal oscillator or main clock oscillator as the input source to the real-time clock. at power-on reset, this bit reflects the value of the modck1 signal. 0 = the main clock oscillator is selected. 1 = the extclk signal is selected. crqencpm request enable this bit is cleared by power-on or hard reset and specifies if the general system clock returns to the high frequency while the communication processor modules risc microcontroller is active. 0 = the system remains in the lower frequency even if the communication processor module is active. 1 = the system switches to high frequency when the communication processor module is active. prqenpower management request enable this bit specifies whether or not the general system clock returns to a high frequency when a pending interrupt from the interrupt controller or pow bit in the machine state register is clear (normal mode). see section 6.4.1.2.1 machine state register for more information. this bit is cleared by power-on or hard reset. 0 = the system remains in low frequency even if there is a pending interrupt from the interrupt controller or pow bit in the machine state register is cleared (normal mode). 1 = the system switches to high frequency when there is a pending interrupt from the interrupt controller or pow bit in the machine state register is cleared. bits 11C12 and 15C16reserved these bits are reserved and must be set to 0.
clocks and power control motorola mpc823e reference manual 5-5 clocks and power 5 control ebdfexternal bus division factor this field defines the frequency division factor between gclkx and gclkx_50. clkout is similar to gclk2_50. the gclkx_50 is used by the bus interface and memory controller to interface with an external system. this field is initialized during hard reset using the hard reset configuration word described in section 4.3.1.1 hard reset configuration word . 00 = clkout is gclk2 divided by 1. 01 = clkout is gclk2 divided by 2. 1x = reserved. dfsyncdivision factor for the syncclk this field sets the vcoout frequency division factor for the syncclk signal. changing the value of this field does not result in a loss-of-lock condition. this field is cleared by a power-on or hard reset. 00 = divide by 1 (normal operation). 01 = divide by 4. 10 = divide by 16. 11 = divide by 64. dfbrgdivision factor of the brgclk this field sets the vcoout frequency division factor for the brgclk signal. changing the value of this field does not result in a loss-of-lock condition. this field is cleared by a power-on or hard reset. 00 = divide by 1 (normal operation). 01 = divide by 4. 10 = divide by 16. 11 = divide by 64. dfnldivision factor low frequency this field sets the vcoout frequency division factor for general system clocks to be used in low-power mode. in low-power mode, the mpc823e automatically switches to the dfnl frequency. to select the dfnl frequency, load this field with the divide value and set the csrc bit. a loss-of-lock condition will not occur when you change the value of this field. this field is cleared by a power-on or hard reset. 000 = divide by 2. 001 = divide by 4. 010 = divide by 8. 011 = divide by 16. 100 = divide by 32. 101 = divide by 64. 110 = reserved. 111 = divide by 256.
clocks and power control 5-6 mpc823e reference manual motorola clocks and power 5 control dfnhdivision factor high frequency this field sets the vcoout frequency division factor for general system clocks to be used in normal mode. in normal mode, the mpc823e automatically switches to the dfnh frequency. to select the dfnh frequency, load this field with the divide value and clear the csrc bit. a loss-of-lock condition will not occur when you change the value of this field. this field is cleared by a power-on or hard reset. 000 = divide by 1. 001 = divide by 2. 010 = divide by 4. 011 = divide by 8. 100 = divide by 16. 101 = divide by 32. 110 = divide by 64. 111 = reserved. dflcddivision factor of lcdclk this field sets the vcoout frequency division factor for the lcdclk signal. the total division factor of dfalcd and this field must not exceed 64, as defined in section 5.3.4.4 the lcd clocks . a loss-of-lock condition does not occur when you change the value of this field. this field is cleared by a power-on or hard reset. 000 = divide by 1. 001 = divide by 2. 010 = divide by 4. 011 = divide by 8. 100 = divide by 16. 101 = divide by 32. 110 = divide by 64. 111 = reserved. dfalcddivision factor of lcdclk50 this field sets the lcdclk frequency division factor for the lcdclk50 signal. the lcdclk50 signal is input to the lcd panel. the total division factor of dflcd and this field must not exceed 64, as defined in section 5.3.4.4 the lcd clocks . changing the value of this field does not result in a loss-of-lock condition. this field is cleared by a power-on or hard reset. 00 = divide by 1. 01 = divide by 3. 10 = divide by 5. 11 = divide by 7.
clocks and power control motorola mpc823e reference manual 5-7 clocks and power 5 control 5.2.2 pll, low-power, and reset control register the 32-bit system pll, low-power, and reset control register (plprcr) is powered by a keep-alive power supply and is used to control the system frequency and low-power mode operation. mfmultiplication factor the output of the voltage control oscillator (vco) frequency is divided to generate the feedback signal that goes to the phase comparator. this field controls the value of the divider in the spll feedback loop. the phase comparator determines the phase shift between the feedback signal and the reference clock. this difference results in an increase or decrease of the vco output frequency. the mf field can be read and written at any time. changing the mf field causes the spll to lose its lock. all clocks are disabled until the spll reaches lock condition. the normal reset value for the dfnh bits is 0x0 (divide-by-one). when the spll is operating in one-to-one mode, the mf field is set to 0. see table 5-2 for details. bits 12C15reserved these bits are reserved and must be set to 0. plprcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field mf reserved hreset 0 por * 0 r/w r/w rw addr (immr & 0xffff0000) + 0x284 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field splss texps res tmist res csrc lpm csr lolre fiopd reserved hreset 10000 0 0 por 010000 0 000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x286 note: hreset is hard reset and por is power-on reset. = undefined. * depends on the combination of modck1and modck2. see table 5-2 for more information.
clocks and power control 5-8 mpc823e reference manual motorola clocks and power 5 control splsssystem pll lock status sticky this bit is not affected by hard reset. an out-of-lock indication sets the splss bit and it remains set until the software clears it. at power-on reset, the state of the splss bit is zero. write a 1 to clear this bit (writing a zero has no effect). notice that a loss-of lock caused by a change in the mf field or the processor entering deep-sleep mode or power-down mode does not affect the splss bit. only a loss-of-lock not caused by the following conditions will set this bit. 0 = spll remains locked. 1 = spll has gone out of lock at least once since the bit was cleared or at the last power-on reset. texpstimer expired status this internal status bit is set when the periodic timer expires, the real-time clock alarm sets, the timebase clock alarm sets, the decrementer interrupt occurs, or the system resets. the texp pin reflects the value of the texps bit, so you have to read the pin to find out the status of the bit. you can clear this bit by writing a 1 (writing a zero has no effect). when texps is set, the texp external signal is asserted and, when it is reset, texp is negated. 0 = texp is negated. 1 = texp is asserted. bits 18, 20, and 27C31reserved these bits are reserved and must be set to 0. tmisttimers interrupt status this bit is cleared at reset and is set when a real-time clock, periodic interrupt timer, timebase, or decrementer interrupt occurs. you can clear this bit by writing a 1 (writing a zero has no effect). when the tmist bit is set, the system clock switches to high frequency, as defined by the dfnh field. the system clock frequency stays high if the csrc bit is set and there is no reason to switch to normal low mode. 0 = no timer interrupt is detected. 1 = a timer interrupt is detected. csrcclock source this bit specifies whether the dfnh or dfnl field generates the general system clock. this bit is cleared by a hard reset. 0 = the general system clock is generated by the dfnh field. 1 = the general system clock is generated by the dfnl field.
clocks and power control motorola mpc823e reference manual 5-9 clocks and power 5 control lpmlow-power modes this bit, in conjunction with the texps and csrc bits, specifies the operating mode of the core. there are seven possible modes. in the normal mode, you can write a non-zero value to this field. in the other modes, only a reset or interrupt (that is not from the interrupt controller) can clear this field. 00 = normal high/normal low mode. 01 = doze high/doze low mode. 10 = sleep mode. 11 = deep sleep/power-down mode. csrcheckstop reset enable this bit enables an automatic reset when the processor enters checkstop mode. if the processor enters debug mode at reset, then reset is not generated automatically. refer to section 20.6.3.2 debug enable register for more information. lolreloss-of-lock reset enable this bit enables hard reset generation when a loss-of-lock indication occurs, but not as a result of altering the mf field or the processor entering deep-sleep or power-down mode. 0 = a hard reset is not generated when a loss-of-lock is indicated. 1 = a hard reset is generated when a loss-of-lock is indicated. fiopdforce i/o pull down this bit indicates when the address and data external pins are driven by an internal pull-down device in sleep and deep-sleep mode. 0 = no pull-down on the address and data bus. 1 = address and data bus is driven low in sleep and deep-sleep mode. csr bit chstpe bit in der checkstop mode result 0 0 no 0 0 yes 0 1 no 0 1 yes enter debug mode 1 0 no 1 0 yes automatic reset 1 1 no 1 1 yes enter debug mode
clocks and power control 5-10 mpc823e reference manual motorola clocks and power 5 control 5.3 the clock module the input frequency source for the phase-locked loop can either be a low frequency crystal or a high frequency crystal (4mhz) that the phase-locked loop multiplies to produce the system clock. if you use a low frequency crystal circuitry, the on-chip main clock oscillator requires an external parallel resonant crystal, two capacitors, and two resistors, as shown in figure 5-2. when you design and implement this circuitry, follow normal high-frequency design rules for placement and layout. if you use a high-frequency oscillator, its output can be directly input to the extclk pin. even though crystals are typically much cheaper, oscillators have more stability because they are less affected by trace length, component quality, printed circuit board layout and characteristics. the mpc823e clock module consists of the main crystal oscillator, the spll, the low-power divider, the clock generator/driver blocks, and the clock module/system low-power control block. the clock module and system low power control block receive control bits from the system clock control register (sccr), pll low-power and reset control register (plprcr), and reset status register (rsr). figure 5-3 illustrates the clock module. figure 5-2. crystal oscillator note: in your design, you must always consider the oscillation startup stablization time of the crystal. during this stabilization time, no internal or external clocks are generated by the mpc823e, which may cause higher than normal static current during the short period of stabilization. assuming that the crystal circuit is powered by keep-alive power, then once you system has had first time power- up, allowance for stabilization is not necessary. extal oscm xtal xfc vddsyn xfc 0.1 f * clkout spll vsssyn 32 or 38khz crystal a4 a5 b2 b1 a1 a2 vsssyn1 vdd extclk 3C5mhz xtal osc *xfc must be a low-leakage capacitor. see section 22 electrical characteristics for recommended values. a6 a2 a7 d1 mpc823
clocks and power control motorola mpc823e reference manual 5-11 clocks and power 5 control figure 5-3. clock module diagram vddsyn / vsssyn phase comparator multiplication factor mf[0:11] xfc oscclk up down vcoout feedback clock delay charge pump vco dfsync dfbrg dfnh dfnl dflcd dfalcd 2:1 mux ebdf cpm core upm, external lcd/video controller lcd panel syncclk brgclk gclk1c gclk2c gclk2 gclk1_50 gclk2_50 clkout lcdclk lcdclk50 division factor total less than 64 low-power mode phase phase bus interface normal modes normal or doze mode com[0:1] pcmcia, gclk1
clocks and power control 5-12 mpc823e reference manual motorola clocks and power 5 control 5.3.1 on-chip oscillators and external clock input the main clock oscillator (oscm) uses either a 3-5mhz source at extclk (4mhz mode) oscillator or a 30-50khz (32khz mode) crystal between extal and xtal to generate the spll reference clock (ossclk). the external clock input extclk is generated from an external source. in one-to-one mode, the input clock frequency must be at least 15mhz. otherwise, it can be between 3 and 5mhz. see figure 5-1 for details. for normal operation, at least one clock source must be active, but it is possible to configure both clock sources to be active. when both clock sources are active, the extclk pin provides the oscclk signal for the spll. the extal and xtal pins provide the input frequency for the oscm that generates the pitrtclk signal. the input of an unused timing reference must be grounded. 5.3.2 system pll the main purpose of the spll is to generate a stable reference frequency by multiplying the frequency and eliminating the clock skew. the spll allows the processor to operate at a high internal clock frequency using a low frequency clock input, which gives you two advantages. lower frequency clock input reduces the overall electromagnetic interference generated by the system. also, oscillating at different frequencies reduces the cost because you will not have to add more oscillators to your system. the mpc823e spll block diagram is illustrated in figure 5-4. note: under any condition, the voltage on the modck1 and modck2 pins must be less than or equal to the power supply voltage vddh applied to the part. figure 5-4. spll block diagram vddsyn / vsssyn phase comparator multiplication factor mf[0:11] xfc oscclk up down vcoout feedback clock delay charge pump vco
clocks and power control motorola mpc823e reference manual 5-13 clocks and power 5 control the oscclk signal goes to the phase comparator that controls the direction in which the charge pump drives the voltage across the external filter capacitor (xfc). direction is based on whether the feedback signal phase lags or leads the reference signal. the output of the charge pump drives the vco whose output frequency at vcoout is divided down and fed back to the phase comparator to be compared with the reference frequency (oscclk signal). the multiplication factor must be between 1 and 4,096. also, when the spll is operating in one-to-one mode, the multiplication factor is 1 (the mf field equals 0). at the initial system power-up after keep-alive power is lost, external logic must assert the poreset pin for 3s after a valid level is reached on the keep-alive power supply. when power-on reset is asserted, the mf field is set as shown in table 5-1 and the dfnh and dfnl fields are both set to 0. this mf field value then programs the spll to generate the approximate default system frequency of 16.7mhz when a 32khz input frequency is used and 20mhz when a 4mhz input frequency is used. 5.3.2.1 spll stability. the spll can multiply the input frequency by any integer that is between 1 and 4,096. the multiplication factor can be changed by modifying the value of the mf field in the plprcr. even though any multiplication factor between 1 and 4,096 can be programmed, the resulting system clock frequency must be within the range specified in section 23 mechanical data and ordering information . the mf field in the plprcr is set to a predetermined value when a power-on reset occurs. the multiplication factor is the most important parameter and as it goes higher it has a greater effect on the stability of the spll. there are three factors that define spll stabilityphase skew, phase jitter, and frequency jitter. the phase skew is the time difference between the falling edges of the extal and clkout pins for a capacitive load on clkout over the entire process, temperature ranges, and voltage ranges. for input frequencies greater than 15mhz and mf 2, this skew is between -0.9ns and +0.9ns. otherwise, this skew is not guaranteed. however, for mf<10 and input frequencies greater than 10mhz, the skew is between -2.3ns and +2.3ns. table 5-1. power-on reset clock configuration modck [1:2] default mf + 1 at power-on reset spll options 00 513 normal operation, spll enabled. main timing reference is oscm freq = 32 khz. 01 5 normal operation, spll enabled. main timing reference is oscm freq = 4 mhz. 11 5 normal operation, spll enabled. main timing reference is extclk freq = 4 mhz. 10 1 normal operation, spll enabled. one-to-one mode maximum oscm freq = extclk freq
clocks and power control 5-14 mpc823e reference manual motorola clocks and power 5 control the phase jitter is a variation in the skew that occurs between the falling edges of the extal and clkout pins for a specific temperature, voltage, input frequency, mf, and capacitive load on the clkout pin. these variations are a result of the pll locking mechanism. for input frequencies greater than 15mhz and mf 2, this jitter is less than 0.6ns. otherwise, this jitter is not guaranteed. however, for mf<10 and input frequencies greater than 10mhz, this jitter is less than 2ns. the frequency jitter is defined as the frequency variation of the clkout pin. for small multiplication factors (mf<10), this jitter is smaller than 0.5%. for mid-range multiplication factors (10500), the frequency jitter is 2C3%. the maximum input frequency jitter on the extal pin is 0.5%. if the rate of change of the frequency at the extal pin is slow (it does not jump between the minimum and maximum values in one cycle), the maximum jitter can be 2%. 5.3.3 the low-power clock divider the output of the spll is sent to a low-power divider that generates other clocks for normal operation, but also has the ability to divide the output frequency of the vco before it generates the syncclk, lcdclk, lcdclk50, brgclk, and gclkx (which is sent to the rest of the mpc823e). gclkxc is the system timing reference for the core, instruction and data caches, and memory management unit. gclkx is the system timing reference for the other modules. gclkx_50 operates at a frequency that is half the gclkx frequency. the frequency ratio between gclkx and gclkx_50 is determined by the ebdf bit in the sccr.
clocks and power control motorola mpc823e reference manual 5-15 clocks and power 5 control the low-power dividers allow you to reduce and restore the operating frequencies of different sections of the mpc823e without losing the spll lock. using the low-power dividers, you can still obtain full chip operation, but at a lower frequency. this is called normal low mode. you can switch to normal low mode or set the speed at any time and the changes you make will occur immediately. the low-power dividers are controlled by the sccr and its default division factor is divide by one at reset. for a 40mhz system, syncclk, lcdclk, lcdclk50, brgclk, and gclkx are all 40mhz at reset. figure 5-5. clock dividers dfsync dfbrg dfnh dfnl dflcd dfalcd 2:1 mux ebdf cpm core upm, external lcd/video controller lcd panel syncclk brgclk gclk1c gclk2c gclk2 gclk1_50 gclk2_50 clkout lcdclk lcdclk50 division factor total less than 64 low-power mode phase phase bus interface normal modes normal or doze mode com[0:1] gclk1 pcmcia,
clocks and power control 5-16 mpc823e reference manual motorola clocks and power 5 control 5.3.4 internal clock signals the internal logic of the mpc823e uses the following internal clock signals: ? general system clocks ? baud rate generator clock ? synchronization clocks ? lcd clocks the mpc823e also generates an external clock signal called clkout. all internal clock signals originate from the same source, so they are all synchronized to vcoout. 5.3.4.1 the general system clocks. the general system clocksgclk1c, gclk2c, gclk1, gclk2, gclk1_50, and gclk2_50are the basic clocks supplied to all modules of the mpc823e. gclkxc is supplied to the core, data and instruction caches, and memory management unit. it is not active when the core is in sleep or power-down mode. gclkx is supplied to the system interface unit, clock module, memory controller, and most of the other blocks in the communication processor module. the timing relationship between the general system clock signals that are shown in figure 5-1 is illustrated in figure 5-6. clkout, the only externally visible clock, is derived from the gclk2_50 signal. figure 5-6. mpc823e clocks timing diagram gclk1 gclk2 gclk1_50 gclk2_50 clkout gclk1_50 gclk2_50 (ebdf=00) (ebdf=00) (ebdf=01) (ebdf=01) clkout (ebdf=00) (ebdf=01)
clocks and power control motorola mpc823e reference manual 5-17 clocks and power 5 control notice that gclk1_50, gclk2_50, and clkout can have a lower frequency than gclk1 and gclk2. this allows the external bus to operate at lower frequencies as controlled by the ebdf bit in the sccr. gclk2_50 always rises simultaneously with gclk2. gclk1_50 rises simultaneously with gclk1, but when the mpc823e is not in normal low mode, the falling edge of gclk1_50 occurs in the middle of the high phase of gclk2_50 and ebdf determines the division factor between gclkx and gclkx_50. see figure 5-9 for more information. the general system clock defaults to vcoout frequency at system reset. in normal low mode, the frequency of the general system clock can be dynamically switched using the sccr. you can switch the general system clock division factor between two different values (dfnh and dfnl). the high frequency is generated by using the dfnh field in the sccr and it is used in normal high and doze high mode. the low frequency is generated using the dfnl field in the sccr and it is used in normal low and doze low mode. conventionally, to conserve power low frequency is slower than high frequency. in some applications, a high frequency is needed to perform critical tasks. for example, interrupt routines need to be run at a high frequency, but the rest of the application can run at a low frequency to conserve power. the mpc823e can automatically switch between low and high frequency operation when one of the following conditions exist: ? a pending interrupt from the interrupt controller occurs. this option is maskable by the prqen bit in the sccr. ? the pow bit of the machine status register is clear. this option is maskable by the prqen bit in the sccr. ? the risc microcontroller in the communication processor module has a pending request or is currently executing a routine. this option is maskable by the crqen bit in the sccr. figure 5-7. selecting the general system clock dfnh divider dfnl divider vcoout dfnh low power mode gclk1 dfnl 2:1 mux
clocks and power control 5-18 mpc823e reference manual motorola clocks and power 5 control when none of these conditions exist and the csrc bit of the plprcr is set, the general system clock automatically switches back to low frequency. when the general system clock is divided, its duty-cycle is modified. one phase remains the same while the other stretches out. gclkx and clkout no longer have a 50% duty cycle when the division factor is greater than 1, as shown in figure 5-8 and figure 5-9. figure 5-8. divided system clocks timing diagram figure 5-9. mpc823e clocks for division factor 2 gclk1 divided by 1 gclk2 divided by 1 gclk1 divided by 2 gclk2 divided by 2 gclk1 divided by 4 gclk2 divided by 4 gclk1 gclk2 gclk1_50 gclk2_50 clkout gclk1_50 gclk2_50 (ebdf=00) (ebdf=00) (ebdf=01) (ebdf=01) clkout (ebdf=00) (ebdf=01)
clocks and power control motorola mpc823e reference manual 5-19 clocks and power 5 control the frequency for the gclkx system clock is: the frequency for the gclkx_50 system clock is: clkout is derived from gclk2_50. it defaults to vcoout, which is the user-defined system frequency (25-75mhz). clkout can drive at full-strength, half-strength, or it can be disabled. the strength of the drive is controlled in the system clock and reset control register. disabling or decreasing the strength of clkout reduces power consumption, noise, and electromagnetic interference on the printed circuit board. when the spll is acquiring lock, the clkout signal is disabled and remains in a low state. 5.3.4.2 the baud rate generator clock. the baud rate generator clock (brgclk) is used by the four baud rate generators of the communication processor module and by the memory controller refresh counter. it defaults to vcoout, which is the user-defined system frequency (25-75mhz). the baud rate generator clock allows the baud rate generators to continue operating at a fixed frequency, even when the rest of the mpc823e is operating at a reduced frequency. refer to section 16.8 the baud rate generators for more information about using the baud rate generator clock to save power. figure 5-10. clkout divider figure 5-11. brgclk divider gclkx freq vcoout freq 2 dfnh () or 2 dfnl 1 + () -------------------------------------------------------------- = gclkx_50 freq vcoout freq 2 dfnh () or 2 dfnl 1 + () -------------------------------------------------------------- 1 ebdf 1 + --------------------------- = ebdf gclk2_50 clkout phase gclk1 dfbrg cpm, upm, brgclk vcoout (refresh timer)
clocks and power control 5-20 mpc823e reference manual motorola clocks and power 5 control the baud rate generator clock frequency is: 5.3.4.3 the synchronization clocks. the synchronization clock signal (syncclk) is used by the serial synchronization circuitry in the serial ports of the communication processor module that includes the serial interface, serial communication controllers, and serial management controllers. syncclk defaults to vcoout, which is the user-defined system frequency (25-75mhz). syncclk allows the serial interface, serial communication controllers, and serial management controllers to continue operating at a fixed frequency, even when the rest of the mpc823e is operating at a reduced frequency. this allows you to maintain the serial synchronization circuitry at the preferred rate, while lowering the general system clock to the lowest possible rate. syncclk must always have a frequency at least as high as the general system clock frequency and be at least two times the preferred serial clock rate. if the time-slot assigner in the serial interface is used, syncclk is at least two and half times the preferred serial clock rate. refer to section 16.7 the serial interface with time-slot assigner for more information on how to select an appropriate frequency for syncclk. the synchronization clock frequency is: figure 5-12. syncclk divider brgclk freq vcoout freq 2 2 dfbrg () ------------------------------------------ - = dfsync cpm syncclk vcoout syncclk freq vcoout freq 2 2 dfsync () ---------------------------------------------- - =
clocks and power control motorola mpc823e reference manual 5-21 clocks and power 5 control 5.3.4.4 the lcd clocks. the lcd clockslcdclk and lcdclk50are used by the lcd controller circuitry to transfer the frame data to pixel format data. lcdclk defaults to vcoout, which is the user-defined system frequency (25-75mhz).when the pon bit in the lccr is set, the ratio between the system clock frequency value and the lcd clock frequency value must be an integer value. the lcd clock frequency is the system frequency divided by two serial dividers. lcdclk50 is a 50% duty-cycle clock at the same frequency as lcdclk that is used as a clock output to the lcd panel. dflcd and dfalcd must be set so that the total lcd clock division factor never exceeds 64. the lcdclk and lcdclk50 frequency is: figure 5-13. lcdclk divider figure 5-14. lcd clock timing diagram dflcd dfalcd lcd/video controller lcd panel lcdclk lcdclk50 vcoout lcdclk freq = lcdclk50 freq vcoout freq 2 dflcd () 2 dfalcd + 1 () ------------------------------------------------------------------------------------- - = lcdclk divide by 1 lcdclk50 divide by 1 lcdclk divide by 2 lcdclk50 divide by 2 lcdclk divide by 4 lcdclk50 divide by 4 gclk2 divide by 1 gclk2 divide by 2 gclk2 divide by 4
clocks and power control 5-22 mpc823e reference manual motorola clocks and power 5 control 5.3.5 clock configuration you can configure the clock of the mpc823e using the modck1 and modck2 pins. the spll has several power and ground pins (vddsyn, vsssyn, vsssyn1, and xfc) that must be properly terminated for stability and clkout integrity. 5.3.5.1 mode clock pins. the modck1 and modck2 pins are used to determine clock source and configuration options. these pins are sampled on the rising edge of the poreset pin. modck1 specifies the input source to the spll and, combined with modck2, specifies the multiplication factor at reset. if you do not want the pitrtclk, tmbclk, and multiplication factor to change during power-down mode, do not sample the modck1 and modck2 pins during wake-up. thus, the poreset pin must remain negated while the hreset pin is asserted during this wake-up sequence. modck1 selects the clock source to use (extclk or main oscillator) and modck2 selects the reference frequency (4mhz, 32khz, or extclk). if, during the power-on reset sequence, the modck1 pin is zero, then the oscillators 4mhz or 32khz clock is the selected input. if modck1 is one, then the extclk pin is the input source to the spll. the system clock frequency (gclk1) can be divided as defined by the dfnh and dfnl fields in the sccr. the maximum system clock frequency occurs when the dfnh field is equal to 00. if modck2 is zero during the power-on reset sequence, the input frequency is either 32khz or extclk (one-to-one mode). if the modck2 pin is one, then a 4mhz clock is the input source to the spll. if the extclk pin is the main timing reference and the oscm is the timing reference to the real-time clock and periodic interrupt timer, then the frequency of the oscm must be 32.768 or 38.4khz. depending on how the tbs bit is set in the sccr, the timebase clock is either the spll clock frequency or gclk2. the rtsel field in the sccr specifies the source (extclk or oscm) of the periodic interrupt timer and real-time clock. the rtdiv field in the sccr specifies the division factor ( ? by 4 or ? by 512). table 5-2. reset clock source configuration modck [1:2] power-on reset (por) default mf + 1 at por pitrtclk division defaults at por tmbclk division defaults at por spll options 00 0 513 4 4 normal operation, spll enabled. main timing reference is oscm freq = 32 khz. 01 0 5 512 4 normal operation, spll enabled. main timing reference is oscm freq = 4 mhz. 11 0 5 512 4 normal operation, spll enabled. main timing reference is extclk freq = 4 mhz. 10 0 1 512 16 normal operation, spll enabled. one-to-one mode, maximum oscm freq = extclk freq 1 the configuration remains unchanged.
clocks and power control motorola mpc823e reference manual 5-23 clocks and power 5 control 5.3.5.2 the system phase-locked loop pins. the internal frequency of the mpc823e and the output of the clkout pin depends on the quality of the crystal circuit and the mf bit in the plprcr. the spll contains the following dedicated pins that are isolated from common power and ground. ? vddsynthe power supply pin for the analog spll circuitry. you must provide a well-regulated voltage to this pin via an extremely low impedance path to the vdd power rail. the spll power plane must be isolated from the vdd power plane with an lc filter, which gives you the best performance. a 0.1 m f bypass capacitor must connect vddsyn and vsssyn and be as close to the chip as possible. to reduce the noise from the open extal pin, pull it to ground when you are not using it. ? vsssyna ground reference pin for the analog spll circuitry. you must provide a low impedance path from vsssyn to the ground plane. ? vsssyn1a ground reference pin for the analog spll circuitry. you must provide a low impedance path from vsssyn1 to the ground plane. ? xfcthe external filter capacitor pin that connects to the off-chip capacitor for the spll filter. one terminal of the capacitor is connected to xfc while the other terminal is connected to the vddsyn pin. for proper spll operation, you must supply a minimum parallel parasitic resistance value of 30m w . the value of the xfc capacitor is based on the value of the mf field in the plprcr. note: the multiply factor range is the true multiply factor starting from 1, not 0. if you look at table 5-4 , it indicates the multiply factor range, not the mf field, of the plprcr. the multiply factor (mf) referred to in this table is the value of the mf field in the plprcr plus 1 (or plprcrmf + 1). the multiply factor (plprcrmf + 1) is the value that should be used in the equations to determine the xfc capacitor value. table 5-3. tmbclk dividers tbs bit in sccr modck1 at reset mf + 1 clock source tmbclk division 1 gclk2 16 0 0 oscm 4 0 1 1, 2 extal 16 0 1 > 2 extal 4 table 5-4. xfc capacitor values based on the mf field xfc capacitor values multiply factor range minimum capacitance recommended capacitance maximum capacitance unit mf 4 (580 *mf) - 100 (680 * mf) - 120 (780 * mf) - 140 pf mf > 4 830 * mf 1100 * mf 1470 * mf pf
clocks and power control 5-24 mpc823e reference manual motorola clocks and power 5 control 5.4 power control to preserve the life of your battery, the mpc823e provides low-power modes that limit the operation to essential modules. in addition to normal high mode, the mpc823e supports normal low, doze high, doze low, sleep, deep-sleep, and power-down modes. when the communication processor module is idle, it uses its own power-saving mechanism to shut down automatically. there are a variety of modules connected to separate power rails that allow you to achieve the best performance using the least amount of power. 5.4.1 power rails there are different power planes (called power rails) within the mpc823e that can be connected to different power sources. your system implementation defines the power source for each of these different power rails. figure 5-15 shows you which module is connected to each power rail. the i/o buffers, logic, and clock control are fed by a 3.3v (5%) power supply. the internal logic can be fed by a 3.3v source. to improve clkout stability, the spll requires a separate 3.3v source (vddsyn). the oscm, timebase, decrementer, periodic interrupt timer, real-time clock, sccr, plprcr, and rsr are all connected to the keep-alive power (kapwr) rail. this power rail architecture allows you to remove the power at the vddh/ vddl/vddsyn pins during sleep, deep-sleep, or power-down mode. the external power supply unit can use the texp pin, which is fed by the kapwr rail, to switch between power sources. mpc823e figure 5-15. mpc823e power rails and texp status clock control analog pit, rtc, tb, dec, sccr, internal logic vddh i / o pad vddl vddsyn kapwr texp oscm, plprcr, and rsr and clock drivers and digital spll spll
clocks and power control motorola mpc823e reference manual 5-25 clocks and power 5 control all other circuits are powered by the normal supply pinsvddh and vddland vss. vddh feeds the i/o buffers and logic and vddl supplies the internal chip logic to reduce system power consumption. however, the power supply connected to vddh must be larger or equal to the one connected to vddl. the power supply for each block is listed in table 5- 5 and described in section 5.4 power control . the following are the power supply requirements of the mpc823e: ? vddh = vddsyn = 3.3v 5% ? vddh 3 vddl 3 3.3v 5% ? vddh 3 kapwr 3 vddh C 0.4v for normal operation ? kapwr 3 2.5v 5% in power-down mode 5.4.2 keep-alive power when the mpc823e is in normal operation mode, the keep-alive power supply (kapwr) is powered to the same voltage value as that of the i/o buffers and logic. therefore, if the vddl and vddh is 3.3v, then the kapwr is 2.9v to 3.3v. table 5-5. mpc823e power supply block vddh vddl vddsyn kapwr i/o pad x clkout x digital spll x clock control x x internal logic x clock drivers x analog spll x main clock oscillator x sccr, plprcr, and rsr x real-time clock, periodic interrupt timer, timebase and decrementer x
clocks and power control 5-26 mpc823e reference manual motorola clocks and power 5 control 5.4.2.1 power switching example. an example of a switching scheme for an optimized low-power system is illustrated in figure 5-16. switch 1 and 2 (sw1 and sw2) can be combined into a single switch if vddsyn and vddh are supplied by the same source. if vddl is fed with 3.3v, sw2 and sw3 can be combined into one switch. the texp pin, if enabled, is asserted by the mpc823e when the real-time clock or timebase time value matches the value programmed in its associated alarm register or when the periodic interrupt timer or decrementer decrements their value to zero. the texp pin is negated when you write a 1 to the texps bit in the plprcr. if the voltage to the kapwr rises too slow, the oscm (supplied by kapwr) will take longer to stabilize the oscclk. the maximum kapwr rise time must be less than 1.7v/ms for a 32khz input frequency. mpc823e figure 5-16. external power supply scheme main power backup vddsyn 3.3v 2.2v vddh vddl kapwr supply switch logic texp 2.5-3.3v sw1 sw2 power supply sw3
clocks and power control motorola mpc823e reference manual 5-27 clocks and power 5 control 5.4.2.2 register lock. the mpc823e registers that are powered by kapwr can be write-protected using the associated key register shown in table 5-6. when the mpc823e disconnects from the main power supply after it enters power-down mode, the value of these registers is automatically preserved. you may lose data if you do not enter power-down mode before disconnecting. to protect your data, lock the register by writing to the associated key register. once you lock a register, writes are ignored and a machine check exception is generated. each of the registers in the keep-alive power region have a key register that can be in an open or locked state. at power-on reset, all key registers are open, except for the key real-time clock registers. each key register has an associated address in the internal memory map, as shown in table 3-1. if you write 0x55ccaa33 to any of the key registers, the associated register will be open and if you write any other value it will be locked. for example, writing a 0x55ccaa33 to the rtck key register will allow you to access the rtc register. table 5-6. key registers mnemonic register name tbscrk timebase status and control register key tbreffuk timebase reference register upper key tbrefflk timebase reference register lower key tbk timebase and decrementer register key rtcsck real-time clock status and control register key rtck real-time clock register key rtseck real-time alarm seconds key rtcalk real-time alarm register key piscrk periodic interrupt status and control register key pitck periodic interrupt count register key sccrk system clock control key plprcrk pll, low power and reset control register key rsrk reset status register key note: refer to section 3 memory map for each registers address. note: a write of 0x55ccaa33 to any of the key registers in table 5-6 will unlock the associated siu register and witing any other value will cause the associated siu register to be locked. any other accesses to these key registers, inlcuding reads, will cause the associated siu register to be locked.
clocks and power control 5-28 mpc823e reference manual motorola clocks and power 5 control 5.5 low-power operation the low-power dividers can be used to take advantage of the mpc823es low-power capabilities. the low-power dividers allow you to dynamically adjust the operating frequencies for different modules of the mpc823e and yet still maintain the spll lock. in normal low mode, you can use the low-power dividers to maintain full chip functionality, but at a much lower frequency. when you change the value of the divider, the resulting output frequency occurs immediately. the low-power dividers are controlled in the sccr (described in section 5.2.1 system clock and reset control register ) and their default division factors are one. for example, in a 75mhz system frequency, the syncclk, lcdclk, lcdclk50, brgclk, and gclkx are all 75mhz. you can switch between the various low-power modes, as illustrated in figure 5-18. your software must set the appropriate csrc and lpm fields in the plprcr and the pow bit in the msr so the mpc823e can enter doze, sleep, or power-down mode from a normal mode. the plprcr is described in section 5.2.2 pll, low-power, and reset control register . the mpc823e uses an interrupt to exit from any of these lower power modes. an enabled interrupt clears the lpm field, but does not change the csrc bit. an interrupt switches automatically to normal high mode from normal low, doze high, doze low, sleep, or deep-sleep mode. interrupts are generated by: ? wake-up interrupts (irqx signal) from the interrupt controller. ? real-time clock, periodic interrupt timer, timebase, or decrementer interrupts. figure 5-17. register lock mechanism open locked write 0x55ccaa33 to write any other value to power-on reset the key register the key register
clocks and power control motorola mpc823e reference manual 5-29 clocks and power 5 control figure 5-18. mpc823e low-power mode flowchart normal high mode lpm = 00, csrc = 0 or 1 normal low mode lpm = 00, csrc = 1 doze low mode lpm = 01, csrc = 1 doze high mode lpm = 01, csrc = 0 or 1 sleep mode lpm = 10, csrc = 0 deep-sleep mode lpm = 11, csrc = 0, power-down mode lpm = 11, csr c = 0, crqen & cpm_act | prqen & (pow | interrupt) | csrc (prqen | pow & interrupt ) & crqen | cpm_act ) & csrc*** cpm_act & csrc cpm_act wake-up: 500 oscm clocks * software is active only in normal high/low modes. rtc/pit/tb/dec interrupt hard reset wake-up: 3-4 vcoout interrupt clocks texps = 1 texps = 0** ** texps receives the zero value by writing a one to it. writing a zero has no effect on texps. external hard reset *** you can switch from normal high to normal low only if the conditions to an interrupt are cleared. followed by an external hard reset or wake-up or rtc/pit/tb/dec interrupt interrupt software * note: & denotes and operation, | denotes or operation, and cpm_act denotes cpm activity. wake-up: maximum 2-4 gclk1 clocks
clocks and power control 5-30 mpc823e reference manual motorola clocks and power 5 control the system responds quickly to an interrupt that does not come from the interrupt controller. the wake-up time from normal low, doze high, doze low, or sleep mode is between three and four vcoout clocks. for example, it could take 60-80ns to wake up in a 75mhz system. the level-sensitive interrupt from the interrupt controller is defined as a wake-up interrupt. it is only negated after the interrupt source bit is cleared. any of the real-time clock, periodic interrupt timer, timebase, or decrementer interrupts can set the tmist bit in the plprcr. the mpc823e clock module recognizes this interrupt as a pending interrupt when the tmist bit is set. therefore, the tmist bit must be cleared before you enter any low- power mode other than normal high mode. the wake-up time for all interrupt sources from the interrupt controller is measured in actual gclk1 clocks. once the interrupt is recognized, it takes between two and four gclk1 clocks for the mpc823e to reach normal high mode. for example, it could take between 10.24s and 20.48s to wake up in a 75mhz system where dfnl = 111 (divided by 256). in normal and doze modes when the csrc bit is set, the system toggles between the low and high frequencies. one of the following conditions must be met before you can switch from normal low mode to normal high mode. ? the communication processor module must be active (cpm_act) ? a pending interrupt from the interrupt controller must be recognized (interrupt) ? the pow bit in the msr must be cleared (normal operation) (pow) if none of these conditions are met, the csrc bit is set, and the interrupt status bits are reset, then the system automatically switches back to normal low mode. if the communication processor module is active, the system automatically switches from doze low mode to doze high mode. on the other hand, when the communication processor module is idle and the csrc bit is set, then the system automatically switches back to doze low mode. a pending interrupt from the interrupt controller transfers the system from doze mode to normal high mode. the mpc823e exits deep-sleep mode and enters normal high mode when a wake-up interrupt from the interrupt controller, real-time clock, periodic interrupt timer, timebase, or decrementer is recognized. in deep-sleep mode the spll is disabled and, therefore, the wake-up time from this mode is a maximum of 500 oscm clocks. in 1-to-1 mode, the wake-up time can be a maximum of 1,000 extclk clocks. for example, if the spll input frequency is 32khz, the wake-up time is a maximum of 15.6ms and if it is 4mhz in 1-to-1 mode, the wake-up time is a maximum of 125 m s. to exit power-down mode and enter normal high mode, the hreset pin must be asserted by external logic when the texp pin is asserted. the texps bit in the plprcr is automatically set when a wake-up interrupt from the real-time clock, periodic interrupt timer, timebase, or decrementer occurs. hreset must be asserted longer than the time it takes the power supply to wake up, plus the time it takes for the spll to reach lock condition. another way to exit power-down mode is to assert hreset when the texp pin is negated and the texps bit is cleared. this causes the mpc823e to automatically assert the texp pin, which sets the texps bit, and enter normal high mode.
clocks and power control motorola mpc823e reference manual 5-31 clocks and power 5 control when a timer expires, if enabled, the texp pin is asserted asynchronously with clkout to show that the mpc823e is preparing to exit power-down mode. texp must be externally connected to a switch that must turn on the power supply to the chip, as illustrated in figure 5-16. in normal and doze modes, the system can be in the high mode defined by the dfnh field or in the low mode defined by the dfnl field. the mpc823e is in normal high mode after reset and this also the default state when the condition to exit low-power mode occurs. table 5-7 provides the power consumption equations for each of these modes table 5-7. mpc823e low-power modes operation mode udr2 (.42) equation power @ 50mhz udr2 (.42) cdr2 (.36) equation power @ 25mhz cdr2 (.36) power @ 50mhz cdr2 (.36) power @ 66mhz cdr2 (.36) normal high lpm=00 texps=1 @ 20 mw + (.78)/2 dfnh w 860mw @ 20 mw + (.555)/2 dfnh w 298 mw 575 mw 750 mw normal low lpm=00 texps=1 @ 20 mw + (.78)/2 (dfnl+1) w 450 mw @ 20 mw + (.555)/2 (dfnl+1) w 159 mw 298 mw 385 mw doze high lpm=01 texps=1 @ 20mw + 0.4(.78)/2 dfnh w 356 mw @ 20 mw + 0.4(.555)/2 dfnh w 132 mw 242 mw 312 mw doze low lpm=01 texps=1 @ 20 mw + 0.4(.78)/ 2 (dfnl+1) w 188 mw @ 20 mw + 0.4(.555)/2 (dfnl+1) w 76 mw 131 mw 166 mw sleep lpm=10 texps=1 10 mw 10 mw 10 mw 10 mw deep-sleep lpm=11 texps=1 40a 40a 40a 40a power-down lpm=11 texps=0 10a 10a 10a 10a note: the above currents are measured at 3.3v. note: the communication processor module has its own power conservation logic, which it uses to automatically shut down its own clock when idle.
motorola mpc823e reference manual 6-1 core 6 section 6 the p ower pc core the mpc823e core is where the powerpc ? architecture is implemented. it has the functionality of the powerpc branch processor and fixed-point processor and includes all the powerpc user mode (problem mode) instructions, except floating-point instructions, relevant privileged instructions, and all the registers associated with the processors and instructions. in addition, it contains part of the development support features of the mpc823e, including breakpoint and watchpoint support, program flow tracking data generation, and debug mode operation in which the core is controlled by the development support system through the debug port module. this section describes the functional specifications of the core. it is based on a document called the powerpc microprocessor family: the programming environment for 32-bit microprocessors (mpcfpe32b/ad). any reference to 64-bit implementation is not supported by this core. only a subset of the powerpc architecture books are supported, as indicated in appendix b mpc823e instruction set . 6.1 features the following is a list of the cores main features: ? 32-bit powerpc architecture ? single-issue integer machine ? variable pipeline depth architecture tailored to instruction complexity ? fully static design ? out-of-order execution termination ? branch prediction for prefetch ? 32 32-bit general-purpose register file ? precise exception model ? extensive debug/testing support
the powerpc core 6-2 mpc823e reference manual motorola core 6 6.2 basic structure of the core to accomplish its tasks, the core is divided into the following subunits: ? sequencer unit consists of the branch processor (next address generation), the instruction prefetch queue, and the interrupt handling mechanism. it controls some data structures within the register unit. ? register unit consists of all the user-visible registers, the registers scoreboard mechanism, and a history of previous operations to allow for a precise interrupt model. this module is physically split so that each data structure is implemented near the area in which it is used. ? fixed-point unit implements all fixed-point instructions, except load/store instructions. this module is subdivided into the following two blocks: o imul/idivCfixed-point multiply and divide instruction implementation. o alu/bfuCfixed-point logic, add, and subtract instruction implementation, as well as the bit field instructions. ? load/store unit implements all load and store instructions. no floating-point processor load and store instructions are implemented. 6.2.1 instruction flow within the core when fetched, instructions enter the instruction queue and enable branch folding by allowing out-of-order branch execution. nonbranch instructions reaching the top of the instruction queue are issued to the execution units. instructions can be flushed from the instruction queue in case of an exception on a previous instruction, interrupt, or miss-predicted fetch. all instructions, including branches, enter the history buffer along with processor state information that can be affected by the instructions execution. this information is used to enable out-of-order completion of instructions together with precise exception handling. when exceptions or interrupts occur, instructions can be flushed or recovered from the machine. the instruction queue is always flushed when the history buffer is recovered. an instruction retires from the machine after it finishes executing without exception and all preceding instructions are retired from the machine. figure 6-1 illustrates the cores microarchitecture.
the powerpc core motorola mpc823e reference manual 6-3 core 6 figure 6-1. block diagram of the core figure 6-2. instruction flow conceptual diagram writeback bus source buses control bus branch l-addr l-data ldst fix ldst addr imul / idiv alu / gpr history gpr (32 x 32) contr regs (2 slots / clock) (4 slots / clock) instruction queue unit next address generation sequencer core bfu instruction cache / instruction mmu interface data cache / data mmu interface data execution units history buffer instruction queue branch unit issue retire fetch writeback
the powerpc core 6-4 mpc823e reference manual motorola core 6 6.2.2 basic instruction pipeline figure 6-3 illustrates the basic instruction pipeline timing. 6.3 sequencer unit the instruction sequencer is the heart of the core. it controls data flow among execution units and register files, implements the basic instruction pipeline, fetches instructions from the memory system and issues them to available execution units, and maintains a state history so it can back up the machine in the event of an exception. the sequencer data path is illustrated in figure 6-4. in addition, the sequencer implements all branch processor instructions, including flow control and condition register instructions. figure 6-3. basic instruction pipeline timing diagram fetch decode read + execute write back l address drive l data load write back branch decode branch execute i1 i3 i2 i1 i2 i1 i2 i1 i2 i1 i1 i1 i1 load store
the powerpc core motorola mpc823e reference manual 6-5 core 6 6.3.1 flow control flow control operations, or branches disrupt normal instruction pipeline flow. a change in program flow creates bubbles in the pipeline because of the time it takes to fetch the newly targeted instruction stream. in typical code, with 4 or 5 sequential instructions between branches, the machine could waste up to 25% of its execution bandwidth waiting on branch latency. the sequencer maintains a 4-instruction deep instruction prefetch queue to execute branches in parallel with the execution of sequential instructions. ideally, a sequential instruction is issued every clock, even when branches are present in the code. this is referred to as branch folding. the instruction prefetch queue also eliminates stalls due to long latency instruction fetches and all instructions are fetched into the instruction prefetch queue, but only sequential instructions are issued to the execution units when they reach the head of the queue. branches enter the queue to mark watchpoints. see section 20 development capabilities and interface for details. since branches do not prevent the issue of sequential instructions unless they come in pairs, the performance impact of entering branches in the instruction prefetch queue is negligible. figure 6-4. sequencer data path instruction address generator cc unit 32 instruction buffer 32 instruction prefetch queue (4) 32 branch condition evaluation execution units and registers files instruction memory system read / write busses
the powerpc core 6-6 mpc823e reference manual motorola core 6 in addition to branch folding, the core implements a branch reservation station and static branch prediction so branches can issue as early as possible. the reservation station allows a branch instruction to issue even before its condition is ready. with the branch issued and out of the way, instruction prefetch can continue while the branch operand is being computed and the condition is evaluated. static branch prediction determines which instruction stream is prefetched while the branch is being resolved. when the branch operand becomes available, it is forwarded to the branch unit and the condition is evaluated. branch instructions whose condition is unavailable and forced to issue to the reservation station are said to be predicted and these branches, which later turn out to have followed the wrong path, are said to be mispredicted. branch instructions that issue with source data already available are unpredicted and those instructions fetched under a predicted branch are conditionally fetched. the core ignores conditionally prefetched instructions fetched under a mispredicted branch. 6.3.2 issuing instructions the sequencer tries to issue a sequential instruction on each clock whenever possible. however, for an instruction to issue, the execution unit must be available and able to discern whether or not the required source data is available and to ensure that no other instruction still in execution targets the same destination register. the sequencer informs the execution units of the existence of the instruction on the instruction bus. the execution units then decode the instruction, interrogate the register unit (if the operands and targets are free), and inform the sequencer that it accepts the instruction for execution. table 6-1. branch prediction policy branch type default prediction (y=0) modified prediction (y=1) bc with negative offset taken fall through bc with positive offset fall through taken bclr or bcctr (lk or ctr) address ready fall through taken bclr or bcctr (lk or ctr) address not ready wait wait b (unconditional branch) taken taken
the powerpc core motorola mpc823e reference manual 6-7 core 6 6.3.3 interrupts the core interrupts can be generated when an exception occurs. an exception results when certain instructions are executed or an asynchronous external event occurs. there are five exception sources in the mpc823e: ? external interrupt request ? certain memory access conditions (protection faults and bus error) ? internal errors, such as an attempt to execute an unimplemented opcode or floating-point arithmetic overflow ? trap instructions ? internal exceptions (breakpoints and debug counters expiration) interrupt handling is transparent to user mode code and uses the same mechanism to handle all types of exceptions. when a user mode instruction experiences an exception, the machine is placed into privileged state and control is transferred to a software exception handler routine located at some offset within a memory-based vector table. each interrupt generated in the machine transfers control to a different address in the vector table. for more information on initializing the base address of the vector table, refer to table 6-6 as well as the powerpc definition of the machine state register. when the exception has been handled, the handler can continue executing your program without ever knowing that an event has occurred. as specified in the powerpc microprocessor family: the programming environment for 32-bit microprocessors , the core implements a precise interrupt model. this means that when an interrupt is taken, the following conditions are met: ? no instruction that logically follows the faulting instruction in the code stream has started executing. ? all instructions preceding the faulting instruction appear to have completed with respect to the executing processor. ? the precise location (address) of the faulting instruction is known to the exception handler. ? the instruction causing the exception might not have started executing (before interrupt), could be partially completed, or has completed (after interrupt), depending on the interrupt and instruction types. see table 6-2 for details. in any case, a partially completed instruction is restartable and can be reexecuted after the interrupt is handled. this precise exception model can simplify and speed up exception processing because the software does not have to manually save the machines internal pipeline states, unwind the pipelines, or cleanly terminate the faulting instruction stream. nor does it have to reverse the process to resume execution of the faulting stream.
the powerpc core 6-8 mpc823e reference manual motorola core 6 6.3.4 implementing the precise exception model to achieve maximum performance, many pieces of the instruction stream are concurrently processed by the core independent of the sequence specified by the executing program. instructions execute in parallel and are completely random. the hardware ensures that this out-of-order operation never has an effect different than that specified by the program. this requirement is most difficult to assure when an interrupt occurs after instructions that logically follow the faulting instruction or have already completed. at the time of an interrupt, the machine state becomes visible to other processes and, therefore, must be in the appropriate architecturally specified condition. the core takes care of this in the hardware by automatically backing up the machine to the instruction which caused the interrupt and is, therefore, said to implement a precise exception model. this is, of course, assuming that the instruction causing the exception has not begun when the interrupt occurs. to recover from an interrupt, a history buffer is used. this buffer is a fifo queue that records the relevant machine state at the time of each instruction issue. instructions are placed on the tail of the queue when they are issued and percolated to the head of the queue while they are in execution. instructions remain in the queue until they complete execution and all preceding instructions have been completed to a point where no exception can be generated (in the core, such a condition is fulfilled by waiting for full completion). table 6-2. before and after interrupts interrupt type instruction type before / after contents of srr0 hard reset any na undefined system reset any before next instruction to execute machine check interrupt any before faulting instruction implementation specific instruction / data tlb miss / error interrupts any before faulting fetch or load/store other asynchronous interrupts (noninstruction related interrupts) any before next instruction to execute alignment interrupt load / store before faulting instruction privileged instruction any privileged instruction before faulting instruction trap tw, twi before faulting instruction system call interrupt sc after next instruction to execute trace any after next instruction to execute debug i- breakpoint any before faulting instruction debug l- breakpoint load / store after faulting instruction + 4 implementation dependent software emulation interrupt na before faulting instruction floating-point unavailable floating-point before faulting instruction
the powerpc core motorola mpc823e reference manual 6-9 core 6 in the event of an exception, the machine state necessary to recover the architectural state is available. as instructions finish executing, they are released (retired) from the queue and the buffer storage is reclaimed for new instructions entering the queue. an exception can be detected at any time during instruction execution and is recorded in the history buffer when the instruction finishes execution. the exception is not recognized until the faulting instruction reaches the head of the history queue, but once the exception is recognized, an interrupt process begins. the queue is reversed and the machine is restored to its state at the time the instruction is issued. machine state is restored at a maximum rate of two floating-point and two fixed-point instructions per clock. to correctly restore the architectural state, the history buffer must record the value of the destination before the instruction is executed. the destination of a store instruction, however, is in memory and it is not practical from a performance standpoint to always read memory before writing it. therefore, stores issue immediately to store buffers, but do not update memory until all previous instructions have finished executing without exception or the store has reached the head of the history buffer. the history buffer has enough storage to hold the state of six instructions, but no more than four fixed-point instructions. the other two instructions can be condition code or branch instructions. in the event of a long latency instruction, it is possible that issued instructions will fill the history buffer. if so, instruction issue waits until the long latency operation finishes. the following types of instructions can potentially cause the history buffer to fill: ? floating-point arithmetic instructions ? integer divide instructions ? instructions that affect or use resources external to the core (load/store instructions) figure 6-5. history buffer queue queue tail queue head history buffer queue issued completed instructions writeback retired instructions instructions
the powerpc core 6-10 mpc823e reference manual motorola core 6 6.3.4.1 restartability after an interrupt most of the interrupt cases in the core are always restartable. some interrupts may be unable to be restarted because they can be recognized when the machine status save/restore 0 and 1 registers (srr0 and srr1) are busy. such interrupts in the powerpc architecture are known as system reset and machine check. all other interrupt types defined in the architecture must always be restartable. by convention, no interrupt generating instruction must be executed between the start of an interrupt handler and the save of the registers altered by any interrupt or between restore of these registers and the execution of the rfi instruction. these registers being the srr0 and srr1 registers or the data address register (dar) and data storage interrupt status register (dsisr) for some interrupt types. external interrupts are also masked in these areas. in the core, two implementation-specific interrupt types can have this characteristicdebug port unmaskable interrupt and breakpoint interrupt in nonmaskable mode. since there might be a situation in which it is preferable to be restartable, such as in the mentioned implementation-specific interrupts, a mechanism is defined to notify the interrupt handler code whether it is in a restartable state. the mechanism uses a bit within the machine state register (msr) called the recoverable interrupt bit (msr ri ). the msr ri shadow bit in the srr1 register indicates whether or not the interrupt is restartable. this bit does not need to be checked on interrupt types that are restartable by convention, except those previously mentioned. the msr ri bit follows a similar behavior as the external interrupt enable bit (msr ee ). every time an interrupt occurs, msr ri is copied to its shadow in the srr1 register (like the msr) and cleared. every time an rfi instruction is executed, msr ri is copied from its shadow in the srr1 register. in addition, it can be altered by the software via the mtmsr instruction. the msr ri bit is intended to be set by the interrupt handler software after saving the machine state, (registers srr0, srr1, dar, and dsisr if needed) and cleared by the interrupt handler software before retrieving the machine state. in critical code sections where msr ee is negated but the srr0 and srr1 registers are not busy, msr ri must be left asserted. in these cases, if an interrupt occurs it is restartable. to facilitate the software manipulation of the msr ri and msr ee bits, the core includes special commands implemented as move to special register. the following table defines these special register mnemonics. a write of any data to these locations performs the operation specified in the following table. any read from these locations is treated like any other unimplemented instruction and, therefore, results in an implementation-dependent software emulation interrupt.
the powerpc core motorola mpc823e reference manual 6-11 core 6 6.3.5 processing an interrupt the following table provides the significant events that occur when processing an interrupt. table 6-3. special ports to machine state register bits mnemonic spr msr ee msr ri used for eie 80 1 1 external interrupt enable: end of interrupt handlers prologue, enable nested external interrupts; end of critical code segment in which external interrupts were disabled eid 81 0 1 external interrupt disable, but other interrupts are recoverable: end of interrupt handlers prologue, keep external nested interrupts disabled; start of critical code segment in which external interrupts are disabled nri 82 0 0 nonrecoverable interrupt: start of interrupt handlers epilogue table 6-4. interrupt latency time point fetch issue instruction complete kill pipeline a faulting instruction issue b instruction complete and all previous instructions complete c start fetch handler kill pipeline d b + 3 clocks e first instruction of handler issued notes: 1. at time point a an instruction that will cause an interrupt is issued. 2. at time point b the excepting instruction has reached the head of the history queue, thus implying that all instructions preceding it in the code stream have ?nished execution without generating any interrupt. also, the excepting instruction itself has completed execution. at this time the exception is recognized and exception processing begins. if, at this point, the instruction had not generated an exception, it would have been retired. 3. at time point c the sequencer starts to fetch the interrupt handlers ?rst instruction. 4. by time point d the state of the machine prior to the issue of the excepting instruction is restored (the machine is restored to its state at time. 5. at time point e the machine state register and instruction pointer of the executing process have been saved and control has been transferred to the interrupt handler routine.
the powerpc core 6-12 mpc823e reference manual motorola core 6 at time point a the excepting instruction issues and begins executing. during the interval between a and b, previously issued instructions are finishing execution. this interval is equivalent to the time required for all instructions currently in progress to complete. at time point b, the exception is recognized and during the interval between b and d the machine state is being restored. this time is a maximum of 10 cycles. at time point c, the core starts fetching the first instruction of the exception handler if the interrupt handler is external. it is 5 cycles if it is in the instruction cache and no show mode is on. at time point d all state has been restored and during the interval between d and e, the machine is saving context information in the srr0 and srr1 registers, disabling interrupts, placing the machine in privileged mode, and continues the process of fetching the first instructions of the interrupt handler from the vector table. the interval between d and e requires a minimum of one clock. the interval between c and e depends on the memory system and is the time it takes to fetch the first instruction of the interrupt handler. for full history buffer restore time, it is no less then two clocks. 6.3.6 serialization the core has multiple execution units, each of which can be executing different instructions at the same time. this is normally transparent to your program, but in some special circumstances (debugging, i/o control, multiprocessor synchronization) it might become necessary to force the machine to serialize. there are two possible serialization actions defined for the core: ? execution serializationinstruction issue is halted until all instructions currently in progress have completed execution, all internal pipeline stages and instruction buffers have emptied, and all outstanding memory transactions are completed. ? fetch serializationinstruction fetch is halted until all instructions currently in the processor have completed execution. after fetch serialization, the machine is completely synchronized. an attempt to issue a serializing instruction causes the machine to serialize before the instruction issues. only the sync instruction guarantees serialization across powerpc implementations. fetching an isync instruction causes fetch serialization. also, when the serialize mode bit (ctrl ser ) is asserted or is in debug mode, any instruction can cause fetch serialization. 6.3.6.1 latency the time required to serialize the machine is also the amount of time needed to complete the instructions currently in progress. this time is heavily dependent on the instructions in progress and the memory system latency. it is impossible to put an absolute upper bound on this time because the memory system design is not under the cores control. the time to complete the current instruction is generally the machine serialization time and the specific instruction execution time determines how long serialization takes. this can be either divide, load, or store a multiple, string, or pair of simple load/store instructions.
the powerpc core motorola mpc823e reference manual 6-13 core 6 6.3.7 the external interrupt the core provides one external interrupt line: the architectural maskable external interrupt. in the mpc823e, this interrupt is generated by the on-chip interrupt controller. it is software acknowledged and maskable by the msr ee bit, which is automatically cleared by the hardware to disable external interrupts when any interrupt is taken. 6.3.7.1 latency when an external interrupt is detected, every instruction that can retire from the history buffer does so and the interrupt is assigned to the instruction at the head of the history buffer (at point b in table 6-4). however, the following conditions must be met before the instruction at the head of the queue can retire. ? the instruction must be completed without exception ? the instruction must either be a mtspr , mtmsr , or rfi instruction, a memory reference, or a storage or cache control instruction. any instruction that does not meet these criteria is discarded with all of its side effects and the execution at the end of the interrupt handler resumes with the first instruction that was discarded. if all the instructions in the history buffer were allowed to complete, execution at the end of the interrupt handler resumes with the next instruction. external interrupt latency depends on the time required to reference memory. the measurement is equal to the time taken for one of the following three possible events, in addition to the interval from b to e as shown in table 6-4. longest load/store multiple/string instruction used or one bus cycle for aligned access or two bus cycles for unaligned access actual system-level interrupt latency can be worse than just the interval from b to e. if the instruction prior to the one in which the interrupt was assigned generates an exception, then the exception is recognized first. if minimal interrupt latency is an important system parameter, interrupt handlers must save the machine context and reenable external interrupt as rapidly as possible so that a pending external interrupt receives service quickly.
the powerpc core 6-14 mpc823e reference manual motorola core 6 6.3.8 interrupt ordering there are two main types of interrupts: ? instruction-related interrupts ? asynchronous interrupts instruction-related exceptions (interrupt causes) are detected while the instruction is in various stages of being processed by the core. exceptions found early in instruction processing preclude detection of further exceptions. this earlier interrupt will eventually be taken. if more than one instruction in the pipeline causes an exception, only the first exception is taken and causes an interrupt. the remaining instruction-induced exceptions are ignored. the following table lists the instruction-related interrupts in the order of detection within the instruction processing. table 6-5. instruction-related interrupt detection order number interrupt type cause 1 trace trace bit asserted 1 2 implementation dependent instruction tlb miss instruction memory management unit tlb miss 3 implementation dependent instruction tlb error instruction memory management unit protection / translation error 4 machine check interrupt fetch error 5 debug i- breakpoint match detection 6 implementation dependent software emulation interrupt attempt to invoke unimplemented feature 1 floating-point unavailable attempt to is made to execute floating-point instruction and msr fp =0 7 2 privileged instruction attempt to execute privileged instruction in problem mode alignment interrupt load/store checking system call interrupt sc instruction trap trap instruction 8 implementation dependent data tlb miss data memory management unit tlb miss 9 implementation dependent data tlb error data memory management unit tlb protection/ translation error 10 machine check interrupt load or store access error 11 debug l- breakpoint match detection notes: 1. the trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second instruction. this, of course, refers to this second instruction. 2. exclusive for any one instruction.
the powerpc core motorola mpc823e reference manual 6-15 core 6 more than one asynchronous interrupt cause or exception can be present at any time. however, when more than one interrupt causes exist, only the highest priority interrupt is taken, as shown in the following table. 6.4 the register unit the fixed-point registers bank holds thirty-two 32-bit fixed-point registers and some control registers. the register unit holds the general register files of the core and performs the following operations: ? decodes the operand fields of all sequential instructions ? drives the operand buses, as requested by the execution unit ? performs scoreboard checking and signing ? samples the resulting data from the writeback bus table 6-6. interrupt priority mapping number interrupt type cause 1 development port nonmaskable interrupt signal from the development port 2 system reset nmi_l assertion 3 instruction-related interrupts instruction processing 4 peripheral breakpoint request or development port maskable interrupt breakpoint signal from any peripheral 5 external interrupt signal from the interrupt controller 6 decrementer interrupt decrementer request
the powerpc core 6-16 mpc823e reference manual motorola core 6 6.4.1 control registers the following tables describe the core control registers, also known as special-purpose registers, implemented within the mpc823e. table 6-7. standard special-purpose registers spr register name privileged serialize access decimal spr 5:9 spr 0:4 1 00000 00001 xer no write: full sync read: sync relative to load/ store operations 8 00000 01000 lr no no 9 00000 01001 ctr no no 18 00000 10010 dsisr yes write: full sync read: sync relative to load/ store operations 19 00000 10011 dar yes write: full sync read: sync relative to load/ store operations 22 00000 10110 dec yes write 26 00000 11010 srr0 yes write 27 00000 11011 srr1 yes write 272 01000 10000 sprg0 yes write 273 01000 10001 sprg1 yes write 274 01000 10010 sprg2 yes write 275 01000 10011 sprg3 yes write 287 01000 11111 pvr yes no (read-only register) table 6-8. standard timebase register mapping spr register name privileged serialize access decimal spr 5:9 spr 0:4 268 01000 01100 tbl read 2 no write - as a store 269 01000 01101 tbu read 2 no write - as a store 284 01000 11100 tbl write 3 yes write - as a store 285 01000 11101 tbu write 3 yes write - as a store notes: 1. extended opcode for mftb , 371 rather then 339. 2. any write ( mtspr ) to this address results in an implementation-dependent software emulation interrupt. 3. any read ( mftb ) to this address results in an implementation-dependent software emulation interrupt.
the powerpc core motorola mpc823e reference manual 6-17 core 6 table 6-9. additional special-purpose registers spr register name privileged serialize access decimal spr 5:9 spr 0:4 80 00010 10000 eie 1 yes write 81 00010 10001 eid yes write 82 00010 10010 nri yes write 144 00100 10000 cmpa 1 debug 3 fetch sync on write 145 00100 10001 cmpb debug fetch sync on write 146 00100 10010 cmpc debug fetch sync on write 147 00100 10011 cmpd debug fetch sync on write 148 00100 10100 icr debug fetch sync on write 149 00100 10101 der debug fetch sync on write 150 00100 10110 counta debug fetch sync on write 151 00100 10111 countb debug fetch sync on write 152 00100 11000 cmpe debug write: fetch sync read: synch relative to load/store operations 153 00100 11001 cmpf debug write: fetch sync read: synch relative to load/store operations 154 00100 11010 cmpg debug write: fetch sync read: synch relative to load/store operations 155 00100 11011 cmph debug write: fetch sync read: synch relative to load/store operations 156 00100 11100 lctrl1 debug write: fetch sync read: synch relative to load/store operations 157 00100 11101 lctrl2 debug write: fetch sync read: synch relative to load/store operations 158 00100 11110 ictrl debug fetch sync on write 159 00100 11111 bar debug write: fetch sync read: synch relative to load/store operations 630 10011 10110 dpdr debug read and write 631 10011 10111 dpir 4 yes fetch
the powerpc core 6-18 mpc823e reference manual motorola core 6 638 10011 11110 immr yes write - as a store 560 10001 10000 ic_csr yes write - as a store 561 10001 10001 ic_adr yes write - as a store 562 10001 10010 ic_dat yes write - as a store 568 10001 11000 dc_csr yes write - as a store 569 10001 11001 dc_adr yes write - as a store 570 10001 11010 dc_dat yes write - as a store 784 11000 10000 mi_ctr yes write - as a store 786 11000 10010 mi_ap yes write - as a store 787 11000 10011 mi_epn yes write - as a store 789 11000 10101 mi_twc (mi_l1dl2p) yes write - as a store 790 11000 10110 mi_rpn yes write - as a store 816 11001 10000 mi_cam yes write - as a store 817 11001 10001 mi_ram0 yes write - as a store 818 11001 10010 mi_ram1 yes write - as a store 792 11000 11000 md_ctr yes write - as a store 793 11000 11001 m_casid yes write - as a store 794 11000 11010 md_ap yes write - as a store 795 11000 11011 md_epn yes write - as a store 796 11000 11100 m_twb (md_l1p) yes write - as a store 797 11000 11101 md_twc (md_l1dl2p) yes write - as a store 798 11000 11110 md_rpn yes write - as a store 799 11000 11111 m_tw (m_save) yes write - as a store 824 11001 11000 md_cam yes write - as a store 825 11001 11001 md_ram0 yes write - as a store 826 11001 11010 md_ram1 yes write - as a store notes: 1. see section 6.3.4.1 restartability after an interrupt . 2. refer to section 20.6.2 development port registers . 3. protection of registers with debug privileges is described in section 20.6.1 protecting the development port registers . 4. this register is a fetch-only register. using mtspr is ignored and using mfspr gives an unde?ned value. table 6-9. additional special-purpose registers (continued) spr register name privileged serialize access decimal spr 5:9 spr 0:4
the powerpc core motorola mpc823e reference manual 6-19 core 6 6.4.1.1 physical location of special registers some of the special registers in the core are physically located outside of the core. access to these registers is gained the same way as any other special registervia the appropriate mtspr , mfspr instructions through the internal chip buses. apart from the powerpc timebase counter and decrementer, in the current implementation the following encoding is reserved for special registers not located within the core. for these registers, a bus cycle is performed on the internal bus with the following address. if any address error occurs on this cycle, an implementation-dependent software emulation interrupt is taken. table 6-10. other control registers description name comments privileged serialize access machine state register msr yes write fetch sync condition register cr no only mtcrf table 6-11. encoding special registers located outside the core spr reserved for spr 5:9 spr 0:4 100xx 110xx xxxxx registers external to the core 1x0xx x0xxx reserved 10011 x0xxx system interface unit internal registers 0xxxx xxxxx the internal bus signifying decrementer or timebase 10000 x0xxx reserved 10000 x1xxx reserved 1100x x0xxx instruction memory management unit implementation-specific control 1100x x1xxx data memory management unit implementation-specific control 10001 x00xx instruction cache registers 10001 x10xx data cache registers 0:17 18:22 23:27 28:31 0. .0 spr 0:4 spr 5:9 0000
the powerpc core 6-20 mpc823e reference manual motorola core 6 6.4.1.2 p ower pc standard control register bit assignment 6.4.1.2.1 machine state register. the 32-bit machine state register (msr) defines the state of the processor. it can be read by the mfmsr instruction. however, it can be modified by the mtmsr , sc , and rfi instructions, as well as the hard reset configuration word. refer to section 4.3.1.1 hard reset configuration word for more information. bits 0C12reserved these bits are reserved and must be set to 0. bits 0, 5, and 9 are loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. reserved bits in the msr are set from the source value on write and return the value last set for it on read. powpower management enable when this bit is set, it allows you to automatically switch between low and high frequency operation or between normal low mode and normal high mode. when this bit is cleared, power management is disabled. refer to section 5 clocks and power control for more information on bus power management. bit 14reserved this bit is reserved and must be set to 0. ileinterrupt little-endian mode when an exception occurs, this bit is copied into the msr to select the endian mode for the context established by the exception. 0 = big-endian mode is selected. 1 = little-endian mode is selected. eeexternal interrupt enable this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. msr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved pow res ile reset 0 000 r/w r/w r/w r/w r/w bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ee pr fp me fe0 se be fe1 res ip ir dr reserved ri le reset 00000000000 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: = undefined.
the powerpc core motorola mpc823e reference manual 6-21 core 6 prproblem state this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. fpfloating-point available this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. memachine check enable this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. fe0floating-point exception mode 0 this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. sesingle-step trace enable this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. bebranch trace enable this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. fe1floating-point exception mode 1 this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. bit 24reserved this bit is reserved and must be set to 0. it is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. reserved bits in the msr are set from the source value on write and return the value last set for it on read. ipinterrupt prefix this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the reset value of this bit is determined by the hard reset configuration word. for more information, see section 4.3.1.1 hard reset configuration word . 0 = the interrupt prefix is 0x000n_nnnn. 1 = the interrupt prefix is 0xfffn_nnnn. irinstruction relocate this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed.
the powerpc core 6-22 mpc823e reference manual motorola core 6 drdata relocate this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. bits 28 and 29reserved these bits are reserved and must be set to 0. reserved bits in the msr are set from the source value on write and return the value last set for it on read. rirecoverable interrupt this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. lelittle-endian mode this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in the msr is loaded from this bit when an rfi is executed. this bit is loaded from the ile bit when an interrupt is taken. 6.4.1.2.2 the condition register. the condition register (cr) contains eight 4-bit condition fields. each field can have one of the following formats and the software can assign an arbitrary meaning to them. ? bit 0negative (lt). the result is negative. ? bit 1positive (gt). the result is positive. ? bit 2zero (eq). the result is zero. ? bit 3summary overflow (so). the values of this bit is copied from xer so .
the powerpc core motorola mpc823e reference manual 6-23 core 6 6.4.1.2.3 fixed-point exception cause register. the following table provides the bit assignments for the fixed-point exception cause register (xer). the bits are based on the final result produced by executing an instruction. sosummary overflow this bit is set when an instruction other than mtspr sets the ov bit. once so is set, it stays that way until an mtspr or mcrxr instruction clears it. it is not altered by compare instructions or other instructions that cannot overflow. so is cleared and ov is set when an mtspr instruction is executed, which supplies the zero values for these bits. ovoverflow when this bit is set, it indicates that an overflow has occurred during the execution of an instruction. the add, subtract, and negate instructions with oe equal to 1, set this bit if the carry out of the msb is not equal to that carry out of the msb+1. the multiply low and divide instructions with oe equal to 1, set this bit if the result cannot be represented in 64 bits ( mulld , divd , divdu ) or 32 bits ( mullw , divw , divwu ). the ov bit is not altered by compare instructions that cannot overflow, except mtspr to the xer and mcrxr . cacarry this bit is set during execution of the following instructions. it is not altered by compare instructions or by other instructions that cannot carry, except shift right algebraic, mtspr to the xer, and mcrxr . ? add carrying, subtract from carrying, add extended, and subtract from extended instructions set ca if there is a carry out of the msb. otherwise, it is cleared. ? the shift right algebraic instructions set ca if any 1 bits have been shifted out of a negative operand. otherwise, it is cleared. bits 3C24reserved these bits are reserved and must be set to 0. bcntbyte count for load/store string operations this field specifies the number of bytes to be transferred by a lswx or stswx instruction. xer bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field so ov ca reserved reset 000 0 r/w r/w r/w r/w r/w bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved bcnt reset 00 r/w r/w r/w
the powerpc core 6-24 mpc823e reference manual motorola core 6 6.4.1.3 initializing the control registers 6.4.1.3.1 system reset interrupt. a system reset interrupt occurs when the irq0 pin is asserted. the only control registers affected by the system reset interrupt are the msr, srr0, and srr1 registers. for information on the values of these registers, refer to section 7.3.7.3.1 system reset interrupt . 6.4.1.3.2 hard/soft reset. when a hard or soft reset occurs, the registers affected by system reset are set in the same way. the following list shows how each register is set. ? srr0, srr1set to an undefined value. ? msr ip programmable. ? msr me set to zero. ? ictrlset to 0. ? lctrl1set to 0. ? lctrl2set to 0. ? counta 16-31 set to 0. ? countb 16-31 set to 0. ? icrset to 0 (no interrupt occurred). ? der 2,14,28:31 set to 1 (all debug-specific interrupts cause debug mode entry). 6.5 the fixed-point unit the fixed-point unit implements all fixed-point processor instructions, except the fixed-point storage access instructions that are implemented by the load/store unit. refer to the powerpc microprocessor family: the programming environment for 32-bit microprocessors manual for more information. 6.5.1 xer update in divide instructions the divide instructions have a relatively long latency, but those instructions can update the ov bit in the xer after one cycle. therefore, data dependency on the xer is limited to one cycle, although the divide instruction latency can be a maximum of 11 clocks.
the powerpc core motorola mpc823e reference manual 6-25 core 6 6.6 the load/store unit the load/store unit handles all data transfers between the register file and chip internal bus. it is implemented as an independent execution unit so that stalls in the memory pipeline do not cause the master instruction pipeline to stall, unless there is a data dependency. the unit is fully pipelined so that memory instructions of any size can be issued on back-to-back cycles. there is a 32-bit wide data path between the load/store unit and fixed-point register file. single-word accesses to the internal on-chip data ram require one clock, resulting in two clock latencies and double-word accesses require two clocks, which results in three clock latencies. because the internal bus is 32 bits wide, double-word transfers take two bus accesses. the load/store unit implements all of the powerpc load/store instructions in hardware, including unaligned and string accesses. the following is a list of the load/store units main features: ? supports many instructions ? two-entry load/store instruction address queue ? pipelined operation ? minimal load latencyC2 clocks using 1 clock on-chip data ram ? minimal store latencyC1 clock since the load/store unit ends the store execution in 2 clocks, using 1 clock on-chip data ram. ? load/store multiple and string instructions synchronize ? load/store breakpoint/watchpoint detection support figure 6-6 illustrates a conceptual block diagram of the load/store unit and its two queues. the address queue is a 2-entry queue shared by all load/store instructions and the fixed-point data queue is a 2-entry, 32-bit wide queue that holds fixed-point data. the load/store unit has a dedicated writeback bus so that loaded data received from the internal bus is written directly back to the fixed- or floating-point register files.
the powerpc core 6-26 mpc823e reference manual motorola core 6 to execute multiple ( lmw, stmw ) instructions, string instructions, and unaligned accesses, the load/store unit contains an address incrementor that generates the needed addresses. this allows the unit to execute the unaligned accesses without stalling the master instruction pipeline. 6.6.1 issuing load/store instructions when load or store instructions are encountered, the load/store unit checks the scoreboard to determine if all of the operands are available. these operands include: ? address register operands ? source data register operands (for store instructions) ? destination data register operands (for load instructions) ? destination address register operands (for load/store with update instructions) if all operands are available, the load/store unit takes the instruction and enables the sequencer to issue a new instruction. then, using a dedicated interface, the load/store unit notifies the integer unit of the need to calculate the effective address. all load/store instructions are executed and terminated in order. figure 6-6. load/store unit functional block diagram fixed-point queue address fixed-point store data load / store unit fixed-point load data d-cache / d-mmu core 32 fixed-point registers file fixed-point unit 32 32 32 address queue increment and data 32 32 interface
the powerpc core motorola mpc823e reference manual 6-27 core 6 if there are no prior instructions waiting in the address queue, the load/store instruction is issued to the data cache immediately at the time the instruction is taken. otherwise, if there are prior instructions remaining whose addresses have not yet been issued to the data cache, the instruction is inserted into the address queue and data is inserted into the respective store data queue. for load/store with update instructions, the destination address register is written back on the following clock, regardless of the address queues state. 6.6.2 serializing load/store instructions the following load/store instructions are not taken until all previous instructions have terminated. ? load/store multiple instructions lmw , stmw ? storage synchronization instructions lwarx , stwcx , sync ? string instructions lswi , lswx , stswi , stswx ? move to internal special registers and move to off-core special registers the following load/store instructions must terminate before more instructions can be issued. ? load/store multiple instructions lmw , stmw ? storage synchronization instructions lwarx , stwcx , sync ? string instructions lswi , lswx , stswi , stswx 6.6.3 instructions issued to the data cache the load/store unit pipelines load accesses. the individual cache cycles of all multiregister instructions and unaligned accesses are pipelined into the data cache interface. 6.6.4 issuing store instruction cycles a new store instruction is not issued to the data cache until all prior instructions have terminated without an exception because the core supports the precise interrupt model. if a load instruction is followed by a store instruction, a one clock delay is inserted between the load bus cycle termination and the store cycle issue. 6.6.5 issuing nonspeculative load instructions load instructions targeted at a nonspeculative memory region are identified as nonspeculative one clock cycle after the previous load/store bus cycle termination, but only if all prior instructions have terminated normally and without an exception. the nonspeculative identification relates to the state of the cycles associated instruction. for lmw , although the cycles are pipelined into the bus, they are all marked as nonspeculative because the instruction is nonspeculative. with a single register load instruction where more than one bus cycle is generated, some of the cycles can be marked as speculative and later cycles can be marked as nonspeculative after all prior instructions terminate. when executing speculative load cycles to the nonspeculative external memory region, no external cycles are generated until the load instruction becomes nonspeculative.
the powerpc core 6-28 mpc823e reference manual motorola core 6 6.6.6 executing unaligned instructions the load/store unit supports fixed-point unaligned accesses in the hardware. the 32-bit l-bus only supports naturally aligned transfers. for an unaligned instruction, the load/store unit breaks the instruction into a series of aligned transfers that are pipelined into the bus. figure 6-7 illustrates the number of bus cycles needed to execute unaligned instructions. 00h 00 01 02 03 1 bus cycle 04h 04 05 06 07 00h 00 01 02 03 1 bus cycle 04h 04 05 06 07 00h 00 01 02 03 1 bus cycle 04h 04 05 06 07 00h 00 01 02 03 2 bus cycles 04h 04 05 06 07 00h 00 01 02 03 2 bus cycles 04h 04 05 06 07 00h 00 01 02 03 2 bus cycles 04h 04 05 06 07 00h 00 01 02 03 3 bus cycles 04h 04 05 06 07 00h 00 01 02 03 3 bus cycles 04h 04 05 06 07 figure 6-7. number of bus cycles needed for unaligned, single register fixed-point load/store instructions
the powerpc core motorola mpc823e reference manual 6-29 core 6 6.6.7 little-endian mode support the load/store unit implements the little-endian mode as it is specified by the powerpc architecture and in this mode the modified address is issued to the data cache. for an individual scalar unaligned transfer or an attempted execution of a multiple/string instruction, an alignment exception is generated. 6.6.8 atomic update primitives the lwarx and stwcx instructions are atomic update primitives. storage reservation accesses made by the same processor are implemented by the load/store unit. the external bus interface module implements storage reservation as it relates to accesses made by external bus masters. accesses made by other internal masters to internal memories implements storage reservation as it relates to special internal bus snoop logic. this logic is implemented in the data cache. when a lwarx instruction is executed the load/store unit issues a cycle to the data cache with a special attribute. for an external memory access, this attribute causes the external bus interface module to set a storage reservation on the cycle address. the external bus interface module is then responsible for snooping the external bus or getting an indication from external snoop logic if the storage reservation is broken by some other processor accessing the same location. when an stwcx instruction to external memory is executed, the external bus interface module checks to see if a reservation was lost. if loss of reservation has occurred, the cycle is blocked from going to the external bus and the external bus interface module notifies the load/store unit of a stwcx failure. the mpc823e storage reservation supplies hooks for the support of storage reservation implementation in a hierarchical bus structure. for a full description of the storage reservation mechanism, refer to section 7 powerpc architecture compliance . in case of storage reservation on internal memory, a lwarx indication causes the on-chip snoop logic to latch the address. this logic notifies the load/store unit in the case of an internal master store access, then the reservation is reset. if a new lwarx instruction address phase is successfully executed it replaces any previous storage reservation address at the appropriate snoop logic. however, when an stwcx instruction is executed, the storage reservation is canceled, unless an alignment interrupt condition is detected.
the powerpc core 6-30 mpc823e reference manual motorola core 6 6.6.9 instruction timing the following table summarizes the different load/store instructions timing in the case of zero wait state memory references on a parked bus. with external memory accesses, pipelined external accesses are assumed. string instructions are broken into a series of aligned bus accesses. figure 6-8 illustrates the maximum number of bus cycles needed for string instruction execution. 6.6.10 stalling storage control instructions a storage control instruction waits one clock before it is taken. 6.6.11 accessing off-core special registers access to special registers mtspr and mfspr implemented off-core is executed by the load/store unit via the internal bus using a special cycle. refer to section 6.4.1.1 physical location of special registers for detailed information. if the access terminates in a bus error, then an implementation-dependent software emulation interrupt is taken. all write operations to off-core special registers ( mtspr ) are previously synchronized. in other words, the instruction is not taken until all prior instructions terminate. table 6-12. load/store instructions timing instruction type latency cleared from load/store unit data cache external memory data cache external memory fixed-point single target register load (aligned) 2 clocks 5 clocks 2 clocks 5 clocks fixed-point single target register store (aligned) 1 clock 1 clock 2 clocks 5 clocks load/store multiple 1 + n 1 + n note: n denotes the number of registers transferred. 00h 00 01 02 03 04h 04 05 06 07 2 bus cycles 08h 08 09 0a 0b word transfers 3 bus cycles 0ch 0c 0d 0e 0f 10h 10 11 12 13 14h 14 15 16 17 2 bus cycles 18h 18 19 1a 1b figure 6-8. number of bus cycles needed for string instruction execution 3n n1 + 3 -------------- ? ?? ++ 3n n1 + 3 -------------- ? ?? ++
the powerpc core motorola mpc823e reference manual 6-31 core 6 6.6.12 storage control instructions cache management instructions and lookaside buffer management instructions are implemented by the load/store unit. these instructions are implemented as the special bus write cycles, which are issued to the data cache interface. 6.6.13 exceptions 6.6.13.1 dar, dsisr, and bar operation. the load/store unit keeps track of all instructions and bus cycles. when a bus error occurs, the data address register (dar) is loaded with the cycles effective address. for a multicycle instruction, the effective address of the first offending cycle is loaded. the data storage interrupt status register (dsisr) notifies the error when an exception caused by the load/store occurs. for a memory management unit error, this register is loaded with the error status delivered by the memory management unit. for other exceptions, the dsisr is loaded with the instruction information as defined by the powerpc architecture for alignment exception. the breakpoint address register (bar) notifies the address on which an l-bus breakpoint occurred. for a multicycle instruction, the bar contains the address of the first cycle with which the breakpoint condition was associated. the bar has a valid value only when a data breakpoint interrupt is taken. at any other time, its value is boundedly undefined. the following situations cause the dar, bar, and dsisr registers to be updated. table 6-13. value summary of the dar, bar, and dsisr registers interrupt type dar value dsisr value bar value data storage interrupt cycle ea memory management unit error status undefined alignment interrupt data ea instruction information undefined l-bus breakpoint interrupt does not change does not change cycle ea machine check interrupt cycle ea instruction information undefined implementation dependent software emulation interrupt does not change does not change undefined floating-point unavailable interrupt does not change does not change undefined program interrupt does not change does not change does not change
motorola mpc823e reference manual 7-1 ppc architecture 7 compliance section 7 p ower pc architecture compliance this section describes implementation-dependent choices made for the core on issues that are optional on the powerpc ? architecture as defined in the powerpc architecture books i, ii, and iii . it also describes features that exist in the architecture, but are not supported by the core. the information in this section is based on the powerpc books, but you can also refer to the powerpc microprocessor family: the programming environment for 32-bit microprocessors (mpcfpe32b/ad) manual for more information. 7.1 p ower pc user instruction set architecture (book i) 7.1.1 computation modes the core is a 32-bit fixed-point implementation of the powerpc architecture. any reference in the powerpc architecture books i, ii, and iii regarding 64-bit implementations are not supported by this core. no floating point of the architecture is implemented. 7.1.2 reserved fields reserved fields in instructions are described under the specific instruction definition sections. unless otherwise stated in the specific instruction description, fields marked i, ii, and iii in the instruction are discarded by the core decoding. thus, this type of invalid form instructions yield results of the defined instructions with the appropriate field zero. in most cases, the reserved fields in registers are ignored on write and return zeros for them on read for any control register implemented by the core. exceptions to this rule are bits 16-23 of the fixed-point exception cause register (xer) and the reserved bits of the machine state register (msr), which are set by the source value on write and return the value last set for it on read. 7.1.3 classes of instructions nonoptional instructions (except floating-point load, store, and compute instructions) are implemented by the hardware. optional instructions are executed by implementation-dependent code and any attempt to execute one of these commands causes the core to take the implementation-dependent software emulation interrupt (offset x01000 of the vector table). illegal and reserved instruction class instructions are supported by implementation-dependent code and, thus the core hardware generates the implementation-dependent software emulation interrupt. how the core treats invalid and preferred instruction forms is described in the specific processor compliance sections.
powerpc architecture compliance 7-2 mpc823e reference manual motorola ppc architecture 7 compliance 7.1.4 exceptions invocation of the system software for any exception caused by an instruction in the core is precise, regardless of the type and setting. 7.1.5 the branch processor 7.1.6 fetching instructions the core fetches a number of instructions into its internal buffer (the instruction prefetch queue) prior to execution. if a program modifies the instructions it intends to execute, it must call a system library program to ensure that the modifications are visible to the instruction fetching mechanism prior to executing the modified instructions. 7.1.7 branch instructions the core implements all the instructions defined for the branch processor by the powerpc user instruction set architecture (book i) in the hardware. for details about the performance of various instructions, see table 8-1 of this manual. 7.1.7.1 invalid branch instruction forms. bits marked with z in the bo encoding definition are discarded by the core decoding. thus, these types of invalid form instructions yield results of the defined instructions with the z bit zero. if the decrement and test ctr option is specified for the bcctr or bcctrl instructions, the target address of the branch is the new value of the ctr. condition is evaluated correctly, including the value of the counter after decrement. 7.1.7.2 branch prediction. the core uses the y bit to predict path for prefetch. prediction is only done for not-ready branch conditions. no prediction is done for branches to the link or count register if the target address is not ready (see table 6-1 for more details). 7.1.8 the fixed-point processor the core implements the following fixed-point instructions: ? arithmetic instructions ? compare instructions ? trap instructions ? logical instructions ? rotate and shift instructions ? move to/from system register instructions all hardware instructions are defined for the fixed-point processor in the powerpc user instruction set architecture (book i) . for details about the performance of the various instructions, see table 8-1 of this manual.
powerpc architecture compliance motorola mpc823e reference manual 7-3 ppc architecture 7 compliance 7.1.8.1 move to/from system register instructions. move to/from invalid special registers in which spr 0 =1 invokes the privilege instruction error interrupt handler if the processor is in problem state (user mode). for a list of all implemented special registers, refer to section 6.4.1 control registers . 7.1.8.2 fixed-point arithmetic instructions. if you try to perform any of the following divisions using the divw[o][.] instruction 0x80000000 ? -1 ? 0 then, the contents of rt are 0x80000000 and if rc =1, the contents of the bits in the cr field 0 are lt = 1, gt = 0, eq = 0, and so is set to the correct value. in the cmpi , cmp , cmpli , and cmpl instructions, the l bit is applicable for 64-bit implementations. for the mpc823e, if l = 1 the instruction form is invalid. the core ignores this bit and, therefore, the behavior when l = 1 is identical to the valid form instruction with l = 0. 7.1.9 the load/store processor the load/store processor supports all of the 32-bit implementation fixed-point powerpc load/store instructions in the hardware. 7.1.9.1 fixed-point load with update and store with update instructions. for load with update and store with update instructions where ra =0, the ea is written into r0. for load with update instructions where ra = rt, ra is boundedly undefined. 7.1.9.2 fixed-point load and store multiple instructions. for these types of instructions, ea must be a multiple of four. if it is not, the system alignment error handler is invoked. for a lmw instruction (if ra is in the range of registers to be loaded), the instruction completes normally. ra is then loaded from the memory location as follows: ra <- mem(ea+(ra-rt)*4, 4) 7.1.9.3 fixed-point load string instructions. load string instructions behave the same as load multiple instructions, with respect to invalid format in which ra is in the range of registers to be loaded. if ra is in the range, it is updated from memory. note: the instruction form is invalid if ra is in the range of registers to be loaded or if ra = 0. note: the instruction forms are invalid if ra is in the range of registers to be loaded or if ra = 0 (i.e. r0). for lswx only, the instruction form is invalid if rd=ra or rd=rb.
powerpc architecture compliance 7-4 mpc823e reference manual motorola ppc architecture 7 compliance 7.1.9.4 storage synchronization instructions. for these type of instructions, ea must be a multiple of four. if it is not, the system alignment error handler is invoked. 7.1.9.5 optional instructions. no optional instructions are supported. 7.1.9.6 little-endian byte ordering. the load/store unit supports little-endian byte ordering as specified in the powerpc user instruction set architecture (book i) . in little-endian mode, if an attempt is made to execute an individual scalar unaligned transfer, as well as a multiple or string instruction, an alignment interrupt is taken. 7.2 p ower pc virtual environment architecture (book ii) 7.2.1 storage model the mpc823e caches are structured as follows: ? physically addressed split 2k instruction cache and 1k data cache ? two-way set associative managed with lru replacement algorithm ? 16-byte (4 words) line size with one valid bit per line 7.2.1.1 memory coherence. hardware memory coherence is not supported in the mpc823e hardware, but can be performed in the software or by defining storage as cache inhibited. in addition, the mpc823e does not provide any data storage attributes to an external system. 7.2.1.2 atomic update primitives. both the lwarx and stwcx instructions are implemented according to the powerpc architecture requirements. when the storage accessed by the lwarx and stwcx instructions is in the cache-allowed mode, it is assumed that the system works with the single master in this storage region. therefore, if a data cache miss occurs, the access on the internal and external buses does not have a reservation attribute. the mpc823e does not cause the system data storage error handler to be invoked if the storage accessed by the lwarx and stwcx instructions is in the writethrough required mode. also, the mpc823e does not provide support for snooping an external bus activity outside the chip. the provision is made to cancel the reservation inside the mpc823e by using the cr_b and kr_b input pins. data cache has a snoop logic to monitor the internal bus for communication processor module accesses of the address associated with the last lwarx instruction.
powerpc architecture compliance motorola mpc823e reference manual 7-5 ppc architecture 7 compliance 7.2.2 the effect of operand placement on performance the load/store unit hardware supports all of the powerpc load/store instructions. an optimal performance can be obtained for naturally aligned operands. these accesses result in optimal performance for a maximum size of four bytes. unaligned operands are supported in the hardware and are broken into a series of aligned transfers. the effect of operand placement on performance is as stated in the powerpc virtual environment architecture (book ii), except for the case of 8-byte operands. because the mpc823e uses a 32-bit wide data bus, the performance is good rather than optimal . refer to section 6.6.6 executing unaligned instructions for a description of fixed-point unaligned instruction execution and timing and to section 6.6.9 instruction timing for a description of string instruction timing. 7.2.3 the storage control instructions the mpc823e interprets the cache control instructions ( icbi , isync , dcbt , dcbi , dcbf , dcbz , dcbst , eieio , and dcbtst ) as if they pertain only to the mpc823e cache. these instructions do not broadcast. any bus activity caused by these instructions is what happens when an operation is performed on the mpc823e cache. ? instruction cache block invalidate ( icbi )the effective address is translated by the memory management unit and the associative block in the instruction cache is invalidated if hit. ? instruction synchronize ( isync )the isync instruction waits for all previous instructions to complete and then discards any prefetched instructions, thus causing subsequent instructions to be fetched or refetched from memory and executed. ? data cache block touch ( dcbt )the block associated with this instruction is checked for hit in the cache. if it is a miss, the instruction is treated as a regular miss, except that the bus error does not cause an interrupt. if no error occurs, the line is written into the cache. ? data cache block touch for store ( dcbtst )the block associated with this instruction is checked for a hit in the cache. if it is a miss, the instruction is treated as a regular miss, except that bus error does not cause an interrupt. if no error occurs, the cache line is written into the cache. ? data cache block set to zero ( dcbz )this instruction is executed according to how it is defined in the powerpc virtual environment architecture book ii . ? data cache block store ( dcbst )this instruction is executed according to how it is defined in the powerpc virtual environment architecture book ii . ? data cache block invalidate ( dcbi )the effective address is translated by the memory management unit and the associated block in the data cache is invalidated if hit. ? data cache block flush ( dcbf )this instruction is executed according to how it is defined in the powerpc virtual environment architecture book ii . ? enforce in-order execution of i/o ( eieio )when executing an eieio instruction, the load/store unit waits until all previous accesses have terminated before issuing cycles associated with load/store instructions after the eieio instruction.
powerpc architecture compliance 7-6 mpc823e reference manual motorola ppc architecture 7 compliance 7.2.4 timebase a description of the timebase register can be found in section 12 system interface unit and section 5 clocks and power control . 7.3 p ower pc operating environment architecture (book iii) the mpc823e has an internal memory space that includes memory-mapped control registers and memory that is used by various modules on the chip. this memory is part of the main memory as seen by the core but cannot be accessed by any external system master. 7.3.1 the branch processor 7.3.1.1 machine state register. the floating-point exception mode is ignored by the mpc823e. the ip bit initial state after reset is set as programmed by the reset configuration specified in section 12 system interface unit . 7.3.1.2 processor version register. the value of the pvr registers version field is x0050. the value of the revision field is x0000 and it is incremented each time the core is revised so that software distinguishes between the core revisions. 7.3.1.3 branch processors instructions. the core implements all the instructions defined for the branch processor in the powerpc user instruction set architecture book i in the hardware. for the details about the performance of various instructions, see table 8-1 of this manual. 7.3.2 the fixed-point processor 7.3.2.1 unsupported registers. the following registers are not supported by the mpc823e. refer to section 7.3.3 storage model for more details. 7.3.2.2 added registers. for a list of the added special purpose registers, see table 6-9. 7.3.3 storage model page sizes are 4k, 16k, 512k, and 8m and an optional sub-page granularity of 1k for 4k pages in a maximum real memory size of 4g. neither ordinary or direct-store segments are supported. 7.3.3.1 address translation. if address translation is disabled (msr ir =0 for instruction accesses or msr dr =0 for data accesses), the effective address is treated as the real address and is passed directly to the memory subsystem. otherwise, the effective address is translated by using the translation lookaside buffer (tlb) mechanism of the sdr 1 ibat2u dbat1u ibat0l ibat3l dbat2l ear ibat2l dbat1l ibat1u dbat0u dbat3u ibat0u ibat3u dbat2u ibat1l dbat0l dbat3l
powerpc architecture compliance motorola mpc823e reference manual 7-7 ppc architecture 7 compliance memory management unit (mmu). instructions are not fetched from no-execute or guarded storage and data accesses are not executed speculatively to or from the guarded storage. the features of the mmu hardware is as follows: ? 32-entry fully associative instruction tlb ? 32-entry fully associative data tlb ? supports up to 16 virtual address spaces ? supports 16 access protection groups ? supports fast software tablewalk mechanism 7.3.4 reference and change bits no reference bit is supported by the mpc823e. however, the change bit is supported by using the data tlb error interrupt mechanism when writing to an unmodified page. 7.3.5 storage protection two main protection modes are supported by the mpc823e: ? domain manager mode ? powerpc mode for more details, refer to section 11 memory management unit . 7.3.6 storage control instructions 7.3.6.1 data cache block invalidate (dcbi). this instruction is executed according to the definition in powerpc operating environment architecture (book iii) . 7.3.6.2 tlb invalidate entry (tlbie). this instruction is performed as defined by the architecture, except that the 22 most-significant bits of the ea are used for address compare. 7.3.6.3 tlb invalidate all (tlbia). this instruction is performed as defined by the architecture. 7.3.6.4 tlb synchronize (tlbsync). this instruction is implemented like a regular mtspr instruction as it relates to engine synchronization with no further effects. 7.3.7 interrupts 7.3.7.1 classes. all interrupts associated with storage are implemented as precise interrupts by the core, which means that a load/store instruction is not complete until all possible error indications are sampled from the load/store bus. this also implies that a store or nonspeculative load instruction is not issued to the load/store bus until all previous instructions have completed. if a late error occurs, a store cycle (or a nonspeculative load cycle) can be issued and aborted.
powerpc architecture compliance 7-8 mpc823e reference manual motorola ppc architecture 7 compliance 7.3.7.2 processing. in each interrupt handler, when registers srr0 and ssr1 are saved, msr ri can be set to 1. 7.3.7.3 definitions. the following table defines the offset value by interrupt type and the sections that follow describe each interrupt in detail. table 7-1. offset of first instruction by interrupt type offset (hex) interrupt type 00000 reserved 00100 system reset 00200 machine check 00300 data storage 00400 instruction storage 00500 external 00600 alignment 00700 program 00800 floating point unavailable 00900 decrementer 00a00 reserved 00b00 reserved 00c00 system call 00d00 trace 00e00 floating point assist 01000 implementation-dependent software emulation 01100 implementation-dependent instruction tlb miss 01200 implementation-dependent data tlb miss 01300 implementation-dependent instruction tlb error 01400 implementation-dependent data tlb error 01500 - 01bff reserved 01c00 implementation-dependent data breakpoint 01d00 implementation-dependent instruction breakpoint 01e00 implementation-dependent peripheral breakpoint 01f00 implementation-dependent nonmaskable development port
powerpc architecture compliance motorola mpc823e reference manual 7-9 ppc architecture 7 compliance 7.3.7.3.1 system reset interrupt. a system reset interrupt occurs when the irq0 pin is asserted and the following registers are set. execution begins at physical address 0x100 if the hard reset configuration word iip bit is 1. execution begins at physical address 0xfff00100 if the hard reset configuration word iip bit is 0. srr0save/restore register 0 set to the effective address of the next instruction the processor executes if no interrupt conditions are present. srr1save/restore register 1 used to save the machine status prior to exceptions and to restore status when an rfi instruction is executed. 1C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me no change. le bit is copied from the ile. other set to 0. 7.3.7.3.2 machine check interrupt. a machine check interrupt indication is received from the u-bus as a response to the address or data phase. it is usually caused by one of the following conditions: ? the accessed address does not exist ? a data error is detected as defined in powerpc operating environment architecture (book iii) , machine check interrupts are enabled when msr me =1. if msr me = 0 and a machine check interrupt indication is received, the processor enters the checkstop state. the behavior of the core in checkstop state is dependent on the working mode as defined in section 20.4.2.1 debug mode enable vs. debug mode disable . when the processor is in debug mode enable, it enters the debug mode instead of the checkstop state. when in debug mode disable, instruction processing is suspended and cannot be restarted without resetting the core. an indication that can generate an automatic reset in this condition is sent to the system interface unit. refer to the section 12 system interface unit for more details. if the machine check interrupt is enabled (msr me =1) it is taken. if srr1 bit 30 =1, the interrupt is recoverable and the following registers are set. srr0save/restore register 0 set to the effective address of the instruction that caused the interrupt.
powerpc architecture compliance 7-10 mpc823e reference manual motorola ppc architecture 7 compliance srr1save/restore register 1 1 set to 1 for instruction fetch-related errors and 0 for load/store-related errors. 2C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me set to 0. le bit is copied from the ile. other set to 0. when using the load/store bus, the following registers are set: dsisrdata/storage interrupt status register 0C14 set to 0. 15C16 set to bits 29-30 of the instruction if x-form instruction and to 0b00 if d-form. 17 set to bit 25 of the instruction if x-form instruction and to bit 5 if d-form. 18C21 set to bits 21-24 of the instruction if x-form instruction and to bits 1-4 if d-form. 22C31 set to bits 6-15 of the instruction. dardata address register set to the effective address of the data access that caused the interrupt. execution resumes at offset x00200 from the base address indicated by msr ip . 7.3.7.3.3 data storage interrupt. a data storage interrupt is never generated by the hardware. however, the software may branch to this location as a result of either an implementation-specific data tlb error or miss interrupt. 7.3.7.3.4 instruction storage interrupt. an instruction storage interrupt is never generated by the hardware, but the software may branch to this location as a result of an implementation-specific instruction tlb error interrupt. 7.3.7.3.5 alignment interrupt. an alignment interrupt occurs as a result of one of the following conditions: ? the operand of a floating-point load or store is not word aligned. ? the operand of a load/store multiple is not word aligned. ? the operand of a lwarx or stwcx is not word aligned. ? the operand of a load/store individual scalar instruction is not naturally aligned when msr le = 1. ? an attempt to execute a multiple/string instruction is made when msr le = 1.
powerpc architecture compliance motorola mpc823e reference manual 7-11 ppc architecture 7 compliance 7.3.7.3.6 program interrupt. the mpc823e cannot generate a floating-point exception type interrupt. likewise, an illegal instruction type program interrupt is not generated by the core, but an implementation-dependent software emulation interrupt is generated instead. a privileged instruction program interrupt is generated for an on-core valid special-purpose register (spr) field or any spr encoded as an external special register if spr 0 =1 and msr pr =1, as well as if you try to execute privileged instruction occurred when msr pr =1. see table 6-11 for details. 7.3.7.3.7 floating-point unavailable interrupt. the mpc823e cannot generate a floating-point exception type interrupt. an implementation-dependent software emulation interrupt will be taken when you try to execute floating-point instruction, regardless of msr fp . 7.3.7.3.8 trace interrupt. a trace interrupt occurs if msr se = 1 and any instruction except rfi is successfully completed or if msr be = 1 and a branch is completed. notice that the trace interrupt does not occur after an instruction that causes an interrupt. the monitor/debugger software must change the vectors of other possible interrupt addresses to single-step these instructions. if this is unacceptable, other debug features can be used. refer to section 20 development capabilities and interface for more information. the following registers are set on a trace interrupt: srr0save/restore register 0 set to the effective address of the instruction following the executed instruction. srr1save/restore register 1 1C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. execution resumes at offset x00d00 from the base address indicated by msr ip . 7.3.7.3.9 floating-point assist interrupt. the floating-point assist interrupt is not generated by the mpc823e. an implementation-dependent software emulation interrupt will be taken when you try to execute a floating-point instruction.
powerpc architecture compliance 7-12 mpc823e reference manual motorola ppc architecture 7 compliance 7.3.7.3.10 implementation-dependent software emulation interrupt. an implementation-dependent software emulation interrupt occurs as a result of one of the following conditions: ? when executing any unimplemented instruction, including all illegal and unimplemented optional and floating-point instructions. ? when executing a mtspr or mfspr that specifies an on-core unimplemented register, regardless of spr 0 . ? when executing a mtspr or mfspr that specifies an off-core unimplemented register and spr 0 =0 or msr pr =0 (no program interrupt condition). for more information, refer to section 7.3.7.3.6 program interrupt . in addition, the following registers are set: srr0save/restore register 0 set to the effective address of the instruction that caused the interrupt. srr1save/restore register 1 1C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. execution resumes at offset x01000 from the base address indicated by msr ip . 7.3.7.3.11 implementation-specific instruction tlb miss interrupt. this type of interrupt occurs if msr ir =1 and you try to fetch an instruction from a page whose effective page number cannot be translated by tlb. the following registers are set: srr0Csave/restore register 0 set to the effective address of the instruction that caused the interrupt. note: the exception 1000 implementation-dependent software emulation is triggered when an unimplemented opcode is being decoded.
powerpc architecture compliance motorola mpc823e reference manual 7-13 ppc architecture 7 compliance srr1save/restore register 1 0C3 set to 0. 4 set to 1. 10 set to 1. 11C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. some instruction tlb registers are set to the values described in section 11 memory management unit . execution resumes at offset x01100 from the base address indicated by msr ip . 7.3.7.3.12 implementation-specific instruction tlb error interrupt. this type of interrupt occurs as a result of one of the following conditions: ? the effective address cannot be translated. either the segment or page valid bit of this page is cleared in the translation table. ? the fetch access violates storage protection. ? the fetch access is to guarded storage and msr ir =1. the following registers are set: srr0save/restore register 0 set to the effective address of the instruction that caused the interrupt. srr1save/restore register 1 1 set to 1 if the translation of an attempted access is not found in the translation tables. otherwise, set to 0. 2 set to 0. 3 set to 1 if the fetch access was to a guarded storage when msr ir = 1 or when bit 4 is set. otherwise, set to 0. 4 set to 1 if the storage access is not permitted by the protection mechanism; otherwise set to 0. in the first revision when this bit is set, bits 3 and 10 are also set, but in future revisions this bit may be set alone. 10 set to 1 when bit 4 is set. otherwise, set to 0. 11C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri .
powerpc architecture compliance 7-14 mpc823e reference manual motorola ppc architecture 7 compliance msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. some instruction tlb registers are set to a value described in section 11 memory management unit . execution resumes at offset x01300 from the base address indicated by msr ip . 7.3.7.3.13 implementation-specific data tlb miss interrupt. this type of interrupt occurs when msr dr =1 and you try to access a page whose effective page number cannot be translated by tlb. the following registers are set: srr0save/restore register 0 set to the effective address of the instruction that caused the interrupt. srr1save/restore register 1 1C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. some instruction tlb registers are set to the values described in section 11 memory management unit . execution resumes at offset x01200 from the base address indicated by msr ip . 7.3.7.3.14 implementation-specific data tlb error interrupt. this type of interrupt occurs as a result of one of the following conditions: ? no effective address of a load , store , icbi , dcbz , dcbst , dcbf or dcbi instruction can be translated (either the segment or page valid bit of this page is cleared in the translation table). ? the access violates storage protection. ? an attempt was made to write to a page with a negated change bit. the following registers are set: srr0save/restore register 0 set to the effective address of the instruction that caused the interrupt.
powerpc architecture compliance motorola mpc823e reference manual 7-15 ppc architecture 7 compliance srr1save/restore register 1 1C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. dsisrdata/storage interrupt status register 0 set to 0. 1 set to 1 if the translation of an attempted access is not found in the translation tables. otherwise, set to 0. 2C3 set to 0. 4 set to 1 if the storage access is not permitted by the protection mechanism; otherwise set to 0. 5 set to 0. 6 set to 1 for a store operation and to 0 for a load operation. 7C31 set to 0. dardata address register set to the effective address of the data access that caused the interrupt. some instruction tlb registers are set to the values described in section 11 memory management unit . execution resumes at offset x01400 from the base address indicated by msr ip . 7.3.7.3.15 implementation-specific debug register. an implementation-specific debug interrupt occurs as a result of one of the following conditions: ? when there is an internal breakpoint match (for more details, refer to section 20.3 generating watchpoints and breakpoints ). ? when a peripheral breakpoint request is presented to the interrupt mechanism. ? when the development port request is presented to the interrupt mechanism. refer to section 20 development capabilities and interface for details on how to generate the development port request.
powerpc architecture compliance 7-16 mpc823e reference manual motorola ppc architecture 7 compliance the following registers are set: srr0save/restore register 0 for i-breakpoints, set to the effective address of the instruction that caused the interrupt. for l-breakpoint, set to the effective address of the instruction following the instruction that caused the interrupt. for development port maskable request or a peripheral breakpoint, set to the effective address of the instruction that the processor would have executed next if no interrupt conditions were present. if the development port request is asserted at reset, the value of srr0 is undefined. srr1save/restore register 1 1C4 set to 0. 10C15 set to 0. other loaded from bits 16-31 of the msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr ri . if the development port request is asserted at reset, the value of srr1 is undefined. msrmachine state register ip no change. me no change. le bits are copied from the ile. other set to 0. for l-bus breakpoint instances, the following registers are set to: barbreakpoint address register set to the effective address of the data access as computed by the instruction that caused the interrupt. dsisrdata/storage interrupt status register do not change. dardata address register do not change. the execution resumes from an address equal to the base indicated by the msr ip and the following offset. ? x01d00Cfor an instruction breakpoint match ? x01c00Cfor a data breakpoint match ? x01e00Cfor a development port maskable request or a peripheral breakpoint ? x01f00Cfor a development port nonmaskable request
powerpc architecture compliance motorola mpc823e reference manual 7-17 ppc architecture 7 compliance 7.3.7.4 partially executed instructions. in general, the architecture allows instructions to be partially executed when an alignment or data storage interrupt occurs. in the core, instructions are not executed if an alignment interrupt condition is detected or if a data storage interrupt is never generated by the hardware. in the mpc823e, the instruction can be partially executed only in the case of load/store instructions that cause multiple access to the memory subsystemmultiple/string and unaligned load/store instructions. in this instance, the instruction can be partially completed if one of the accesses (except the first one) causes a miss in the data tlb. the implementation-specific data tlb miss interrupt is taken in this case. for the update forms, the update register (ra) is not altered. 7.3.8 timer facilities descriptions of the timebase and decrementer registers can be found in section 12 system interface unit and section 5 clocks and power control . 7.3.9 optional facilities and instructions any other powerpc operating environment architecture (book iii) optional facilities and instructions that are not discussed here are not implemented by the mpc823e hardware. any attempt to execute any of these instructions causes an implementation-dependent software emulation interrupt to occur.
motorola mpc823e reference manual 8-1 instruction execution 8 timing section 8 instruction execution timing this section describes the timing of the instruction cycles in terms of clock cycles, including serialization, latency, and blockage. 8.1 instruction timing list the following table lists the instruction execution timing in terms of latency and blockage of the appropriate execution unit. a serializing instruction has the effect of blocking all execution units. table 8-1. instruction execution timing instructions latency blockage execution unit serializing instruction branch instructions: b, ba, bl, bla, bc, bca, bcl, bcla, bclr, bclrl, bcctr, bcctl taken 2 2 branch unit no not taken 1 1 system call: sc, rfi serialize + 2 serialize + 2 yes cr logical: crand, crxor, cror, crnand, crnor, crandc, creqv, crorc, mcrf 1 1 cr unit no fixed-point trap instructions: twi, tw taken serialize + 3 serialize + 3 alu / bfu after not taken 1 1 no move to special registers: mtspr, mtcrf, mtmsr, mcrxr except mtspr to lr and ctr and external to the core registers serialize + 1 serialize + 1 all yes move to lr, ctr: mtspr 1 1 branch unit no move to external to the core special registers: mtspr, mttb, mttbu serialize + 1 8 serialize + 1 ldst yes move from external to the core special registers: mfspr, mftb, mftbu load latency 1 ldst no move from special registers located internal to the core: mfspr 1 11 see list 2
instruction execution timing 8-2 mpc823e reference manual motorola instruction execution 8 timing move from others: mfcr, mfmsr serialize + 1 serialize + 1 see list 3 fixed-point arithmetic: addi, add[o][.], addis, subf[o][.], addic, subfic, addic., addc[o][.], adde[o][.], subfc[o][.], subfe[o][.], addme[o][.], addze[o][.], subfme[o][.], subfze[o][.], neg[o][.] 1 1 alu / bfu no fixed-point arithmetic (divide instructions): divw[o][.], divwu[o][.] min 2 max 11 4 min 2 max 11 5 imul / idiv no fixed-point arithmetic (multiply instructions): mul, mullw[o][.], mulhw[.], mulhwu[.] 2 1-2 6 imul / idiv no fixed point compare: cmpi, cmp, cmpli, cmpl 1 1 alu / bfu no fixed-point logical: andi., andis., ori, oris, xori, xoris, and[.], or[.], xor[.], nand[.], nor[.], eqv[.], andc[.], orc[.], extsb[.], extsh[.], cntlzw[.] 1 1 alu / bfu no fixed-point rotate and shift: rlwinm[.], rlwnm[.], rlwimi[.], slw[.], srw[.], srawi[.], sraw[.] 1 1 alu / bfu no fixed-point load instructions: lbz, lbzu, lbzx, lbzux, lhz, lhzu, lhzx, lhzux, lha, lhau, lhax, lhaux, lwz, lwzu, lwzx, lwzux, lhbrx, lwbrx. 2 7 1 ldst no fixed-point store instructions: stb, stbu, stbx, stbux, sth, sthu, sthx, sthux, stw, stwu, stwbrx, stwx, stwux, sthbrx 1 8 1 ldst no fixed-point load and store multiple instructions: lmw, smw serialize + 1 + number of registers serialize + 1 + number of registers ldst yes synchronize: sync serialize + 1 serialize + 1 ldst yes storage synchronization instructions: lwarx, stwcx. serialize + 2 serialize + 2 ldst yes move condition register from xer: mcrxr serialize + 1 serialize + 1 ldst yes (before) move to / from special purpose register (debug, dar, dsisr): mtspr, mfspr serialize + 1 serialize + 1 ldst yes (before) string instructions: lswi, lswx, stswi, stswx serialize + 1 + number of words accessed serialize + 1 + number of words accessed ldst yes table 8-1. instruction execution timing (continued) instructions latency blockage execution unit serializing instruction
instruction execution timing motorola mpc823e reference manual 8-3 instruction execution 8 timing storage control instructions: isync serialize serialize branch yes order storage access: eieio 1 1 ldst next load or store is synchronized relative to all prior load or store cache control: icbi 1 1 ldst, i-cache no notes: 1. refer to table 6-11 for details. 2. refer to section 6.4.1 control registers . 3. see table 6-10 for details. 4. where: 5. 6. blocking the multiply instruction is dependent on the subsequent instruction. for any subsequent multiply instruction, the blockage is 1 clock and for any subsequent divide it is 2 clocks. 7. assuming nonspeculative aligned access, on-chip memory, and available bus. for details, refer to section 6.6.5 issuing nonspeculative load instructions , section 6.6.6 executing unaligned instructions , and section 6.6.9 instruction timing . 8. although a store (as well as mtspr for special registers external to the core) issued to the load/store unit buffer frees the core pipeline, the next load or store will not actually be performed on the bus until the bus is free. table 8-1. instruction execution timing (continued) instructions latency blockage execution unit serializing instruction divisionlatency nooverflow 3 t 34 divisorlength C 4 ------------------------------------------------------ ? ?? + overflow 2 t ------------------------------------------------------------------------------------------------------------------------ = overflow x 0 -- - ? ?? or maxnegativenumber 1 C -------------------------------------------------------------- - ? ?? = divisionblockage divisionlatency =
instruction execution timing 8-4 mpc823e reference manual motorola instruction execution 8 timing 8.2 instruction execution timing examples all examples assume an instruction cache hit. 8.2.1 data cache load lwz r12,64 (sp) sub r3,r12,3 addic r4,r14,1 mulli r5,r3,3 addi r4,3(r0) this is an example from a data cache with zero wait states. the sub instruction is dependent on the value loaded by the load to r12. this causes a bubble to occur in the instruction stream as shown in the execute line. refer to section 8.2.2.2 private writeback bus load for instances in which no such dependency exists. figure 8-1. example of a data cache load lwz sub mulli addi addic fetch decode read + execute writeback l address drive l data load write back lwz sub bubble add addic lwz sub sub addic ld ld ld
instruction execution timing motorola mpc823e reference manual 8-5 instruction execution 8 timing 8.2.2 writeback 8.2.2.1 writeback arbitration mulli r12,r4,3 sub r3,r15,3 addic r4,r12,1 the addic instruction is dependent on the mulli result. since the single-cycle instruction sub has priority on the writeback bus over the mulli and the mulli writeback is delayed one clock and causes a bubble in the execute stream. mulli r12,r4,3 sub r3,r15,3 addic r4,r3,1 figure 8-2. example of a writeback arbitration figure 8-3. another example of a writeback arbitration mulli sub addic fetch decode read + execute writeback mulli sub bubble add addic mulli sub, mulli mulli addic sub gclk1 mulli sub addic fetch decode read + execute writeback mulli sub add addic mulli sub, mulli mulli addic sub gclk1
instruction execution timing 8-6 mpc823e reference manual motorola instruction execution 8 timing in this example, the addic instruction is dependent on the sub rather than on the mulli . although the writeback of the mulli is delayed two clocks, there is no bubble in the execution stream. 8.2.2.2 private writeback bus load lwz r12,64 (sp) sub r5,r5,3 cror 4,14,1 and r3,r4.r5 xor r4,r3,r5 or r6,r12.r3 the load and the xor writeback in the same clock since they use the writeback bus in two different ticks. figure 8-4. example of a private writeback bus load ori xor load lwz sub and xor cror ori sub and cror ori load sub lwz lwz lwz lwz lwz sub lwz cror cr and and xor xor ori gclk1 e data fetch decode read + execute writeback l address drive l data cache address load writeback e address
instruction execution timing motorola mpc823e reference manual 8-7 instruction execution 8 timing 8.2.3 fastest external load (data cache miss) lwz r12,64 (sp) sub r3,r12,3 addic r4,r14,1 the sub instruction is dependent on the value read by the load. it causes three bubbles in the instruction execution stream. the external clock is shifted 90 relative to the internal clock. figure 8-5. example of an external load sub lwz lwz sub addic sub sub lwz bubble lwz lwz lwz lwz lwz lwz gclk1 e data fetch decode read + execute writeback l address drive l data cache address load writeback e address bubble bubble bubble
instruction execution timing 8-8 mpc823e reference manual motorola instruction execution 8 timing 8.2.4 a full history buffer lwz r12,64 (sp) sub r5,r5,3 addic r4,r14,1 and r3,r4.r5 xor r4,r3,r5 ori r7,r8,1 this example demonstrates the condition of a full history buffer. in this case, the history buffer is full from executing the sub , add , and and instructions. it takes one more bubble from the load writeback to allow further issue. this is the time for the history buffer to retire sub , add , and and . figure 8-6. example of a full history buffer xor xor lwz lwz sub and xor addic ori sub and addic xor lwz sub lwz lwz lwz lwz lwz sub lwz addic ad and and bubble gclk1 e data fetch decode read + execute writeback l address drive l data cache address load writeback e address bubble
instruction execution timing motorola mpc823e reference manual 8-9 instruction execution 8 timing 8.2.5 branch folding lwz r12,64 (sp) sub r3,r12,3 addic r4,r14,1 bl func ... func: mulli r5,r3,3 addi r4,3(r0) the lwz instruction accesses the internal storage with one wait state. the instruction prefetch queue and parallel operation of the branch unit allows the two bubbles caused by the bl issue and execution to overlap the two bubbles caused by the load. the issue of the branch itself is referred to as a bubble since no actual work is done by a branch. figure 8-7. example of branch folding addic lwz lwz sub bl bubble addic mulli sub sub bubble mulli lwz bubble lwz lwz bl lwz bl sub addic add mulli fetch decode read + execute writeback l address drive l data load writeback branch decode branch execute addi gclk1
instruction execution timing 8-10 mpc823e reference manual motorola instruction execution 8 timing 8.2.6 branch prediction while: mulli r3,r12,r4 addi r4,3(r0) ... lwz r12,64 (r2) cmpi 0,r12,3 addic r6,r5,1 blt cr0,while ... in this example, the blt instruction is dependent on the cmpi instruction. nevertheless, the branch unit predicts the correct path and allows an overlap of its bubbles with those of lwz . when the cmpi writes back, the branch unit reevaluates the decision and if correct prediction occurs no more action is taken and execution continues fluently. the fetched instructions on the predicted path are not allowed to execute before the condition is finally resolved. instead, they are stacked in the instruction prefetch queue. figure 8-8. example of branch prediction addic lwz lwz cmpi blt bubble addic mulli cmpi cmpi bubble mulli lwz bubble lwz lwz blt lwz blt cmp addic add mulli fetch decode read + execute writeback l address drive l data load writeback branch decode branch execute addi branch final decision blt gclk1
motorola mpc823e reference manual 9-1 instruction cache 9 section 9 instruction cache the mpc823e instruction cache is a 16k four-way, set associative storage area. it is organized into 256 sets, four lines per set and four words per line. cache lines are aligned on 4-word boundaries in memory and can be used as an sram that allows the application to lock critical code segments that need fast and deterministic execution time. the cache access cycle begins with an instruction request from the instruction unit in the core. if a cache hit occurs, the instruction is delivered to the instruction unit and if a cache miss occurs, the cache initiates a burst read cycle on the internal bus with the address of the requested instruction. the first word received from the bus is considered the requested instruction. the cache forwards this instruction to the instruction unit of the core as soon as it is received from the internal bus. a cache line is then selected to receive the data that will be coming from the bus. a least recently used (lru) replacement algorithm is used to select a line when no empty lines are available. instruction cache coherency in a multiprocessor environment is maintained by the software and supported by a fast hardware invalidation capability. figure 9-1 illustrates a block diagram view of the cache organization and figure 9-2 illustrates a view of the caches data path. 9.1 features the following is a list of the instruction caches main features: ? 16k four-way, set-associative at four words per line ? implements the lru replacement policy ? parked on the internal bus ? lockable cache lines ? critical word first burst access ? contains stream hit, which allows fetching from the burst buffer and of the word currently on the internal bus ? operates in parallel with the core to maximize performance ? cache control o supports powerpc ? invalidate instruction o supports load and lock (cache line granularity)
instruction cache 9-2 mpc823e reference manual motorola instruction cache 9 ? supports cache inhibit o as a cache mode of operation (cache disable) o on memory regions (supported by the memory management unit) ? efficiently uses the pipeline of the internal bus by initiating a new burst cycle (if a miss is detected) while bringing the tail of the previously missed line to the cache. ? performance enhanced for cache-inhibited regions by fetching a full line to the internal burst buffer. instructions stored in the burst buffer and those originated in a cache-inhibited region are only used once before being refetched. ? instruction unit request has priority over a burst buffer write to an array (burst buffer holds last missed data), thus increasing the overall core performance ? miss latency is reduced by sending addresses to the cache and internal bus simultaneously and aborting when a hit before a cycle goes external ? minimum operational power consumption ? tags and data arrays can be accessed by the core for debugging and testing purposes ? special support is available when the mpc823e processor is in debug mode. refer to section 9.9 debug support for more information.
instruction cache motorola mpc823e reference manual 9-3 instruction cache 9 figure 9-1. instruction cache organization block diagram 28 29 27 21 20 0 word select 20 bidirectional mux 4-> 1 20 128 hit0 hit 128 instruction pointer 8 . . . . . . . . set0 set1 set255 set254 comp l r u a r r a y . . . . 20 comp hit1 to line buffer/ from burst buffer 2 mmu way0 tag0 w0 w1 w2 w3 valid bit lock bit tag1 w0 w1 w2 w3 tag255 w0 w1 w2 w3 tag254 w0 w1 w2 w3 . . . . . . . . . . . . w2 way1 way2 way3 20 comp 20 comp hit2 hit3 128 128 128 19
instruction cache 9-4 mpc823e reference manual motorola instruction cache 9 9.2 programming the instruction cache three special-purpose registers can be used to control the instruction cache with the mfspr and mtspr instructions: ? instruction cache control and status register (ic_cst) ? instruction cache address register (ic_adr) ? instruction cache data port register (read-only) (ic_dat) these registers are privileged and any attempt to access them while the core is in the problem state (msr pr =1) results in a program interrupt. figure 9-2. cache data path block diagram 4 words line buffer instruction internal bus data 16k set address [20:27] 4 address [28:29] cache array decoder 128 32 words burst buffer 128 128 128 stream hit mux 2->1 word select mux 4->1 128 data bypass mux 2->1 32 32 to core
instruction cache motorola mpc823e reference manual 9-5 instruction cache 9 9.2.1 instruction cache control and status register the instruction cache control and status register (ic_cst) is used to configure and access the status of the instruction cache. ieninstruction cache enable status this read-only bit indicates the status of the instruction cache. any attempt to write to it is ignored. you can enable or disable the instruction cache by writing to the cmd field. 0 = instruction cache is disabled. 1 = instruction cache is enabled. bits 1C3reserved these bits are reserved and must be set to 0. cmdcommand the following commands can be written to the cmd field to control and configure the instruction cache. the machine must be in privilege mode (msr pa =1). 000 = reserved. 001 = cache enable . 010 = cache disable . 011 = load & lock . 100 = unlock line . 101 = unlock all . 110 = invalidate all . 111 = reserved. bits 7C9reserved these bits are reserved and must be set to 0. ic_cst bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ien reserved cmd reserved ccer1 ccer2 ccer3 reserved reset 00000000 r/w r r/w r r r spr 560 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w spr 560 note: = undefined.
instruction cache 9-6 mpc823e reference manual motorola instruction cache 9 ccer1instruction cache error type 1 this field is sticky and set by the hardware. it is read-only and cleared when read. 0 = no error. 1 = error. ccer2instruction cache error type 2 this field is sticky and set by the hardware. it is read-only and cleared when read. 0 = no error. 1 = error. ccer3instruction cache error type 3 this field is sticky and set by the hardware. it is read-only and cleared when read. 0 = no error. 1 = error. bits 13C31reserved these bits are reserved and must be set to 0. 9.2.2 instruction cache address register the instruction cache register (ic_adr) contains addresses to be used in the command programmed in the ic_cst. adraddress this field represents the address to be used in the command programmed in the cmd field of the ic_cst. the format may vary depending on the selected cache operation. ic_adr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field adr reset r/w r/w spr 561 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field adr reset r/w r/w spr 561 note: = undefined.
instruction cache motorola mpc823e reference manual 9-7 instruction cache 9 9.2.3 instruction cache data port register the instruction cache data port register (ic_dat) contains data that is received from the instruction cache. datdata this field represents the data received when reading information from the instruction cache. the format may vary depending on the selected cache. 9.3 instruction cache operation on an instruction fetch, bits 20-27 of the instructions address point into the cache to retrieve the tags and data of one set. the tags from all four accessed ways are then compared against bits 0-19 of the instructions address. if a match is found and the matched entry is valid, then it is a cache hit. if none of the tags match or the matched tag is not valid, it is a cache miss. the instruction cache includes one burst buffer that holds the last line received from the bus and one line buffer that holds the last line retrieved from the cache array. if the requested data is found in one of these buffers, it can also be considered a cache hit. refer to figure 9-2 for more information. to minimize power consumption, the instruction cache attempts to make use of data stored in one of its internal buffers. using a special indication from the core, it is possible to make sure that the requested data is in one of the buffers early enough that the cache array is not activated. 9.3.1 instruction cache hit when a cache hit occurs, bits 28-29 of the instruction address are used to select one word from the cache line whose tag matches the instruction pointer. the instruction is then immediately transferred to the instruction unit of the core. ic_dat bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field dat reset r/w r/w spr 562 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dat reset r/w r/w spr 562 note: = undefined.
instruction cache 9-8 mpc823e reference manual motorola instruction cache 9 9.3.2 instruction cache miss when an instruction cache miss occurs, the address of the missed instruction is driven on the internal bus with a 4-word burst transfer read request. a cache line is then selected to receive the data that will be coming from the bus. the selection algorithm gives first priority to invalid lines. if none of the lines in the selected set are invalid, then the least recently used line is selected for replacement. locked lines are never replaced. the transfer begins with the word requested by the instruction unit, followed by the remaining words of the line, then by the word at the beginning of the lines. when the missed instruction is received from the bus, it is immediately delivered to the instruction unit and also written to the burst buffer. as subsequent instructions are received from the bus, they are written into the burst buffer and delivered to the instruction unit either directly from the bus or from the burst buffer. when the line resides in the burst buffer, it is written to the cache array as long as it is not busy with an instruction unit request. if a bus error is encountered on the access to the requested instruction, then a machine check interrupt is taken. if a bus error occurs on any access to other words in the line, then the burst buffer is marked invalid and the line is not written to the array. however, if no bus error is encountered, the burst buffer is marked valid and eventually written to the array. if you receive a cache-inhibit signal, the line is only written to the burst buffer and not to the cache. instructions that are stored in the burst buffer and originate in a cache-inhibited memory region are only used once before they are refetched. refer to section 9.4.6 instruction cache read for more information. 9.3.3 instruction fetch on a predicted path the core allows branch prediction so branches can issue as early as possible. this mechanism allows instruction prefetch to continue while an unresolved branch is being computed and the condition is being evaluated. instructions fetched after unresolved branches are considered fetched on a predicted path. these instructions may be discarded later if it turns out that the machine has followed the wrong path. to minimize power consumption, the mpc823e instruction cache does not initiate a miss sequence in most cases when the instruction is inside a predicted path. the mpc823e instruction cache evaluates fetch requests to see if they are inside a predicted path and if a hit is detected, the requested data is delivered to the core. however, if a cache miss is detected, the miss sequence is usually not initiated until the core finishes branch evaluation. 9.4 instruction cache commands the mpc823e instruction cache supports the powerpc invalidate instruction with some additional commands that help control the cache and debug the information stored in it. the additional commands are implemented using the three special-purpose control registers mentioned previously in section 9.2 programming the instruction cache . most of the commands are executed immediately after the control register is written and unable to generate any errors. therefore, when executing these command, there is no need to check the error status in the ic_cst.
instruction cache motorola mpc823e reference manual 9-9 instruction cache 9 some commands may take some time to generate errors. in the current implementation, load & lock is the only command to which this applies. therefore, when executing these commands, you must insert an isync instruction immediately after the instruction cache command and check the error status in the ic_cst after the isync . the error type bits in the ic_cst are sticky, thus allowing you to perform a series of instruction cache commands before checking the termination status. these bits are set by the hardware and cleared by the software. only commands that are not immediately executed need to be followed by an isync instruction for the hardware to perform them correctly. however, all commands need to be followed by an isync to make sure all instruction fetches that are after the instruction cache commands in the program stream are affected by the instruction cache command. when the instruction cache is executing a command it is busy, so it stops any treatment of core requests. this eventually results in a machine stall. 9.4.1 invalidating the instruction cache the mpc823e implements the powerpc instruction cache block invalidate ( icbi ) instruction if it only pertains to the mpc823e instruction cache. this instruction does not broadcast on the external bus and the mpc823e does not snoop this instruction if it is broadcasted by other masters. this command is not privileged and has no associated error cases. the instruction cache performs this instruction in one clock cycle. to accurately calculate the latency of this instruction, bus latency must be taken into consideration. the invalidate all instruction cache operation is privileged and any attempt to perform it when the core is in the problem state (msr pr =1) results in a program interrupt. when it is invoked and msr pr = 0, all valid lines in the cache, except the lines that are locked, are made invalid. as a result of this command, the lines lru points to an unlocked way or to way 0 if all of the lines are unlocked. this last feature is useful when initializing the instruction cache out of reset. for more information, refer to section 9.8 reset sequence . to invalidate the whole cache, set the invalidate all command in the ic_cst. this command has no associated error cases. the instruction cache performs this instruction in one clock cycle. to accurately calculate the latency of this instruction, bus latency must be taken into consideration.
instruction cache 9-10 mpc823e reference manual motorola instruction cache 9 9.4.2 loading and locking the instruction cache the load & lock command is used to lock critical code segments in the instruction cache. this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr = 1) results in a program interrupt. load & lock is performed on a cache line granularity and after a line is locked, it operates as a regular instruction sram. it is not replaced during misses and it is not affected by invalidation commands. the hardware operation trusts the software to follow the exact steps mentioned in section 9.7 updating code and memory region attributes . to load and lock a line, follow these steps: 1. read the error type bits in the ic_cst to clear them. 2. write the address of the line to be locked to the ic_adr. 3. set the load & lock command in the ic_cst. 4. execute the isync instruction. 5. return to step 2 to load and lock more lines. 6. read the error type bits in the ic_cst to determine if the operation completed properly. after the load & lock command is written to the ic_cst, the cache checks to see if the line containing the byte addressed by the ic_adr is in the cache. if it is a hit, the line is locked and the command terminates with no exception. if it is not, a regular miss sequence is initiated. after the whole line is placed in the cache, the line is locked. you must check the error type bits in the ic_cst to determine if the load & lock operation completed properly. the load & lock command can generate two errors: ? type 1a bus error occurs in one of the cycles that fetched the line. ? type 2there is no place to lock. it is your responsibility to make sure that there is at least one unlocked way in the appropriate set. 9.4.3 unlocking a line the unlock line command is used to unlock previously locked cache lines. this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr = 1) results in a program interrupt. unlock line is performed on a cache line granularity. if the line is found in the cache it is considered a hit, thus it is unlocked and operates as a regular valid cache line. if the line is not found in the cache it is considered a miss, there is no operation and the command terminates without an exception. to unlock a line, follow these steps: 1. write the address of the line to be unlocked into the ic_adr. 2. set the unlock line command in the ic_cst. this command has no error cases that you need to check. the instruction cache performs this instruction in one clock cycle. to accurately calculate the latency of this instruction, bus latency must be taken into consideration.
instruction cache motorola mpc823e reference manual 9-11 instruction cache 9 9.4.4 unlocking the entire instruction cache the unlock all command is used to unlock the entire instruction cache. this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr =1) results in a program interrupt. it is performed on all cache lines. if a line is locked, it is unlocked and operates as a regular valid cache line. if a line is not locked or if it is invalid, no operation occurs. to unlock the whole cache, set the unlock all command in the ic_cst. this command has no associated error cases. the instruction cache performs this instruction in one clock cycle. to accurately calculate the latency of this instruction, bus latency must be taken into consideration. 9.4.5 inhibiting the instruction cache in the mpc823e, there are two ways to inhibit the cacheusing the mmu cache-inhibit attribute or the cache disable mode. to disable the instruction cache, set the cache disable command in the ic_cst. this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr =1) results in a program interrupt. this command has no error cases that you need to check. to enable the instruction cache, set the cache enable command in the ic_cst. this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr =1) results in a program interrupt. this command has no error cases that you need to check. when fetching from cache-inhibited regions the full line is brought to the internal burst buffer. instructions that originate in a cache-inhibited region and are stored in the burst buffer can be sent to the mpc823e core no more than once before being refetched. in the memory management unit, a memory region can be programmed as cache-inhibited. when changing a memory region to be cache inhibited, you must unlock all previously locked lines containing code that originated in this memory region, invalidate all lines containing code that originated in this memory region, and execute an isync instruction. when the mpc823e asserts the frz signal, it indicates that the mpc823e is under debug and all fetches from the cache are treated as if they were from the cache-inhibited memory region. for more information on cache debug support, refer to section 9.9 debug support . note: failure to follow these steps causes code from cache-inhibited regions to be left inside the cache and any reference to these regions will result in a cache hit. if a reference to a cache-inhibited region results in a cache hit, the data is sent to the core from the cache and not from memory.
instruction cache 9-12 mpc823e reference manual motorola instruction cache 9 9.4.6 instruction cache read the mpc823e allows you to read all data stored in the instruction cache, including the content of the tags array. however, this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr =1) results in a program interrupt. to read the data stored in the instruction cache, follow these steps: 1. write the address of the data to be read to the ic_adr. it is also possible to read this register for debugging purposes. 2. read the ic_dat register. so that it can access all parts of the instruction cache, the ic_adr is divided into the fields shown in the following table. bits 0C16reserved these bits are reserved and must be set to 0. tdtag or data select 0 = select tag ram. 1 = select data ram. wayway select 00 = select way 0 of cache array. 01 = select way 1 of cache array. 10 = select way 2 of cache array. 11 = select way 3 of cache array. setset select this field is used to select the set index of the cache array. ic_adr (cache read command format) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset r/w r/w spr 561 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field res ts way set word reserved reset r/w r/w r/w r/w r/w r/w r/w spr 561 note: = undefined.
instruction cache motorola mpc823e reference manual 9-13 instruction cache 9 wordword select this field is used to select a word within a set and way. bits 30C31reserved these bits are reserved and must be set to 0. when read from the data array, the 32 bits of the word selected by the ic_adr is placed in the targeted general-purpose register. when read from the tag array, the 22 bits of the tag and related information that is selected by the ic_adr are all placed in the targeted general-purpose register. the following table provides the bit layout of the instruction cache data register when reading a tag. tagtag select this field contains the upper 22 bits of the address. bits 20-21 and 30-31reserved these bits are reserved and must be set to 0. vvalid entry 0 = entry is not valid. 1 = entry is valid. llock entry 0 = entry is unlocked. 1 = entry is locked. ic_dat (tag read format) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tag reset r/w r/w spr 562 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tag res v l lru res reset r/w r/w r/w r/w r/w r r/w spr 562 note: = undefined.
instruction cache 9-14 mpc823e reference manual motorola instruction cache 9 lruleast-recently used this bit indicates that the entry is aged or least recently used. bit 24when set, way 3 is more recently used than way 2. bit 25when set, way 3 is more recently used than way 1. bit 26when set, way 3 is more recently used than way 0. bit 27when set, way 2 is more recently used than way 1. bit 28when set, way 2 is more recently used than way 0. bit 29when set, way 1 is more recently used than way 0. 9.4.7 instruction cache write instruction cache write is only enabled when the mpc823e is in test mode. 9.5 restrictions zero wait state devices that are placed on the internal bus are considered to be in the cache-inhibited memory region and the hardware correct operation trusts the software to follow the exact steps mentioned in section 9.7 updating code and memory region attributes . it is not recommended that you perform load & lock from zero wait state devices that are placed on the internal bus, especially since it is not guaranteed that the data will be fetched from the instruction cache. in most cases, it is fetched from the device, but found in the instruction cache. 9.6 instruction cache coherency cache coherency in a multiprocessor environment is maintained by the software and supported by the invalidation mechanism as described above. all instruction storage is considered to be coherent, not required, mode. 9.7 updating code and memory region attributes to update the code or change the programming of the memory regions in the chip-select logic, follow these steps: 1. update the code and change the memory region programming in the chip-select logic. 2. execute the sync instruction to ensure that the update/change operation has finished. 3. unlock all locked lines that contain code that was updated. 4. invalidate all lines that contain code that was updated. 5. execute the isync instruction. 9.8 reset sequence to simplify the debug task of the system, the instruction cache is only disabled during hardware reset (ic_cst en = 0). this feature enables you to investigate the exact state of the instruction cache prior to the event that asserts the reset. to ensure proper operation of the instruction cache after reset, the unlock all , invalidate all , and instruction cache enable commands must be executed.
instruction cache motorola mpc823e reference manual 9-15 instruction cache 9 9.9 debug support the mpc823e can be debugged either in debug mode or by a software monitor debugger. in both cases, the core of the mpc823e cpu asserts the internal freeze (frz) signal. when frz is asserted the instruction cache treats all misses as if they were from cache-inhibited regions and, assuming the debug routine is not in the instruction cache, the cache state remains exactly the same. when frz is asserted, hits are still read from the array and the lru bits are updated. therefore, in the simple case of the debug routine it is read from memory like any other miss. however, for performance reasons, it might be preferable to run the debug routine from the cache. follow these steps with little variation: 1. save all four ways of the sets that are needed for the debug routine by reading the tag, lru code bit, valid bit, and lock bit values. 2. unlock the locked ways in the selected sets. 3. use a load & lock command to load and lock the debug routine into the instruction cache ( load & lock operates the same when frz is asserted). 4. run the debug routine. all accesses to it will result in hits. after the debug routine has completed, the old state of the instruction cache can be restored by following these steps: 1. unlock and invalidate all the sets that are used by the debug routine (both ways). 2. use a load & lock command to restore the old sets. 3. unlock the ways that were not previously locked. 4. to restore the old state of the lru, accesses must be made in the second lru way, the third lru way and the mru way. an access in this description is either load & lock or unlock line . 9.9.1 fetching instructions from the development port when the mpc823e is in debug mode, all instructions are fetched from the development port, regardless of the address generated by the mpc823e core. therefore, the instruction cache is practically bypassed when the mpc823e is in debug mode.
motorola mpc823e reference manual 10-1 data cache 10 section 10 data cache the mpc823e data cache is a 8k two-way, set-associative cache. it is organized into 256 sets, two lines per set and four words per line. cache lines are aligned on 4-word boundaries in memory and can be used as an sram that allows the application to lock critical data segments that need a fast and deterministic execution time. two state bits are included in each cache line and implement invalid, modified-valid, and unmodified-valid states of the data cache. cache coherency in a multiprocessor environment is maintained by the software and supported by a fast hardware invalidation capability. the cache is designed for both writeback and writethrough modes of operation and a least recently used (lru) replacement algorithm is used to select a line when no empty lines are available. 10.1 features the following is a list of the data caches main features: ? 8k four-way, set associative, and physically addressed ? single-cycle cache access on hit and 1 clock latency added for miss ? four word line size ? critical word first and four word burst line fill ? implements lru replacement policy ? 32-bit interface to load/store unit ? one-word write buffer ? lockable cache line granularity ? copyback/writethrough operation is programmed per memory management unit page ? coherency is only maintained by the software and no bus snooping is supported ? cache operation is blocked under miss, until the critical word is delivered to the core ? hit under miss operation ? full data cache powerpc ? control operations ? implementation-specific single operation
data cache 10-2 mpc823e reference manual motorola data cache 10 10.2 organization of the data cache the data cache is a 8k two-way, set associative, physically addressed cache that has 16-byte line and a 32-bit data path to and from the load/store unit, which allows for a 4-byte transfer per cycle. figure 10-1. data cache organization comp way0 28 31 27 21 20 0 byte select bidirectional mux 2 -> 1 hit0 hit effective address . . . . . . . . set0 set1 set255 set254 comp tag0 w0 w1 w2 w3 valid bit lock bit tag1 w0 w1 w2 w3 tag255 w0 w1 w2 w3 tag254 w0 w1 w2 w3 . . . . . . . . . . . . l r u a r r a y . . . . . . . . hit1 to/from line buffer/ burst buffer 4 w2 tag0 w0 w1 w2 w3 way1 tag1 w0 w1 w2 w3 tag255 w0 w1 w2 w3 tag254 w0 w1 w2 w3 . . . . . . . . . . . . valid bit lock bit w2 mmu 8 20 20 128 128 20 128 dirty bit dirty bit 19
data cache motorola mpc823e reference manual 10-3 data cache 10 10.3 programming the data cache 10.3.1 powerpc architecture instructions the following powerpc instructions are supported by the data cache. 10.3.1.1 p ower pc user instruction set architecture (book i) the data cache supports the sync instruction through a cache pipe clean indication to the core. figure 10-2. cache data path block diagram 4 words dirty buffer data internal 8k set address [20:27] 4 cache array decoder 128 32 words burst buffer 32 128 stream hit mux 2->1 word select mux 4->1 32 data bypass mux 2->1 32 32 to core bus data
data cache 10-4 mpc823e reference manual motorola data cache 10 10.3.1.2 p ower pc virtual environment architecture (book ii) the data cache supports the following instructions: ? data cache block flush ( dcbf ) ? data cache block store ( dcbst ) ? data cache block touch ( dcbt ) ? data cache block touch for store ( dcbtst ) ? data cache block set to zero ( dcbz ) 10.3.1.3 p ower pc operating environment architecture (book iii). the data cache supports the dcbi (data cache block invalidate) instruction. 10.3.2 implementation-specific operations the mpc823e data cache includes some extended features in addition to those of the powerpc architecture. the following are implementation-specific operations supported by the mpc823e: ? block lock ? block unlock ? invalidate all ? unlock all ? flush cache line ? read tags ? read registers 10.3.3 special registers of the data cache the powerpc special registers are accessed via the mtspr and mfspr instructions. the following registers are used to control the data cache: ? data cache control and status register (dc_cst) ? data cache address register (dc_adr) ? data cache data register (dc_dat) these registers are privileged and any attempt to access them while the core is in the problem state (msr pr =1) results in a program interrupt.
data cache motorola mpc823e reference manual 10-5 data cache 10 10.3.3.1 data cache control and status register. the data cache control and status register (dc_cst) is used to configure and access the status of the data cache. dendata cache enable status this read-only bit indicates the status of the data cache. any attempt to write to it is ignored. you can enable or disable the data cache by writing to the cmd field. 0 = data cache is disabled. 1 = data cache is enabled. dfwtdata cache force writethrough this bit is read-only and any attempt to write to it is ignored. write to the cmd field to set or force writethrough mode. 0 = data cache mode is determined by the memory management unit. 1 = data cache is forced writethrough. leslittle-endian swap this bit is read-only. write to the cmd field to set or clear little-endian swap mode. refer to section 14 endian modes for details about using this bit to achieve the required endian behavior. 0 = address of the data and the instruction caches is the unchanged address from the core. no byte swap is done on the data and instruction caches external accesses. 1 = address munging performed by the core is reversed before accessing the data cache, the instruction cache and storage. byte swap is performed for the instruction and data caches external accesses. this bit is a read-only bit and any attempt to write to it is ignored. dc_cst bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field den dfwt les res cmd reserved ccer1 ccer2 ccer3 reserved reset 0000 0 0 000 0 r/w r r r r/w r/w r/w r r r r/w spr 568 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w spr 568 note: = undefined.
data cache 10-6 mpc823e reference manual motorola data cache 10 bits 3, 8, and 9reserved these bits are reserved and must be set to 0. cmdcommand the following commands can be written to the cmd field to control and configure the data cache. the machine must be in privilege mode (msr pr =1). 0000 = reserved. 0010 = data cache enable . 0100 = data cache disable . 0110 = lock line . 1000 = unlock line . 1010 = unlock all . 1100 = invalidate all . 1110 = flush data cache line . 0001 = set force writethrough mode . 0011 = clear force writethrough mode . 0101 = set little-endian swap mode . 0111 = clear little-endian swap mode . others = reserved. ccer1data cache error type 1 this field is sticky and set by the hardware. it is read-only and cleared when read. 0 = no error. 1 = error. ccer2data cache error type 2 this field is sticky and set by the hardware. it is read-only and cleared when read. 0 = no error. 1 = error. ccer3data cache error type 3 this field is sticky and set by the hardware. it is read-only and cleared when read. 0 = no error. 1 = error. bits 13C31reserved these bits are reserved and must be set to 0.
data cache motorola mpc823e reference manual 10-7 data cache 10 10.3.3.2 data cache address register. the data cache address register (dc_adr) contains the address to be used in the command programmed in the cmd field of the dc_cst. it also may contain the internal address for the read tags and register operation. adraddress this field represents the address to be used in the command programmed in the dc_cst. it is also the internal address used to read tags and registers. 10.3.3.3 reading the cache structures. to read the data stored in the data cache tags or registers, follow these steps: 1. write to the dc_adr. this register can also be read for debugging purposes. 2. read the dc_dat register. dc_adr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field adr reset r/w r/w spr 569 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field adr reset r/w r/w spr 569 note: = undefined.
data cache 10-8 mpc823e reference manual motorola data cache 10 the dc_adr must be configured into the following fields before the internal parts of the data cache are read from the dc_dat register. bits 0C17 and 28C31reserved these bits are reserved and must be set to 0. rtregister or tag selection 0 = select tag operation. 1 = select register operation. wayway selection 0 = select way 0 of the cache array. 1 = select way 1 of the cache array. setset selection this field is used to select the index of the cache array. when rt is set to 1, it specifies the register to be read. the following registers and their encoding are supported: ?0 00copyback data register 0 ?0 01copyback data register 1 ?0 02copyback data register 2 ?0 03copyback data register 3 ?0 04copyback address register when reading from the dc_dat register, the 20 bits of the tag (and related information) that is selected by the dc_adr are placed in the targeted general-purpose register. the dc_adr (cache read command format) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset r/w r/w spr 569 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved rt way set reserved reset r/w r/w r/w r/w r/w r/w spr 569 note: = undefined.
data cache motorola mpc823e reference manual 10-9 data cache 10 following table illustrates the dc_dat registers bit layout when reading a tag. writing to dc_dat is illegal and can result in an undefined data cache state. tagtag selection this field contains the upper 20 bits of the address. bits 20C21 and 26C31reserved these bits are reserved and must be set to 0. vvalid cache line 0 = entry is not valid. 1 = entry is valid. llock entry 0 = cache entry is unlocked. 1 = cache entry is locked. lruleast recently used 0 = this entry is not aged or least-recently used. 1 = this entry is aged or least-recently used. ddirty or clean cache line 0 = this entry has not been modified since it was read from memory. 1 = this entry has been modified since it was read from memory. dc_dat (tag read format) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tag reset r/w r/w spr 570 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tag reserved v l lru d reserved reset r/w r/w r/w r/w r/w r/w r/w r/w spr 570 note: = undefined.
data cache 10-10 mpc823e reference manual motorola data cache 10 10.4 operating the data cache the data cache is a three-state design. two bits are included in each cache line to maintain the lines state information. the status bits keep track of whether or not the line is valid or if it has been modified relative to memory. these modes are invalid, modified-valid, and unmodified-valid. 10.4.1 data cache read there are two possible outcomes of a data cache read: ? read hiton a cache hit, the requested word is immediately transferred to the load/store unit and the lru state of the set is updated. no state transition occurs and the access time is 1 clock (zero wait state). ? read missa line in the cache is selected to hold the data that will be fetched from memory. the selection algorithm gives first priority to invalid lines and if both lines are invalid, the way zero line is selected first. if neither of the two candidate lines in the selected set is invalid, then one of the lines is selected by the lru algorithm for replacement. if the selected line is valid-modified (dirty), then it is kept in a special buffer to be written out (flushed) to memory or a later time. subsequently, the address of the missed entry is sent to the system interface unit with a request to retrieve the cache line. the system interface unit arbitrates for the bus and initiates a 4-word burst transfer read request. the transfer begins with the aligned word containing the missed data, followed by the remaining word in the line, then by the word at the beginning of the line (wraparound). as the missed word is received from the bus, it is delivered (forwarded) directly to the load/store unit. when the line has been fully received, it is written into the cache. the data cache supports further requests as long as they hit in the cache immediately after the arrival of the critical word. after the line with the requested data has been brought from memory, the dirty line kept in the buffer is sent to the system interface unit to be written out (flushed) to memory. if a bus error is detected during the fetch of the missed critical word, a machine check interrupt is generated. if a bus error occurs on any other word in the line transfer, the line is marked invalid. on the other hand, if no bus error is encountered, the cache line is marked unmodified-valid. if a bus error is detected during the dirty line flush, a machine check interrupt is generated (the dirty line ?ush error is an imprecise interrupt). for more information about reading the address and data of a line, see section 10.3.3.3 reading the cache structures . 10.4.2 data cache write the cache operates in either writethrough or copyback mode, depending on how the memory management unit is programmed. if two logical blocks map to the same physical block, it is considered a programming error for them to specify different cache write policies.
data cache motorola mpc823e reference manual 10-11 data cache 10 10.4.2.1 copyback mode in copyback mode, write operations do not necessarily update the external memory. for this reason, copyback mode is the preferred mode of operation when it is necessary to keep bus bandwidth usage and power consumption at a minimum. the possible outcomes of a data cache write in copyback mode are: ? write hit to modified linedata is simply written into the cache with no state transition. the lru of the set is updated to point to the way holding the hit data. ? write hit to unmodified linedata is written into the cache and the line is marked modified. the lru of the set is updated to point to the way holding the hit data. ? write missa line in the cache is selected to hold the data that is fetched from memory. the selection algorithm gives first priority to invalid lines if both lines are invalid the way zero line is selected first. if neither of the two candidate lines in the selected set is invalid, then one of the lines is selected by the lru algorithm for replacement. if the selected line is valid-modified (dirty), it is kept in a special buffer to be written out (flushed) to memory at a later time. subsequently, the address of the missed entry is sent to the system interface unit with a request to retrieve the cache line. the system interface unit arbitrates for the bus and initiates a 4-word burst transfer read request. the transfer begins with the aligned word containing the missed data (the critical word first), followed by the remaining word in the line, then by the word at the beginning of the line (wraparound). as the missed word is received from the bus, it is merged with the data to be written. when the line has been fully received, it is written into the cache. once the line fill is complete, the new store data is written into the cache and the line is marked modified-valid (dirty). at this point, if the machine stalls while waiting for the store to complete, execution is allowed to resume. the data cache does not support further requests until after the whole line arrives. after the line with the requested data has been brought from memory, the dirty line kept in the buffer is sent to the system interface unit to be written out (flushed) to memory. the data cache can support further requests as long as they hit in the cache while flushing the dirty line to memory. if a bus error is detected during a fetch of the missed line (even on a word not accessed by the load/store unit) the cache line is not modified and a machine check interrupt is generated. if a bus error is detected during the dirty line flush, a machine check interrupt is generated (the dirty line ?ush error is an imprecise interrupt). for more information about reading the address and data of a line, see section 10.3.1.2 powerpc virtual environment architecture (book ii) .
data cache 10-12 mpc823e reference manual motorola data cache 10 10.4.2.2 writethrough mode. in writethrough mode, store operations always update memory. this mode is used when external memory and internal cache images must agree. it gives a lower worst-case interrupt latency at the expense of average performance (for example, if it does not have to do flush accesses). the possible outcomes of a data cache write in writethrough mode are: ? write hitdata is written into both the cache and memory, but the cache state is not changed. the lru of the set is updated to point to the way holding the hit data. if a bus error is detected during the write cycle, the cache is still updated and a machine check interrupt is generated. ? write miss data is only written into memory, not to the cache (write no allocate) and no state transition occurs. the lru is not changed, but if a bus error is detected during the write cycle, a machine check interrupt is generated. 10.4.3 data cache inhibited accesses if the cache access is to a page that has the ci bit set in the memory management unit, one of the following outcomes will occur: ? hit to modified or unmodified line this is considered a programming error if the targeted location copy of a load , store , or dcbz instruction to cache inhibit storage is in the cache. the result is boundedly undefined. ? read missdata is read from memory, but not placed in the cache. the caches status is unaffected. ? write miss data is written through to memory, but not placed in the cache. the caches status is unaffected. 10.4.4 data cache freeze the mpc823e can be debugged either in debug mode or by a software monitor debugger. in both cases, the mpc823e core asserts the internal frz signal. for a detailed description of mpc823e debug support, refer to section 20 development capabilities and interface . when frz is asserted, the possible outcomes are: ? read miss data is read from memory, but not placed in the cache. the caches status is unaffected. ? read hit data is read from the cache, but lru is not updated. ? write miss/hit data cache operates in writethrough mode, but lru is not updated. ? dcbz instruction miss/hitdata is written into cache and memory, but lru is not updated. ? dcbst / dcbf / dcbi instructions the data cache and memory is updated according to the powerpc architecture, but lru is not updated.
data cache motorola mpc823e reference manual 10-13 data cache 10 10.4.5 data cache coherency the mpc823e data cache provides no support for snooping external bus activity. all coherency between the internal caches and memory/devices external to the extended core must be controlled by the software. in addition, there is no mechanism provided for dma or other internal masters to access the data cache directly. 10.5 data cache commands 10.5.1 flushing and invalidating the cache the mpc823e allows the data cache to be flushed and invalidated when it is being controlled by the software. the data cache can be invalidated by writing the unlock all and invalidate all commands to the dc_cst. the data cache is not automatically invalidated on reset. it must be invalidated under software control. the data cache can be flushed by a software loop using the dcbst or dcbf instructions or the implementation- specific cache line flush command. notice that the powerpc architecture instructions flush a line indexed by the effective address, while the implementation-specific command indexes a line by its physical set index within the data cache. when flushing must be restricted to a specific memory area or the architecture must be compliant, it is recommended that you use the powerpc architecture instructions. however, if the entire data cache must be flushed and there is no concern for compatibility, the implementation-specific command is more efficient. if a bus error occurs while executing the dcbf and dcbst instructions or the implementation-specific cache line flush command, the data of the cache line specified by these operations must be retrieved from the copyback data registers rather than from the data cache array. 10.5.2 enabling and disabling the cache the data cache can be enabled or disabled by writing the data cache enable and data cache disable commands to the dc_cst. in the disabled state, the cache tag state bits are ignored and all accesses are propagated to the bus as single beat transactions. the default after the reset state of the data cache is disabled. disabling the data cache does not affect the data address translation logic and translation is still controlled by the msr dr bit. any write to the dc_cst must be preceded by a sync instruction. this prevents the data cache from being disabled or enabled in the middle of a data access. when the data cache generates an interrupt as a result of a bus error on the copyback or implementation-specific cache line flush command, it enters the disable state. operation of the cache when it is disabled is similar to cache-inhibit operation. 10.5.3 locking and unlocking the cache each line of the data cache can be independently locked by writing the lock line command to the dc_cst. replacement line fills are not performed to a locked line. a flush or invalidation of a locked line cache is ignored by the data cache. any write to the dc_cst must be preceded by a sync instruction, which prevents a cache from being locked during a line fill. use the unlock line or unlock all commands to unlock the cache.
data cache 10-14 mpc823e reference manual motorola data cache 10 10.5.4 data cache instructions 10.5.4.1 dcbi, dcbst, dcbf and dcbz instructions the dcbz , dcbi , dcbst , and dcbf instructions operate on a block basis of cache line, which is 16 bytes (4 words) long. a data tlb miss exception is generated if the effective address of one of these instructions cannot be translated and data address relocation is enabled. 10.5.4.2 touch. the dcbt and dcbtst instructions of the mpc823e operate on a block basis of cache line, which is 16 bytes (4 words) long. touch instructions initiate bus transfers to bring in a cache line of data from memory. they become no operation instructions if the effective address cannot be translated when the memory management unit is enabled. 10.5.4.3 storage synchronization/reservation. the lwarx and stwcx. instructions are implemented according to the powerpc architecture requirements. when the storage accessed by the lwarx and stwcx. instructions is in the cache allowed mode, it is assumed that the system works with the single master in this storage region. therefore in the case of a data cache miss, the access on the internal and external buses do not have a reservation attribute. the mpc823e does not cause the system data storage error handler to be invoked if the storage accessed by the lwarx and stwcx. instructions is in the write through required mode. the mpc823e does not provide support for snooping an external bus activity outside the chip. the provision is made to cancel the reservation inside the mpc823e by using the cr_b and kr_b input pins. the data cache has a snoop logic to monitor the internal bus for cpm accesses of the address associated with the last lwarx instruction. 10.5.5 data cache read to allow debug and recovery actions, the mpc823e allows you to read the content of the tags array as well as the last copyback address and data buffers. see section 10.3.3 special registers of the data cache for details. this operation is privileged and any attempt to perform it when the core is in the problem state (msr pr =1) results in a program interrupt.
motorola mpc823e reference manual 11-1 memory management 11 unit section 11 memory management unit the mpc823e implements a virtual memory management scheme that provides cache control, storage access protection, and effective-to-real address translation. this implementation includes separate instruction and data memory management units. the mpc823e memory management unit is compliant with the powerpc microprocessor family: the programming environment for 32-bit microprocessors manual in relation to the supported attributes, except that two new modes of operation have been added: ? powerpc ? mode with extended encoding ? domain manager mode available protection granularity sizes are page (4k, 16k, 512k, or 8m) or 1k subpage (1k subpage resolution is supported for 4k pages only). the prefix mx_ that appears before a memory management unit control register name corresponds to instruction and data cache conditions. 11.1 features the following is a list of the memory management units main features: ? 32-entry fully associative data and instruction translation lookaside buffers (tlbs) ? multiple page size support ? high performance ? supports maximum of 16 virtual address spaces ? supports 16 access protection groups ? each entry can be programmed to match problem accesses, privileged accesses, or both ? powerpc msr ir and msr dr controls memory management unit translation and protection ? supports powerpc tlbie and tlbia instructions. no tlbsync instruction is supported, but it is implemented as a nop instruction. ? powerpc mtspr/mfspr instructions to and from the implementation-specific special-purpose registers can be used for programming ? a scratch register is available for software tablewalks ? designed for minimum power consumption
memory management unit 11-2 mpc823e reference manual motorola memory management 11 unit 11.2 address translation the mpc823e core generates 32-bit effective addresses and, when enabled, the memory management unit translates the effective address to a real address that is used for cache or memory access. if disabled, the effective address is passed as the real address to the memory, which bypasses the appropriate translation lookaside buffer. when the memory management unit is enabled, the effective address is used to locate a tlb entry if found or hit, which will then provide the real address mapping and storage attributes. for performance reasons, a translation lookaside buffer is implemented in each hardware cache to hold recently used address translations. in the mpc823e, the table lookup and tlb reload are performed by a software routine with little hardware assistance. this partition simplifies the hardware and gives the system the opportunity to choose the translation table structure. a tlb hit in multiple entries is avoided during the tlb reload phase. the tlb logic recognizes that the effective page number (epn) currently loaded into the translation lookaside buffer overlaps another epn. at least when taking into account the page sizes, subpage validity flags, problem/privileged state, address space id (asid), and the sh values of the tlb entries. when such an event occurs, the current epn is written into the translation lookaside buffer and the entry of the other epn is invalidated from the translation lookaside buffer. the memory management unit supports a multiple virtual address space model and, when enabled, each translation is associated with an asid. in this case, for the translation to be valid, its asid must be equal to the current address space id (casid) that is in effect when an access is performed. 11.2.1 translation lookaside buffer operation two translation lookaside buffers are provided in the mpc823eone for instruction fetches and one for data accesses. the translation lookaside buffer contains pointers to pages in the real memory where data is indexed by the effective page number and it can hold entries with different page sizes. the entry page size controls the number of effective address bits to be compared and the number of least-significant effective address bits that remain untranslated and passes them as least-significant real address bits. for a 4k page size, four subpage validity flags are supported, thus allowing any combination of 1k subpages to be mapped. for any other page size, all of these flags must have the same value. programming pages other than 4k pages with different valid bits is considered a programming error. the subpage validity flags can be manipulated to implement effective page sizes of 1k, 2k, 3k, 4k, or any other combination of 1k subpages. however, subpages of an effective page frame must all map to the same real page. during the translation process, the effective address, the processor problem state (msr pr ), and casid are provided to the translation lookaside buffer. see figure 11-1 for details. in the translation lookaside buffer, the effective address and casid are compared with the epn and asid of each entry. the casid is only compared when the matching entry was programmed as nonshared. see section 11.6.1.6 mmu instruction real page number register and section 11.6.1.7 mmu data real page number register for details.
memory management unit motorola mpc823e reference manual 11-3 memory management 11 unit a successful tlb hit occurs if the incoming effective address matches the epn stored in a valid tlb entry and the casid value stored in the m_casid register matches the entrys asid field. at the same time, the subpage validity flag is set for the subpage pointed to by the incoming effective address. if a hit is detected, the content of the real page number is concatenated with the appropriate number of least-significant bits from the effective address to form the real address that is then sent to the cache and memory system. 11.3 protection access control is assigned on a page-by-page basis and any further manipulation is conducted on a group basis. figure 11-1. block diagram of effective-to-real address translation for 4k pages enabled translation lookaside buffer 32-bit real address byte 12 20 page no access free access exception page protection translation msrpr implementation specific tlb miss interrupts to core implementation specific error interrupts to core logic protection group number 32-bit logical address protection lookup table 20 byte real page number 20 12 32-bit effective address casid (from m_casid) translation enabled 32-entry fully associative array
memory management unit 11-4 mpc823e reference manual motorola memory management 11 unit each tlb entry holds an access protection group (apg) number. when a match is detected, the value of the matched entrys apg is used to index a field in the access protection register that defines access control for the translation. the access protection register contains 16 fields. the field content is used according to the group protection mode. in the powerpc mode, each field holds the kp and ks bits of a corresponding segment register. to be consistent with the powerpc microprocessor family: the programming environment for 32-bit microprocessors manual, the apg value must match the four most-significant bits of the effective page number. in domain manager mode, each field holds override information over the page protection setting. no override, no access override, and free access override modes are all supported. 11.4 storage control the memory management unit can be used to map a block of memory in different access modes. each page can have different storage control attributes. the mpc823e supports cache inhibit, writethrough, and guarded attributes, but not the memory coherence attribute. a page that needs to be memory coherent must be programmed cache-inhibited. refer to the definition of these attributes in the powerpc microprocessor family: the programming environment for 32-bit microprocessors manual. the effects of the cache-inhibit and writethrough attributes in the mpc823e are described in section 9 instruction cache . the guarded attribute is used to map i/o devices that are sensitive to speculative accesses. an attempt to access a page marked guarded with the guarded bit asserted forces the access to stall until the access is nonspeculative or canceled by the core. fetching from a guarded storage is prohibited and if it is attempted an implementation-specific instruction storage interrupt is generated. when msr ir or msr dr for instruction or data address translation are negated, default attributes are used. see section 11.6.1.1 mmu instruction control register and section 11.6.1.2 mmu data control register for details. the mpc823e does not generate an exception for a reference bit update because there is no entry for a reference bit in the translation lookaside buffer. the change bit updates are implemented by the software, but the hardware treats the change bit as a write-protect attribute. therefore, if you try to write to a page marked unmodified, that entry is invalidated and an implementation-specific data tlb error interrupt is generated.
memory management unit motorola mpc823e reference manual 11-5 memory management 11 unit 11.5 translation table structure the mpc823e memory management unit includes special hardware to assist in a two-level software tablewalk. other table structures are not precluded. figure 11-2 and figure 11-3 illustrate the two levels of translation table structures supported by mpc823e special hardware. when md_ctr twam = 1, the tablewalk begins at the level one base address in the m_twb register. the level one table is indexed by the ten most-significant bits of the effective address to get the level one page descriptor. for 8m pages, there must be two identical entries in the level one table for either bit 9 =0 or bit 9 =1. see table 11-2 for more information. the level two base address from the level one descriptor is indexed by the next ten least-significant bits to find the level two page descriptor. for pages larger than 4k, the entry in the level two table must be duplicated according to the page size. see table 11-3 for more information. during address translation by the memory management unit, the most-significant bits of the missed effective address are replaced by the real page address bits from the level two page descriptor. the number of replaced bits depends on the page size. the rest of the real address bits are taken directly from the effective address. when md_ctr twam = 0, the tablewalk begins at the level one base address placed in the m_twb register. the level one table is indexed by the 12 most-significant bits of the effective address to get the level one page descriptor. for 8m pages, there must be eight identical entries in the level one table for bits 9-11 of the effective address. the level two base address from the level one descriptor is indexed by the next ten least-significant bits to find the level two page descriptor. for pages larger than 1k, the entry in the level two table must be duplicated according to the page size.
memory management unit 11-6 mpc823e reference manual motorola memory management 11 unit figure 11-2. two level translation table when md_ctr(twam) = 1 level 2 index page offset level one table pointer 0 9 10 19 20 31 level one table base level 1 index 00 019 level one descriptor 0 level one descriptor 1 level one descriptor n level one descriptor 1023 20 10 effective address level one table real address 12 - for 4k 10 level 1 index 20 20 level two table base level 2 index 00 10 14 - for 16k 19 - for 512k 23 - for 8m level two descriptor 0 level two descriptor 1 level two descriptor n level two descriptor 1023 10 level two table 20 real page address page offset 20 - for 4k 18 - for 16k 13 - for 512k 9 - for 8m
memory management unit motorola mpc823e reference manual 11-7 memory management 11 unit figure 11-3. two level translation table when md_ctr(twam) = 0 level 2 index page offset level one table pointer 011122122 31 level one table base level 1 index 00 017 level one descriptor 0 level one descriptor 1 level one descriptor n level one descriptor 4095 18 12 effective address level one table real address 12 - for 4k 10 level 1 index 18 20 level two table base level 2 index 00 12 14 - for 16k 19 - for 512k 23 - for 8m level two descriptor 0 level two descriptor 1 level two descriptor n level two descriptor 1023 10 level two table 20 real page address page offset 20 - for 4k 18 - for 16k 13 - for 512k 9 - for 8m 20 - for 1k 12 - for 1k
memory management unit 11-8 mpc823e reference manual motorola memory management 11 unit during the memory management units address translation, the most-significant bits of the missed effective address are replaced by the real page address bits from the level two page descriptor. the number of replaced bits depends on the page size. the rest of the real address bits are taken directly from the effective address. see table 11-1 for details. table 11-1. number of effective address bits replaced by real address bits page size number of replaced effective address bits 1k 20 4k 20 16k 18 512k 13 8m 9 table 11-2. number of identical entries required in the level one table page size md_ctr twam = 0 md_ctr twam = 1 1k 1 4k 1 1 16k 1 1 512k 1 1 8m 8 2 table 11-3. number of identical entries required in the level two table page size md_ctr twam = 0 md_ctr twam = 1 1k 1 4k 4 1 16k 16 4 512k 512 128 8m 1,024 1,024
memory management unit motorola mpc823e reference manual 11-9 memory management 11 unit 11.5.1 level one descriptor the following table describes the hardware-assisted level one descriptor format that minimizes the software tablewalk routine. l2balevel 2 table base address this field contains a pointer to a base address of the level 2 table. bits 18 and 19 are only used when md_ctr twam = 1. otherwise, they must be set to 0. bits 20C22reserved these bits are reserved and must be set to 0. apgaccess protection group this field contains access protection for the entire memory segment associated with this entry of the table. gguarded storage attribute for entry 0 = unguarded storage. 1 = guarded storage. pspage size level one 00 = small (4k or 16k). 01 = 512k. 11 = 8m. 10 = reserved. wtwritethrough attribute for entry 0 = copyback cache policy region (default). 1 = writethrough cache policy region. level one descriptor format bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field l2ba reset r/w r/w addr system memory xxxxx0000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field l2ba reserved apg g ps wt v reset r/w r/w r/w r/w r/w r/w r/w r/w addr system memory xxxxx002 note: = undefined. the default values depend on the state of system memory.
memory management unit 11-10 mpc823e reference manual motorola memory management 11 unit vvalid 0 = segment is not valid. 1 = segment is valid. 11.5.2 level two descriptor the following table describes the hardware-assisted level two descriptor format that minimizes the software tablewalk routine. rpnreal page number this field contains the physical address of the page mapped in by this entry. pp1protection for the first 1k subpage in a 4k page this field contains protection code for the first subpage in a 4k page. depending on bit 22 of the pp2 field, the same protection code has different protection schemes. level two descriptor format bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rpn reset r/w r/w addr system memory bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rpn pp1 pp2 pp3 pp4 lps sh ci v reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr system memory note: = undefined. the default values depend on the state of system memory. 4k pages with 1k resolution protection pp1 setting instruction pages data pages privileged mode problem mode privileged mode problem mode 00 no access no access no access no access 01 executable no access read/write no access 10 executable executable read/write read-only 11 executable executable read/write read/write
memory management unit motorola mpc823e reference manual 11-11 memory management 11 unit pp2protection for a second 1k subpage in a 4k page this field contains a protection code for the second subpage in a 4k page. depending on the encoding mode, this field has different meanings. pages over 4k with 4k resolution protection (extended encoding) pp1 setting instruction pages data pages privileged mode problem mode privileged mode problem mode 00 no access no access no access no access 01 executable no access read-only no access 10 reserved reserved reserved reserved 11 reserved reserved reserved reserved pages over 4k with 4k resolution protection (powerpc encoding) pp1 setting instruction pages data pages privileged mode problem mode privileged mode problem mode 00 executable executable read-only read-only 01 executable no access read-only no access 10 executable executable read/write read-only 11 executable executable read/write read/write 4k pages with 1k resolution protection pp2 setting instruction pages data pages privileged mode problem mode privileged mode problem mode 00 no access no access no access no access 01 executable no access read/write no access 10 executable executable read/write read-only 11 executable executable read/write read/write
memory management unit 11-12 mpc823e reference manual motorola memory management 11 unit pp3protection for the third 1k subpage in a 4k page this field contains protection code for the third subpage in a 4k page. depending on the encoding mode, this field has different meanings. pp2 setting pages over 4k with 4k resolution protection 0x pp1 contains powerpc encoding 1x pp1 contains extended encoding x1 page is writable x0 page is write-protected 4k pages with 1k resolution protection pp3 setting instruction pages data pages privileged mode problem mode privileged mode problem mode 00 no access no access no access no access 01 executable no access read/write no access 10 executable executable read/write read-only 11 executable executable read/write read/write pages over 4k with 4k resolution protection pp3 setting case: mx_ctr (ppcs) = 0 0x first subpage not valid 1x first subpage valid x0 second subpage not valid x1 second subpage valid
memory management unit motorola mpc823e reference manual 11-13 memory management 11 unit pp4protection for the fourth 1k subpage in a 4k page this field contains protection code for the fourth subpage in a 4k page. depending on the encoding mode, this field has different meanings. pages over 4k with 4k resolution protection pp3 setting case: mx_ctr (ppcs) = 1 00 no hit for any state 01 hit only for problem accesses 10 hit only for privilege accesses 11 hit for both problem and privilege accesses 4k pages with 1k resolution protection pp4 setting instruction pages data pages privileged mode problem mode privileged mode problem mode 00 no access no access no access no access 01 executable no access read/write no access 10 executable executable read/write read-only 11 executable executable read/write read/write pages over 4k with 4k resolution protection pp4 setting case: mx_ctr (ppcs) = 0 0x third subpage not valid 1x third subpage valid x0 fourth subpage not valid x1 fourth subpage valid
memory management unit 11-14 mpc823e reference manual motorola memory management 11 unit lpslarge page size this bit must be set to 0 for 1k resolution protection. 0 = 1k or 4k. 1 = 16k. shshared page 0 = this entry matches only if the asid field in the tlb entry matches the value of the m_casid register. 1 = asid comparison is disabled for the entry. cicache inhibit this bit is the cache-inhibit attribute for the entry. setting this bit will inhibit cache fill for accesses to this page. vvalid this is the page valid bit. setting this bit indicates the page is valid or resident in the memory (for demand page memory management). pages over 4k with 4k resolution protection pp4 setting case: mx_ctr (ppcs) = 1 00 must be zero 01 reserved 10 reserved 11 reserved
memory management unit motorola mpc823e reference manual 11-15 memory management 11 unit 11.6 programming the memory management unit the memory management unit implements specific operations using control and status registers, which can be accessed with the powerpc mtspr / mfspr instructions. in addition, the powerpc tlbie and tlbia architecture instructions are supported. the memory management unit registers must be accessed when both msr ir =0 and msr dr =0. no similar restriction exists for the tlbie and tlbia instructions. figure 11-4. organization of the memory management unit registers md_ctr mi_ctr md_ap mi_ap m_casid current address space id md_epn mi_epn md_twc mi_twc md_rpn mi_rpn instruction mmu real address m_twb m_tw md_dcam mi_dcam md_dram0 mi_dram0 md_dram1 mi_dram1 configuration registers: table walk registers: debug registers: data mmu control instruction mmu control data mmu access protection instruction mmu access protection data mmu effective address instruction mmu effective address data mmu table walk control instruction mmu table walk control data mmu real address mmu table walk base mmu table walk scratch data mmu debug cam instruction mmu debug cam data mmu debug ram0 instruction mmu debug ram0 data mmu debug ram1 instruction mmu debug ram1 instruction mmu registers data mmu registers
memory management unit 11-16 mpc823e reference manual motorola memory management 11 unit 11.6.1 control registers 11.6.1.1 mmu instruction control register. the mmu instruction control register (mi_ctr) is a special register that is used to control the operation of the instruction memory management unit. gpmgroup protection mode 0 = powerpc mode. 1 = domain manager mode. ppmpage protection mode 0 = page resolution protection. 1 = 1k resolution protection for a 4k page. cidefci default default value for instruction cache-inhibit attribute when the instruction mmu is disabled (msr ir = 0). bits 3 and 5reserved these bits are reserved and must be set to 0. ignored on write and returns a 0 on read. rsv4ireserve four instruction tlb entries 0 = itlb_indx decremented modulo 32. 1 = itlb_indx decremented modulo 28. ppcsprivilege/problem state compare mode 0 = ignore problem/privilege state during address compare. 1 = consider problem/privilege state according to mi_rpn[24:27]. bits 7C18reserved these bits are reserved and must be set to 0. ignored on write and returns a 0 on read. mi_ctr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field gpm ppm cidef res rsv2i res ppcs reserved reset 0000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 784 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved itlb_indx reserved reset 00 0 r/w r/w r/w r/w addr spr 784
memory management unit motorola mpc823e reference manual 11-17 memory management 11 unit itlb_indxinstruction tlb index this field acts as a pointer to the instruction tlb entry to be loaded. it is automatically decremented at every instruction translation lookaside buffer update. bits 24C31reserved these bits are reserved and must be set to 0. ignored on write and returns a 0 on read. 11.6.1.2 mmu data control register. the mmu data control register (md_ctr) is a special register that is used to control the operation of the data memory management unit.gpmgroup protection mode 0 = powerpc mode. 1 = domain manager mode. ppmpage protection mode 0 = page resolution protection. 1 = 1k resolution protection for a 4k page. cidefci default this bit is the data cache attributes default value when the data mmu is disabled (msr dr = 0). wtdefwt default this bit is the data cache attributes default value when the data mmu is disabled (msr dr = 0). rsv4dreserve four data tlb entries 0 = dtlb_indx decremented modulo 32. 1 = dtlb_indx decremented modulo 28. md_ctr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field gpm ppm cidef wtdef rsv2d twam ppcs reserved reset 0000000 0 r/w r/w r/wr r/w r/w r/w r/w r/w r/w addr spr 792 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved dtlb_indx reserved reset 00 0 r/w r/w r/w r/w addr spr 792
memory management unit 11-18 mpc823e reference manual motorola memory management 11 unit twamtablewalk assist mode 0 = 1k subpage hardware assist. 1 = 4k page hardware assist. ppcsprivilege/problem state compare mode 0 = ignore problem/privilege state during address compare. 1 = consider problem/privilege state according to md_rpn[24:27]. bits 7C18reserved these bits are reserved and must be set to 0. ignored on write and returns a 0 on read. dtlb_indxdata tlb index this field acts as a pointer to the data tlb entry to be loaded. it is automatically decremented at every data translation lookaside buffer update. bits 24C31reserved these bits are reserved and must be set to 0. ignored on write and returns a 0 on read. 11.6.1.3 mmu current address space id register. the mmu current address space id (m_casid) register is used to compare the current effective address with the asid field in the tlb entry when searching for a matching entry. bits 0C27reserved these bits are reserved and must be set to 0. ignored on a write. casidcurrent address space id this field is compared to the asid field of a tlb entry to qualify a match. m_casid bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset r/w r addr spr 793 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved casid reset r/w r r/w addr spr 793 note: = undefined.
memory management unit motorola mpc823e reference manual 11-19 memory management 11 unit 11.6.1.4 mmu instruction effective page number register. the mmu instruction effective page number (mi_epn) register contains the effective address to be loaded into a tlb entry. epneffective page number for the tlb entry this field is the effective address default value of the last instruction tlb miss. bits 20C21 and 23C27reserved these bits are reserved and must be set to 0. ignores on write and returns a 0 on read. evtlb entry valid bit this bit is set to 1 on every instruction tlb miss. 0 = the tlb entry is invalid. 1 = the tlb entry is valid. asidaddress space id this field represent the address space id of the instruction tlb entry to be compared with the casid field of the m_casid register. mi_epn bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field epn reset 0 r/w r/w addr spr 787 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field epn reserved ev reserved asid reset 0 0 0 r/w r/w r r/w r r/w addr spr 787 note: = undefined.
memory management unit 11-20 mpc823e reference manual motorola memory management 11 unit 11.6.1.5 mmu data effective page number register. the mmu data effective page number (md_epn) register contains the effective address to be loaded into a tlb entry. epneffective page number for entry the default value is the effective address of the last data tlb miss. evtlb entry valid this bit is set to 1 on a data tlb miss. 0 = the data tlb entry is invalid. 1 = the data tlb entry is valid. bits 20-21 and 23C27reserved these bits are reserved and must be set to 0. ignores on write and returns a 0 on read. asidaddress space id this field is the address space ids of the tlb entry to be compared with the casid field of the m_casid register. md_epn bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field epn reset r/w r/w addr spr 795 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field epn res ev reserved asid reset 0 r/w r/w r/w r/w r/w r/w addr spr 795 note: = undefined.
memory management unit motorola mpc823e reference manual 11-21 memory management 11 unit 11.6.1.6 mmu instruction real page number register. the mmu instruction real page number (mi_rpn) register contains the physical address and the storage attributes of an entry to be loaded into a translation lookaside buffer. this register must be written after the mi_epn and mi_twc registers are written. rpnreal page number these bits are the most-significant bits of the pages physical address. pp1protection for the first 1k subpage in a 4k page this field contains protection code for the first subpage in a 4k page. depending on bit 22 of the pp2 field, the same protection code has different protection schemes. mi_rpn bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rpn reset r/w r/w addr spr 790 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rpn pp1 pp2 pp3 pp4 lps sh ci v reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 790 note: = undefined. the default values depend on the state of system memory. 4k pages with 1k resolution protection pp1 setting instruction pages privileged mode problem mode 00 no access no access 01 executable no access 10 executable executable 11 executable executable
memory management unit 11-22 mpc823e reference manual motorola memory management 11 unit pp2protection for a second 1k subpage in a 4k page this field contains a protection code for the second subpage in a 4k page. depending on the encoding mode, this field has different meanings. pages over 4k with 4k resolution protection (extended encoding) pp1 setting instruction pages privileged mode problem mode 00 no access no access 01 executable no access 10 reserved reserved 11 reserved reserved pages over 4k with 4k resolution protection (powerpc encoding) pp1 setting instruction pages privileged mode problem mode 00 executable executable 01 executable no access 10 executable executable 11 executable executable 4k pages with 1k resolution protection pp2 setting instruction pages privileged mode problem mode 00 no access no access 01 executable no access 10 executable executable 11 executable executable
memory management unit motorola mpc823e reference manual 11-23 memory management 11 unit pp3protection for the third 1k subpage in a 4k page this field contains protection code for the third subpage in a 4k page. depending on the encoding mode, this field has different meanings. pp2 setting pages over 4k with 4k resolution protection 0x pp1 contains powerpc encoding 1x pp1 contains extended encoding x1 page is writable x0 page is write-protected 4k pages with 1k resolution protection pp3 setting instruction pages privileged mode problem mode 00 no access no access 01 executable no access 10 executable executable 11 executable executable pages over 4k with 4k resolution protection pp3 setting case: mi_ctr (ppcs) = 0 0x first subpage not valid 1x first subpage valid x0 second subpage not valid x1 second subpage valid
memory management unit 11-24 mpc823e reference manual motorola memory management 11 unit pp4protection for the fourth 1k subpage in a 4k page this field contains protection code for the fourth subpage in a 4k page. depending on the encoding mode, this field has different meanings. pages over 4k with 4k resolution protection pp3 setting case: mi_ctr (ppcs) = 1 00 no hit for any state 01 hit only for problem accesses 10 hit only for privilege accesses 11 hit for both problem and privilege accesses 4k pages with 1k resolution protection pp4 setting instruction pages privileged mode problem mode 00 no access no access 01 executable no access 10 executable executable 11 executable executable pages over 4k with 4k resolution protection pp4 setting case: mi_ctr (ppcs) = 0 0x third subpage not valid 1x third subpage valid x0 fourth subpage not valid x1 fourth subpage valid
memory management unit motorola mpc823e reference manual 11-25 memory management 11 unit lpslarge page size this bit must be set to 0 for 1k resolution protection. 0 = 1k or 4k. 1 = 16k. shshared page 0 = this entry matches only if the asid filed in the tlb entry matches the value of the m_casid register. 1 = asid comparison is disabled for the entry. cicache inhibit this bit is the cache-inhibit attribute for the tlb entry. vvalid this bit indicates that a tlb entry is valid. pages over 4k with 4k resolution protection pp4 setting case: mi_ctr (ppcs) = 1 00 must be zero 01 reserved 10 reserved 11 reserved
memory management unit 11-26 mpc823e reference manual motorola memory management 11 unit 11.6.1.7 mmu data real page number register. the mmu data real page number (md_rpn) register contains the physical address and the storage attributes of an entry to be loaded into a translation lookaside buffer. this register must be written after the md_epn and md_twc registers. rpnreal page number these bits are the most-significant bits of the pages physical address. pp1protection for the first 1k subpage in a 4k page this field contains protection code for the first subpage in a 4k page. depending on bit 22 of the pp2 field, the same protection code has different protection schemes. md_rpn bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rpn reset r/w r/w addr spr 798 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rpn pp1 pp2 pp3 pp4 lps sh ci v reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 798 note: = undefined. the default values depend on the state of system memory. 4k pages with 1k resolution protection pp1 setting data pages privileged mode problem mode 00 no access no access 01 read/write no access 10 read/write read-only 11 read/write read/write
memory management unit motorola mpc823e reference manual 11-27 memory management 11 unit pp2protection for a second 1k subpage in a 4k page this field contains a protection code for the second subpage in a 4k page. depending on the encoding mode, this field has different meanings. pages over 4k with 4k resolution protection (extended encoding) pp1 setting data pages privileged mode problem mode 00 no access no access 01 read-only no access 10 reserved reserved 11 reserved reserved pages over 4k with 4k resolution protection (powerpc encoding) pp1 setting data pages privileged mode problem mode 00 read/write no access 01 read/write read-only 10 read/write read/write 11 read-only read-only 4k pages with 1k resolution protection pp2 setting data pages privileged mode problem mode 00 no access no access 01 read/write no access 10 read/write read-only 11 read/write read/write
memory management unit 11-28 mpc823e reference manual motorola memory management 11 unit pp3protection for the third 1k subpage in a 4k page this field contains protection code for the third subpage in a 4k page. depending on the encoding mode, this field has different meanings. pp2 setting pages over 4k with 4k resolution protection 0x pp1 contains powerpc encoding 1x pp1 contains extended encoding x1 page is writable x0 page is write-protected 4k pages with 1k resolution protection pp3 setting data pages privileged mode problem mode 00 no access no access 01 read/write no access 10 read/write read-only 11 read/write read/write pages over 4k with 4k resolution protection pp3 setting case: md_ctr (ppcs) = 0 0x first subpage not valid 1x first subpage valid x0 second subpage not valid x1 second subpage valid
memory management unit motorola mpc823e reference manual 11-29 memory management 11 unit pp4protection for the fourth 1k subpage in a 4k page this field contains protection code for the fourth subpage in a 4k page. depending on the encoding mode, this field has different meanings. pages over 4k with 4k resolution protection pp3 setting case: md_ctr (ppcs) = 1 00 no hit for any state 01 hit only for problem accesses 10 hit only for privilege accesses 11 hit for both problem and privilege accesses 4k pages with 1k resolution protection pp4 setting data pages privileged mode problem mode 00 no access no access 01 read/write no access 10 read/write read-only 11 read/write read/write pages over 4k with 4k resolution protection pp4 setting case: md_ctr (ppcs) = 0 0x third subpage not valid 1x third subpage valid x0 fourth subpage not valid x1 fourth subpage valid
memory management unit 11-30 mpc823e reference manual motorola memory management 11 unit lpslarge page size this bit must be set to 0 for 1k resolution protection. 0 = 1k or 4k. 1 = 16k. shshared page 0 = this entry matches only if the asid filed in the tlb entry matches the value of the m_casid register. 1 = asid comparison is disabled for a tlb entry. cicache inhibit this bit is the cache-inhibit attribute for a tlb entry. vvalid this bit indicates that a tlb entry is valid. pages over 4k with 4k resolution protection pp4 setting case: md_ctr (ppcs) = 1 00 must be zero 01 reserved 10 reserved 11 reserved
memory management unit motorola mpc823e reference manual 11-31 memory management 11 unit 11.6.1.8 mmu instruction access protection register. the mmu instruction access protection (mi_ap) register contains the access protection group for the instruction memory management unit. gpxgroup protection in domain manager mode, these bits have the following settings. 00 = no access. 01 = client-access permission defined by page protection bits. 10 = reserved. 11 = manager-free access. in powerpc mode, the gpx bits have these settings and are privilege and problem state (ks and kp) in the powerpc microprocessor family: the programming environment for 32-bit microprocessors manual: 00 = all accesses are considered privileged. 01 = access permission defined by page protection bits. 10 = problem and privileged interpretation is swapped. 11 = all accesses are considered problem. mi_ap bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field gp0 gp1 gp2 gp3 gp4 gp5 gp6 gp7 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 786 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gp8 gp9 gp10 gp11 gp12 gp13 gp14 gp15 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 786 note: = undefined.
memory management unit 11-32 mpc823e reference manual motorola memory management 11 unit 11.6.1.9 mmu data access protection register. the mmu data access protection (md_ap) register contains the access protection group for the data memory management unit. gpxgroup protection in domain manager mode, these bits have the following settings. 00 = no access. 01 = client-access permission defined by page protection bits. 10 = reserved. 11 = manager-free access. in powerpc mode, the gpx bits have these settings and are privilege and problem state (ks and kp) in the powerpc microprocessor family: the programming environment for 32-bit microprocessors manual: 00 = all accesses are considered privileged. 01 = access permission defined by page protection bits. 10 = problem and privileged interpretation is swapped. 11 = all accesses are considered problem. md_ap bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field gp0 gp1 gp2 gp3 gp4 gp5 gp6 gp7 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 794 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gp8 gp9 gp10 gp11 gp12 gp13 gp14 gp15 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w addr spr 794 note: = undefined.
memory management unit motorola mpc823e reference manual 11-33 memory management 11 unit 11.6.1.10 mmu instruction tablewalk control register. the mmu instruction tablewalk control (mi_twc) register contains the access protection group and page size of the entry to be loaded into the translation lookaside buffer. bits 0C22 and 30reserved these bits are reserved and must be set to 0. ignores on write and returns a 0 on read. apgaccess protection group a maximum of 16 protection groups are supported. the default value of instruction tlb miss is 0. gguarded storage attribute for entry default value on instruction tlb miss is 0. 0 = unguarded storage. 1 = guarded storage. pspage size level one default value on instruction tlb miss is 00. 00 = small (4k or 16k). 01 = 512k. 11 = 8m. 10 = reserved. mi_twc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r/w addr spr 789 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved apg g ps res v reset 00 r/w r/w r/w r/w r/w r/w r/w addr spr 789 note: = undefined.
memory management unit 11-34 mpc823e reference manual motorola memory management 11 unit ventry valid default value on instruction tlb miss is 1. 0 = entry is not valid. 1 = entry is valid. 11.6.1.11 mmu data tablewalk control register. the mmu data tablewalk control (md_twc) register contains the second level pointer and access protection group of an entry to be loaded into the translation lookaside buffer. l2tbtablewalk level 2 base value these bits are the most-significant bits of the level two pointer. bits 20C22reserved when written, these bits are reserved and must be set to 0. when read, they return md_epn[10:19] when md_ctr twam = 1 and md_epn[12:21] when md_ctr twam = 0. apgaccess protection group when written, this field supports a maximum of 16 protection groups. it is set to 0000 on the data tlb miss. when read, it returns md_epn[10:19] when md_ctr twam = 1 and md_epn[12:21] when md_ctr twam = 0. gguarded when written, this bit of the entry has the following settings and is set to 0 on a data tlb miss: 0 = unguarded storage. 1 = guarded storage. md_twc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field l2tb reset r/w r/w addr spr 797 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field l2tb reserved apg g ps wt v reset r/w r/w r/w r/w r/w r/w r/w r/w addr spr 797 note: = undefined.
memory management unit motorola mpc823e reference manual 11-35 memory management 11 unit when read, this bit returns md_epn[10:19] when md_ctr twam = 1 and md_epn[12:21] when md_ctr twam = 0. pspage size when written, this field has the following settings and is set to 0 on a data tlb miss. when this field is read, it returns a zero. 00 = small (4k or 16k). 01 = 512k. 11 = 8m. 10 = reserved. when read, this field returns md_epn[10:19] when md_ctr twam = 1 and md_epn[12:21] when md_ctr twam = 0. wtwritethrough when written, this bit has the following settings and is set to 1 on a data tlb miss. when this bit is read, it returns a zero. 0 = copyback data cache policy page entry. 1 = writethrough data cache policy page entry. vvalid when written, this bit has the following settings and is set to 1 on a data tlb miss. when this bit is read, it returns a zero. 0 = entry is invalid. 1 = entry is valid.
memory management unit 11-36 mpc823e reference manual motorola memory management 11 unit 11.6.1.12 mmu tablewalk base register. the mmu tablewalk base (m_twb) register contains a pointer to the level one table to be used in hardware-assisted tablewalk mode. l1tbtablewalk level 1 base value these bits are the most-significant bits of the level one pointer. l1indxlevel 1 table index this field is ignored on write. it returns md_epn[0:9] on read when md_ctr twam = 1 and md_epn[2:11] when md_ctr twam = 0. bits 30C31reserved these bits are reserved and must be set to 0. ignores on write and returns a 0 on read. m_twb bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field l1tb reset r/w r/w addr spr 796 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field l1tb l1indx reserved reset 0 r/w r/w r/w r/w addr spr 796 note: = undefined.
memory management unit motorola mpc823e reference manual 11-37 memory management 11 unit 11.6.1.13 mmu tablewalk special register. the mmu tablewalk special (m_tw) register is used as a scratch register in the software tablewalk interrupt handler. 11.6.2 mmu data content-addressable registers the md_cam, md_ram0, and md_ram1 registers are interface registers that allow you to read the data memory management unit cam and ram entries. if you try to write to the md_cam register using the mtspr instruction, the cam and ram values of the entry indexed by the dtlb_indx field to md_cam, md_ram0, and md_ram1 will be loaded. the source register in the mtspr instruction can be any register, since its value is not used. the values of the md_cam, md_ram0, and md_ram1 registers can be read using the mfspr instruction. if you try to write to the md_ram0 and md_ram1 registers using the mtspr instruction, it will be considered a nop (no operation) instruction. m_tw bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reset m_tw r/w r/w addr spr 799 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset m_tw r/w r/w addr spr 799 note: = undefined.
memory management unit 11-38 mpc823e reference manual motorola memory management 11 unit 11.6.2.1 mmu data cam entry read register. when the content-addressable memory of the mmu data cam entry read (md_cam) register is read, it contains the effective address and page sizes of an entry indexed by the dtlb_indx field of the md_ctr. this register is only updated when you write a value to it. epneffective page number these bits are the most-significant bits of the pages effective address. spvfsubpage validity flags for bit 20: 0 = subpage 0 (address[20:21] = 00) is not valid. 1 = subpage 0 (address[20:21] = 00) is valid. for bit 21: 0 = subpage 1 (address[20:21] = 01) is not valid. 1 = subpage 1 (address[20:21] = 01) is valid. for bit 22: 0 = subpage 2 (address[20:21] = 10) is not valid. 1 = subpage 2 (address[20:21] = 10) is valid. for bit 23: 0 = subpage 3 (address[20:21] = 11) is not valid. 1 = subpage 3 (address[20:21] = 11) is valid. md_cam bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field epn reset r/w r addr spr 824 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field epn spvf ps sh asid reset r/w rrrrr addr spr 824 note: = undefined.
memory management unit motorola mpc823e reference manual 11-39 memory management 11 unit pspage size 000 = 4k. 001 = 16k. 011 = 512k. 111 = 8m. 010 = reserved. 100 = reserved. 101 = reserved. 110 = reserved. shshared page 0 = this entry matches only if the asid field in the data tlb entry matches the value of the m_casid register. 1 = asid comparison is disabled for the entry. asidaddress space id this field is the address space id of the tlb entry to be compared with the casid field of the m_casid register. 11.6.2.2 mmu data ram entry read register 0. the mmu data ram entry read register 0 (md_ram0) contains the physical page number and page attributes of an entry indexed by the dtlb_indx field of the md_ctr. this register is only updated when you write a value to it. rpnreal page number these bits are the most-significant bits of the pages physical address. md_ram0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rpn reset r/w r addr spr 825 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rpn ps apgi g wt ci reserved reset 0 r/w rrrrrrr addr spr 825 note: = undefined.
memory management unit 11-40 mpc823e reference manual motorola memory management 11 unit pspage size 000 = 4k. 001 = 16k. 011 = 512k. 111 = 8m. 010 = reserved. 100 = reserved. 101 = reserved. 110 = reserved. apgiaccess protection group inverted this field is an inversion of the access protection group in the md_twc register. gguarded 0 = unguarded storage. 1 = guarded storage. wtwritethrough 0 = copyback data cache policy page entry. 1 = writethrough data cache policy page entry. cicache-inhibit when this bit is 0, it is not cache-inhibited. bits 30C31reserved these bits are reserved and must be set to 0.
memory management unit motorola mpc823e reference manual 11-41 memory management 11 unit 11.6.2.3 mmu data ram entry read register 1. the mmu data ram entry read register 1 (md_ram1) contains the protection mode information of the entry indexed by the dtlb_indx field of the md_ctr. this register is only updated when you write a value to it. bits 0C16reserved these bits are reserved and must be set to 0. cchange bit for data entry tlb 0 = unchanged region. write access to this page results in the implementation-specific instruction mmu interrupt invocation. software must take an appropriate action before setting this bit to 1. 1 = changed region. write access is allowed to this page. evfentry valid flag 0 = entry is invalid. 1 = entry is valid. md_ram1 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r addr spr 826 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field res c evf sa sat urp0 uwp0 urp1 uwp1 urp2 uwp2 urp3 uwp3 reset 0 r/w rrr r rrrrrrrrr addr spr 826 note: = undefined.
memory management unit 11-42 mpc823e reference manual motorola memory management 11 unit saprivileged (supervisor) access for bit 19: 0 = subpage 0 (address[20:21]=00) privileged access is not permitted. 1 = subpage 0 (address[20:21]=00) privileged access is permitted. for bit 20: 0 = subpage 1 (address[20:21]=01) privileged access is not permitted. 1 = subpage 1 (address[20:21]=01) privileged access is permitted. for bit 21: 0 = subpage 2 (address[20:21]=10) privileged access is not permitted. 1 = subpage 2 (address[20:21]=10) privileged access is permitted. for bit 22: 0 = subpage 3 (address[20:21]=11) privileged access is not permitted. 1 = subpage 3 (address[20:21]=11) privileged access is permitted. satprivileged (supervisor) access type 0 = privileged access type is read-only. 1 = privileged access type is read/write. urp0problem (user) read permission page 0 0 = subpage 0 (address[20:21]=00) problem read access is not permitted. 1 = subpage 0 (address[20:21]=00) problem read access is permitted. uwp0problem (user) read permission page zero 0 = subpage 0 (address[20:21]=00) problem write access is not permitted. 1 = subpage 0 (address[20:21]=00) problem write access is permitted. urp1problem (user) read permission page 1 0 = subpage 1 (address[20:21]=01) problem read access is not permitted. 1 = subpage 1 (address[20:21]=01) problem read access is permitted. urp2problem (user) read permission page two 0 = subpage 2 (address[20:21]=10) problem read access is not permitted. 1 = subpage 2 (address[20:21]=10) problem read access is permitted. uwp2problem (user) write permission page two 0 = subpage 2 (address[20:21]=10) problem write access is not permitted. 1 = subpage 2 (address[20:21]=10) problem write access is permitted. urp3problem (user) read permission page three 0 = subpage 3 (address[20:21]=11) problem read access is not permitted. 1 = subpage 3 (address[20:21]=11) problem read access is permitted.
memory management unit motorola mpc823e reference manual 11-43 memory management 11 unit uwp3problem (user) write permission page three 0 = subpage 3 (address[20:21]=11) problem write access is not permitted. 1 = subpage 3 (address[20:21]=11) problem write access is permitted. 11.6.3 mmu instruction content-addressable registers the mi_cam, mi_ram0, and mi_ram1 registers are interface registers that allow you to read the data memory management unit cam and ram entries. if you try to write to the mi_cam register using the mtspr instruction, the cam and ram values of the entry indexed by the dtlb_indx field to mi_cam, mi_ram0, and mi_ram1 will be loaded. the source register in the mtspr instruction can be any register, since its value is not used. the values of the mi_cam, mi_ram0, and mi_ram1 registers can be read using the mfspr instruction. if you try to write to the mi_ram0 and mi_ram1 registers using the mtspr instruction, it will be considered a nop (no operation) instruction. 11.6.3.1 mmu instruction cam entry read register. when the content-addressable memory of the mmu instruction cam entry read (mi_cam) register is read, it contains the effective address and page sizes of an entry indexed by the itlb_indx field of the mi_ctr. this register is only updated when you write a value to it. epneffective page number these bits are the most-significant bits of the pages effective address. mi_cam bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field epn reset r/w r addr spr 816 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field epn ps asid sh spv reset r/w r r rrr addr spr 816 note: = undefined.
memory management unit 11-44 mpc823e reference manual motorola memory management 11 unit pspage size 000 = 4k. 001 = 16k. 011 = 512k. 111 = 8m. 010 = reserved. 100 = reserved. 101 = reserved. 110 = reserved. asidaddress space id this field represents the data tlb entry to be compared with the casid field in the m_casid register. shshared page 0 = this entry matches only if the asid field in the data tlb entry matches the value of the m_casid register. 1 = asid comparison is disabled for the entry. spvsubpage validity bit 28: 0 = subpage 0 (address[20:21]=00) is not valid. 1 = subpage 0 (address[20:21]=00) is valid. bit 29: 0 = subpage 1 (address[20:21]=01) is not valid. 1 = subpage 1 (address[20:21]=01) is valid. bit 30: 0 = subpage 2 (address[20:21]=10) is not valid. 1 = subpage 2 (address[20:21]=10) is valid. bit 31: 0 = subpage 3 (address[20:21]=11) is not valid. 1 = subpage 3 (address[20:21]=11) is valid.
memory management unit motorola mpc823e reference manual 11-45 memory management 11 unit 11.6.3.2 mmu instruction ram entry read register 0. the mmu instruction ram entry read register 0 (mi_ram0) contains the physical page number and page attributes of an entry indexed by the itlb_indx field of the mi_ctr. this register is only updated when you write to the mi_cam register. rpnreal page number these bits are the most-significant bits of the pages physical address. ps_bpage size 000 = 4k. 001 = 16k. 011 = 512k. 111 = 8m. 010 = reserved. 100 = reserved. 101 = reserved. 110 = reserved. cicache-inhibit when this bit is 0, it is not cache-inhibited. apgaccess protection group a maximum of 16 protection groups are supported and represented in ones compliment format. mi_ram0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rpn reset r/w r addr spr 817 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rpn ps_b ci apg sfp reset r/w rrrr r addr spr 817 note: = undefined.
memory management unit 11-46 mpc823e reference manual motorola memory management 11 unit sfpprivileged (supervisor) fetch permission bit 28: 0 = subpage 0 (address[20:21]=00) privileged fetch is not permitted. 1 = subpage 0 (address[20:21]=00) privileged fetch is permitted. bit 29: 0 = subpage 1 (address[20:21]=01) privileged fetch is not permitted. 1 = subpage 1 (address[20:21]=01) privileged fetch is permitted. bit 30: 0 = subpage 2 (address[20:21]=10) privileged fetch is not permitted. 1 = subpage 2 (address[20:21]=10) privileged fetch is permitted. bit 31: 0 = subpage 3 (address[20:21]=11) privileged fetch is not permitted. 1 = subpage 3 (address[20:21]=11) privileged fetch is permitted. 11.6.3.3 mmu instruction ram entry read register 1. the mmu instruction ram entry read register 1 (mi_ram1) contains the protection mode information of the entry indexed by the itlb_indx field of the mi_ctr. this register is only updated when you write to the mi_cam register. bits 0C25reserved these bits are reserved and must be set to zero. mi_ram1 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r addr spr 818 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved ufp pv g reset 0 r/w rrrr addr spr 818 note: = undefined.
memory management unit motorola mpc823e reference manual 11-47 memory management 11 unit ufpproblem (user) fetch permission bit 26: 0 = subpage 0 (address[20:21]=00) problem fetch is not permitted. 1 = subpage 0 (address[20:21]=00) problem fetch is permitted. bit 27: 0 = subpage 1 (address[20:21]=01) problem fetch is not permitted. 1 = subpage 1 (address[20:21]=01) problem fetch is permitted. bit 28: 0 = subpage 2 (address[20:21]=10) problem fetch is not permitted. 1 = subpage 2 (address[20:21]=10) problem fetch is permitted. bit 29: 0 = subpage 3 (address[20:21]=11) problem fetch is not permitted. 1 = subpage 3 (address[20:21]=11) problem fetch is permitted. pvpage validity 0 = page is invalid. 1 = page is valid. gguarded 0 = unguarded storage. 1 = guarded storage. 11.7 interrupts 11.7.1 implementation-specific instruction tlb miss the implementation-specific instruction tlb miss interrupt occurs when msr ir =1 and there is an attempt to fetch an instruction from a page whose effective page number cannot be found in the instruction translation lookaside buffer. the software tablewalk code is responsible for loading the translation information of the missed page from the translation table that resides in the memory. refer to section 11.8.1.1 translation reload examples for more information. 11.7.2 implementation-specific data tlb miss the implementation-specific data tlb miss interrupt occurs when msr dr =1 and there is an attempt to access a page whose effective page number cannot be found in the data translation lookaside buffer. the software tablewalk code is responsible for loading the translation information of the missed page from the translation table that resides in the memory. refer to section 11.8.1.1 translation reload examples for more information.
memory management unit 11-48 mpc823e reference manual motorola memory management 11 unit 11.7.3 implementation-specific instruction tlb error the implementation-specific instruction tlb error interrupt occurs under one of the following conditions: ? the effective address cannot be translated. either the segment or page valid bit of this page is cleared in the translation table. ? the fetch access violates storage protection. ? the fetch access is to guarded storage and msr ir =1. the cause of an instruction tlb error interrupt can be found in the save/restore register 1 (srr1). for bit assignments, refer to section 7.3.7.3.12 implementation-specific instruction tlb error interrupt . it is the softwares responsibility to invoke the instruction storage interrupt handler. 11.7.4 implementation-specific data tlb error the implementation-specific data tlb error interrupt occurs under one of the following conditions: ? the effective address of a load , store , icbi , dcbz , dcbst , dcbf , or dcbi instruction cannot be translated. either the segment or page valid bit of this page is cleared in the translation table. ? the access violates storage protection. ? an attempt is made to write to a page with a negated change bit. the data storage interrupt status register indicates the cause of the data tlb error interrupt. for bit assignments refer to section 7.3.7.3.14 implementation-specific data tlb error interrupt . it is the softwares responsibility to invoke the data storage interrupt handler.
memory management unit motorola mpc823e reference manual 11-49 memory management 11 unit 11.8 manipulating the translation lookaside buffer 11.8.1 reloading the translation lookaside buffer the tlb reload (tablewalk) function is performed in the software with optional hardware assistance in the following ways: ? automatically stores the missed effective data or instruction address and default attributes in the mi_epn or md_epn registers, respectively. this value is loaded into the selected entry on a write to mi_rpn or md_rpn for the instruction and data translation lookaside buffer. ? automatically updates the replacement location counter to point to the entry to be replaced. this value is placed in the xtlb_indx field of the mi_ctr and md_ctr. ? generates a level one pointer when a mfspr rx, m_twb is performed by the concatenation of the level one table base and level one index. see figure 11-2 and figure 11-3 for details. ? generates a level two pointer when a mfspr rx, md_twc is performed by the concatenation of the level two table base and level two index. ? performs a write to the tlb entry by loading the tablewalk level two entry value to the mi_rpn or md_rpn register. ? a special register (m_tw) is available for the software tablewalk routine, in addition to the powerpc architectures special registers (sprg0Csprg3). using this register allows for more efficient interrupt handling.
memory management unit 11-50 mpc823e reference manual motorola memory management 11 unit 11.8.1.1 translation reload examples. the following are code examples for generating the real page number using a two-level tree page table structure. the first example is for a data tlb reload and the second is for an instruction tlb reload. notice that the following assumptions are made: ? m_twb holds the base pointer to the first level table. ? both instruction and data address translation is turned off (msr ir =0 and msr dr =0). dtlb_swtw mtspr m_tw, r1 # save r1 mfspr r1, m_twb # load r1 with level one pointer lwz r1, (r1) # load level one page entry mtspr md_twc,r1 # save level two base pointer and # level one attributes mfspr r1, md_twc # load r1 with level two pointer # while taking into account the # page size lwz r1, (r1) # load level two page entry mtspr md_rpn, r1 # write tlb entry mfspr r1, m_tw # restore r1 rfi itlb_swtw mtspr m_tw, r1 # save r1 mfspr r1, srr0 # load r1 with instruction miss # effective address (the same data # may be taken from the mi_epn # register) mtspr md_epn, r1 # save instruction miss effective # address in md_epn mfspr r1, m_twb # load r1 with level one pointer lwz r1, (r1) # load level one page entry mtspr mi_twc,r1 # save level one attributes mtspr md_twc,r1 # save level two base pointer mfspr r1, md_twc # load r1 with level two pointer # while taking into account the # page size lwz r1, (r1) # load level two page entry mtspr mi_rpn, r1 # write tlb entry mfspr r1, m_tw # restore r1 rfi
memory management unit motorola mpc823e reference manual 11-51 memory management 11 unit 11.8.2 controlling the tlb replacement counter the tlb replacement counter can be programmed to only select among the first six entries in each translation lookaside buffer by setting the rsv2i bit in the mi_ctr or the rsv2d bit in the md_ctr. these control bits also affect the tlbia instruction. replacement counters are cleared to zero after execution of the tlbia instruction and the counters decrement after an appropriate tlb reload. 11.8.3 invalidating the translation lookaside buffer the mpc823e implements the tlbie instruction to invalidate the tlb entries. this instruction invalidates tlb entries in the translation lookaside buffer that hits, including the reserved entries. notice that with 4k page size, the 22 most-significant bits of the effective address are used in the comparison because no segment registers are implemented. although, for entries with larger page sizes than 4k, some of the lower bits of the effective page number are ignored. the asid value in the entry is ignored for the purpose of matching an invalidated address, thus multiple entries can be invalidated if they have the same effective address and different asid values. the mpc823e supports the tlbia instruction to invalidate all entries in both translation lookaside buffers. if the rsv2d or rsv2i bit is set for a translation lookaside buffer, the four reserved entries will not be invalidated when tlbia is executed. however, the software can explicitly invalidate one or more of these entries by setting the xtlb_indx field in the md_ctr or mi_ctr, which negates the ev bit in the md_epn or mi_epn register and performs a write to the appropriate md_rpn or mi_rpn register. the translation lookaside buffers are not automatically invalidated on reset, but they are disabled. however, they must be invalidated under program control. 11.8.4 loading the reserved tlb entries to load a single reserved entry in the translation lookaside buffer, follow these steps: 1. disable the translation lookaside buffer by clearing msr ir or msr dr as needed. 2. clear the rsv 4 x bit in the mx_ctr. 3. invalidate the effective address of the reserved page by using the tlbia or tlbie instruction. 4. set the xtlb_indx fields of the mx_ctr to the appropriate value (6 or 7). 5. load the mx_epn register with the effective page number, the asid with the reserved page, and set the ev bit to 1. 6. run software tablewalk code to load the appropriate entry into the translation lookaside buffer. refer to section 11.8.1.1 translation reload examples for examples of this code. 7. if needed, repeat the three previous steps to load other tlb entries. 8. set the rsv 4 x bit in the mx_ctr.
memory management unit 11-52 mpc823e reference manual motorola memory management 11 unit 11.9 requirements for accessing the memory management unit control registers all instruction and data memory management unit control registers must be accessed when instruction and data address translation is turned off. prior to an mtspr md_dbcam receive instruction, an eieio instruction must be placed and executed before you write to the mx_cam register.
motorola mpc823e reference manual 12-1 system interface unit 12 section 12 system interface unit the system interface unit controls system startup, initialization, operation, and protection, as well as the external system bus. the system configuration and protection function controls the overall system and provides various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, powerpc ? decrementer, timebase, and real-time clock. the clock synthesizer generates the clock signals for other modules and external devices that the system interface unit uses. this circuitry generates the system clock from an inexpensive 32khz crystal or an oscillator with a maximum frequency of 5mhz. the system interface unit supports various low-power modes that supply different ranges of power consumption, functionality, and wake-up time. the clock scheme supports low-power modes for applications that use baud rate generators and/or serial ports in standby mode. the main system clock can be changed dynamically, but the baud rate generators and serial ports work with a fixed frequency. for more information on clocks, refer to section 5 clocks and power control . the external bus interface handles the transfer of information between internal buses and the memory or peripherals in the external address space. the mpc823e is designed to allow external bus masters to request and obtain mastership of the system bus. for additional information on bus operation, see section 13 external bus interface . the memory controller module provides a glueless interface to many types of memory devices and peripherals and it supports a maximum of eight memory banks, each with their own device and timing attributes. memory control services are provided to both internal and external masters. the mpc823e supports circuitboard test strategies through a user-accessible test logic that is fully compliant with information in section 21 ieee 1149.1 test access port . note: the mpc823es external address bus is 26 bits wide, while the internal address bus is 32 bits wide. therefore, external accesses are considered internally as 26-bit accesses (a[6:31]) with a[0:5] equal to 0, while internal accesses are full 32-bit accesses.
system interface unit 12-2 mpc823e reference manual motorola system interface unit 12 the pcmcia host adapter module provides all control logic for a pcmcia interface fully compliant with the pcmcia standard, release 2.1+ (pc card -16). it can support one pcmcia socket with a maximum of eight memory or i/o windows. 12.1 features the following is a list of the system interface units main features: ? system configuration and protection ? system interrupt configuration ? system reset monitoring and generation ? clock synthesizer ? power management ? real-time clock ? powerpc decrementer ? timebase ? periodic interrupt timer ? external bus interface control ? eight memory banks supported by the memory controller ? debug support ? pcmcia host adapter module supports eight memory or i/o windows ? ieee 1149.1 test access port 12.2 system configuration and protection the mpc823e incorporates many system functions that normally must be provided in external circuits. it is designed to provide maximum system safeguards against hardware and/or software faults. the following features are provided in the system configuration and protection submodule: ? interrupt configuration allows you to configure the system according to your own requirements. the functions include control of parity checking, show cycle operation, and part and mask number constants. ? bus monitor monitors the ta response time for all bus accesses initiated by the internal masters. a tea signal is asserted if the ta response limit is exceeded. the bus monitor measures time between ts and any termination of the bus cycle, including ta , tea , and retry . note: both the mpc823e and mpc821 have the same pcmcia module except that the mpc823e has only one valid slot (slot b). programming a window to be assigned to slot a may cause an erroneous operation.
system interface unit motorola mpc823e reference manual 12-3 system interface unit 12 ? software watchdog timer asserts a reset or nonmaskable interrupt that is selected by the system protection control register (sypcr) if the software fails to service the software watchdog timer after a certain period of time. after system reset, the software watchdog timer, if enabled, selects a maximum timeout period and asserts a system reset if the timeout is reached. the software watchdog timer can be disabled or its timeout period can be changed in the sypcr. once the sypcr is written, it cannot be written again until a system reset. ? periodic interrupt timer generates periodic interrupts to be used with the real-time operating system or the application software. the periodic interrupt timer is clocked by the pitrtclk clock, thus providing a period from 122 microseconds to 8,000 milliseconds assuming a 32.768khz crystal. the periodic interrupt timer function can be disabled if it is not needed. ? powerpc timebase counter provides a timebase reference for the operating system or application software. this 64-bit timebase counter is defined by the powerpc architecture and has two independent reference registers that generate a maskable interrupt when the programmed value in one of the registers is reached. the associated bit in the timebase status register is set for the reference register that generated the interrupt. the timebase is clocked by the tmbclk clock. ? powerpc decrementer provides a decrementer interrupt and is clocked at the same frequency as the timebase. this 32-bit decrementing counter is defined by the powerpc architecture to be clocked by the tmbclk clock. when it is driven by a 4mhz oscillator the period for the decrementer is 4,295 seconds, which is approximately 71.6 minutes. ? real-time clock provides a time-of-day information to the operating system or application software. it is composed of a 45-bit counter and an alarm register. a maskable interrupt is generated when the counter reaches the value programmed in the alarm (rtcal) register. the real-time clock is clocked by the pitrtclk clock. ? freeze support the system interface unit determines whether the software watchdog timer, periodic interrupt timer, timebase, decrementer, and real-time clock will continue to run in freeze mode.
system interface unit 12-4 mpc823e reference manual motorola system interface unit 12 figure 12-1 illustrates a block diagram of the system configuration and protection logic. figure 12-1. system configuration and protection logic module configuration bus monitor periodic interrupt timer software watchdog timer powerpc decrementer powerpc timebase counter real-time clock clock tea interrupt interrupt or system reset interrupt interrupt interrupt
system interface unit motorola mpc823e reference manual 12-5 system interface unit 12 12.3 interrupt configuration many aspects of mpc823e system configuration are controlled by the siu module configuration register (siumcr). the siumcr primarily controls the external bus arbitration logic, external master support, and pin multiplexing. see section 12.12.1.1 siu module configuration register for more information. 12.3.1 the interrupt structure the system interface unit receives interrupts from internal sources, such as the periodic interrupt timer, real-time clock, communication processor module (cpm), and the external irqx pins. the mpc823e interrupt structure is illustrated in figure 12-2. if it is programmed to generate an interrupt, the software watchdog timer always generates a nonmaskable interrupt (nmi) to the core. the external irq0 pin will generate a nonmaskable interrupt as well. figure 12-2. mpc823e interrupt structure level 2 level 7 level 6 level 5 level 4 level 3 level 1 level 0 nmi irq [0:7] ireq nmi gen powerpc core system interface unit timebase periodic real-time pcmcia cpm / lcd/video software irq0 interrupt controller decrementer decrementer debug debug selector edge det interrupt controller watchdog timer interrupt timer clock
system interface unit 12-6 mpc823e reference manual motorola system interface unit 12 notice that the core takes the system reset interrupt when a nonmaskable interrupt is asserted and the external interrupt when any other interrupt is asserted by the interrupt controller. each one of the external irqx pins has its own dedicated assigned priority level and there are eight additional interrupt priority levels. each one of the system interface unit internal interrupt sources (the interrupt request that is generated by the communication processor modules interrupt controller) can be assigned by the software to any one of those eight interrupt priority levels. thus, a very flexible interrupt scheme is realized. 12.3.2 priority of the interrupt sources the system interface unit has 15 interrupt sources that assert just one interrupt request to the core. there are seven external irqx pins and eight interrupt levels. the priority between all interrupt sources is shown in table 12-1. note: irq0 is a nonmaskable interrupt. it will cause the core to go to the system reset vector. table 12-1. priority of system interface unit interrupt sources number priority level interrupt source description interrupt code 0 highest irq0 00000000 1 level 0 00000100 2 irq1 00001000 3 level 1 00001100 4 irq2 00010000 5 level 2 00010100 6 irq3 00011000 7 level 3 00011100 8 irq4 00100000 9 level 4 00100100 10 irq5 00101000 11 level 5 00101100 12 irq6 00110000 13 level 6 00110100 14 irq7 00111000 15 lowest level 7 00111100 16-31 reserved
system interface unit motorola mpc823e reference manual 12-7 system interface unit 12 12.3.3 programming the interrupt controller the system interface units interrupt controller consists of the sipend, simask, siel and sivec registers. 12.3.3.1 siu interrupt pending register. the 32-bit siu interrupt pending (sipend) register contains bits that individually correspond to an interrupt request. if they are set, the bits associated with internal exceptions indicate that an interrupt service is requested, if they are not masked by the corresponding bit in the simask register. these bits reflect the status of the internal requesting device and they are cleared when the appropriate actions are software-initiated in the device itself. the bits associated with the irqx pins have a different behavior depending on the sensitivity defined for them in the siel register. when an irqx signal is defined as a level interrupt the corresponding bit behaves similar to the bits associated with internal interrupt sources. when an irqx signal is defined as an edge interrupt and if the corresponding bit is set, it indicates that a falling edge was detected on the line. these bits are reset by writing a 1 to them. irqinterrupt request 0C7 when set, this field indicates a pending external irqx interrupt of a corresponding value. see figure 12-2 for more information. 0 = the appropriate interrupt is not pending. 1 = the appropriate interrupt is pending. lvllevel 0C7 when set, this field indicates a pending internal level interrupt of a corresponding value. see figure 12-2 for more information. 0 = the appropriate interrupt is not pending. 1 = the appropriate interrupt is pending. sipend bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field irq0 lvl0 irq1 lvl1 irq2 lvl2 irq3 lvl3 irq4 lvl4 irq5 lvl5 irq6 lvl6 irq7 lv7 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x010 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x012
system interface unit 12-8 mpc823e reference manual motorola system interface unit 12 bits 16C31reserved these bits are reserved and must be set to 0. 12.3.3.2 siu interrupt mask register. the 32-bit read/write siu interrupt mask (simask) register contains bits that individually correspond to the interrupt request bits in the sipend register. when a bit is set, it enables the generation of an interrupt request to the core. simask is updated by the software and cleared at reset. it is the responsibility of the software to determine which of the interrupt sources are enabled at a given time. irmxinterrupt request mask 0C7 these bits determine whether an irqx interrupt service request from an external source is to be automatically generated to the core. independent of the irmx setting, the system interface unit will automatically set the corresponding irqx bit in the sipend register. see figure 12-2 for more information. 0 = disable automatic generation of an interrupt request to the cpu. you can monitor the corresponding irqx bit in the sipend register to implement interrupt polling. 1 = enable automatic generation of an interrupt service request to the cpu, which may then vector to an interrupt service routine. the edx bits in the siel register determine if the corresponding irqx interrupt is falling edge-triggered or low logical level triggered. the wmx field in the siel register determines if the corresponding irqx interrupt will cause the mpc823e to exit low-power mode. simask bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field irm0 lvm0 irm1 lvm1 irm2 lvm2 irm3 lvm3 irm4 lvm4 irm5 lvm5 irm6 lvm6 irm7 lvm7 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x014 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x016 note: irq0 will generate a non-maskable interrupt even if its corresponding irm0 bit is not set.
system interface unit motorola mpc823e reference manual 12-9 system interface unit 12 lvmlevel mask 0C7 when set, these bits enable a levelx interrupt request from an internal source to be generated. the sipend register contains the corresponding lvlx bits. see figure 12-2 for more information. 0 = disable the generation of an irqx bit in the sipend register. 1= enable the generation of an irqx bit in the sipend register. bits 16C31reserved these bits are reserved and must be set to 0. 12.3.3.3 siu interrupt edge/level register. the 32-bit read/write siu interrupt edge/level (siel) register contains pairs of bits that correspond to an external interrupt request. if set, the edx bit specifies when a falling edge in the corresponding irqx signal is an interrupt request. when the edx bit is 0, a low logical level in the irqx signal is an interrupt request. the wmx bit, if set, indicates that a low level detection in the corresponding interrupt request line causes the mpc823e to exit low-power mode. ededge detect 0C7 0 = the bits specify that a low logical level in the irqx signal is detected as an interrupt request. 1 = the bits specify that a falling edge in the corresponding irqx signal is detected as an interrupt request. wmwake-up mask 0C7 0 = not allowed to exit from low-power mode. 1 = allows low-level detection in the corresponding irqx signal to exit or wake up the mpc823e from low-power mode. siel bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ed0 wm0 ed1 wm1 ed2 wm2 ed3 wm3 ed4 wm4 ed5 wm5 ed6 wm6 ed7 wm7 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x018 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x018
system interface unit 12-10 mpc823e reference manual motorola system interface unit 12 bits 16C31reserved these bits are reserved and must be set to 0. 12.3.3.4 siu interrupt vector register. the 32-bit read-only siu interrupt vector (sivec) register contains an 8-bit code that represents the unmasked interrupt source of the highest priority level. the sivec register can be read as either a byte, half, or word. when read as a byte, a branch table can be used in which each entry contains one instruction (branch). when read as a half-word, each entry can contain a full routine of 256 instructions (max). the interrupt code is equal to the interrupt number multiplied by four, which allows indexing into the table. refer to figure 12-3 and table 12-1 for details. intcinterrupt code this field indicates the highest priority pending interrupt. bits 8C31reserved these bits are reserved and must be set to 0. the value equals the interrupt number multiplied by four. see table 12-1 for details. sivec bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field intc reserved reset 00 r/w rr addr (immr & 0xffff0000) + 0x01c bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r addr (immr & 0xffff0000) + 0x01e
system interface unit motorola mpc823e reference manual 12-11 system interface unit 12 12.4 the bus monitor the bus monitor ensures that each bus cycle is terminated within a reasonable period of time. the mpc823e system interface unit provides a bus monitor option that monitors internally generated external bus accesses on the external bus. at the start of the transfer start (ts ) signal, the monitor begins counting and stops when the transfer acknowledge (ta ) or transfer error (tea ) signal is asserted. within the bus cycle, the burst cycle performs three functionsstops the previous count, resets, and restarts a new count until the next transfer acknowledge. the last transfer acknowledge of the burst cycle only stops the counter. when a retry signal is asserted, it has the same effect as the ta or tea signal. if the monitor times out, a tea signal is internally asserted by the bus monitor to terminate the cycle. the programmability of the timeout allows for a variation in system peripheral response time. the timing mechanism is clocked by the system clock divided by eight. the maximum value can be 2,040 system clocks. the bus monitor will always be active when the frz signal is asserted or when a debug mode request is pending, regardless of the state of the bmt bit. figure 12-3. interrupt table handling example note: if the bus monitor is disabled, the transfer error conditions will not assert the tea pin. base b routine1 b routine2 b routine3 b routine4 ? ? base + n base + 4 base + 8 base + c base +10 base 1st instruction of routine1 1st instruction of routine2 1st instruction of routine3 1st instruction of routine4 ? ? base + n base + 400 base + 800 base + c00 base +1000 ? ? ? ? ? ? intr: ? ? ? save state r3 <- @ sivec r4 <-- base of branch table ? ? ? lbz add mtspr bctr rx, r3 (0) # load as byte rx, rx, r4 ctr, rx intr: ? ? ? save state r3 <- @ sivec r4 <-- base of branch table ? ? ? lhz add mtspr bctr rx, r3 (0) # load as byte rx, rx, r4 ctr, rx
system interface unit 12-12 mpc823e reference manual motorola system interface unit 12 12.5 the powerpc decrementer the 32-bit decrementing counter is defined by the powerpc architecture to provide a decrementer interrupt. this binary counter is clocked by the same frequency as the timebase. in the mpc823e, the decrementer is clocked by the tmbclk clock, so you must enable the tbe bit in the tbscr for the decrementer to start. the state of the decrementer is not affected by hreset and sreset and, therefore, must be initialized by the software. the decrementer runs continuously after power-up. it continues counting while hreset and sreset are asserted and it is implemented with the following requirements in mind. the decrementer interrupt is also sent to the power-down wake-up logic, which allows the cpu to be awaken from power-down mode. ? the operation of the timebase and decrementer are coherent, which means the counters are driven by the same fundamental timebase. ? the decrementer is unaffected when read. ? when storing to the decrementer, the value in the decrementer is replaced with the value in the gpr. ? when bit 0 (msb) of the decrementer changes from 0 to 1, an interrupt request is signaled. if multiple decrementer interrupt requests are received before the first one is reported, only one interrupt is reported. ? if the decrementer is altered by the software and the content of bit 0 is changed from 0 to 1, an interrupt request is signaled. a decrementer exception causes a pending decrementer interrupt request in the core. when the decrementer interrupt is taken, the request is automatically cleared. the following chart shows some of the periods available for the decrementer, assuming that a 4mhz oscillator is used. count value timeout count value timeout 0 1 microsecond 999999 1.0 second 9 10. microseconds 9999999 10.0 seconds 99 100. microseconds 99999999 100.0 seconds 999 1.0 millisecond 999999999 1000. seconds 9999 10.0 milliseconds ffffffff(hex) 4295 seconds t dec 32 2 f tmbclk () ---------------------------- - =
system interface unit motorola mpc823e reference manual 12-13 system interface unit 12 12.5.1 decrementer register the 32-bit decrementer (dec) register is a special-purpose register defined by powerpc architecture. the decrementer causes an interrupt whenever bit 0 changes from a logic 0 to a logic 1. the contents of this register can be read or written to by the mfspr or mtspr instruction. this register is undefined at reset. the decrementer is powered by standby power and continues counting when standby power is applied. to enable the decrementer control bits, use the timebase control and status register. the decrementer and timebase share the same tmbclk. decdecrementer this field is used by a down counter to cause decrementer interrupts. a read of this register always returns the current count value from the down counter. dec bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field dec reset r/w r/w spr 22 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dec reset r/w r/w spr 22 note: = undefined.
system interface unit 12-14 mpc823e reference manual motorola system interface unit 12 12.6 the powerpc timebase the timebase is defined by the powerpc architecture and is a 64-bit free-running binary counter that is incremented at a frequency determined by each implementation of the timebase. there is no interrupt or other indication generated when the count rolls over. the period of the timebase depends on the driving frequency. for the mpc823e, the timebase is clocked by the tmbclk clock and the period for the timebase is: the state of the timebase is unaffected by any resets and must be initialized by the software. reads and writes of the timebase are restricted to special instructions. for the mpc823e implementation, it is not possible to read or write the entire timebase in a single instruction. therefore, the mttb and mftb instructions are used to move the lower half of the timebase while the mttbu and mftbu instructions are used to move the upper half of the timebase. the timebase has two reference registers associated with it. a maskable interrupt is generated when the timebase count reaches the value programmed in one of the two reference registers and the two status bits indicate which of the two reference registers generated the interrupt. 12.6.1 timebase register the special-purpose 64-bit timebase (tb) register contains a 64-bit integer that is periodically incremented. there is no automatic initialization of this register. the system software must perform the initialization. the contents of the register can be written by the mtspr instruction and read by the mftb or mftbu instruction. tbutimebase upper the value stored in this field is used as an upper part of the timebase counter. tb-upper bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tbu reset r/w r/w spr 269 (read), 285 (write) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tbu reset r/w r/w spr 269 (read), 285 (write) note: = undefined. t tb 2 64 f tmbclk ---------------------- - =
system interface unit motorola mpc823e reference manual 12-15 system interface unit 12 tbltimebase lower the value stored in this field is used as the lower part of the timebase register. 12.6.2 timebase reference registers there are two special-purpose 32-bit read/write timebase reference registerstbrefu and tbreflassociated with the upper and lower parts of the timebase. when there is a match between the contents of the timebase and the reference register, a reference interrupt is enabled in the timebase control and status register. tbrefutimebase reference upper these bits represent the 32-bit reference value for the upper part of the timebase. tb-lower bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tbl reset r/w r/w spr 268 (read), 284 (write) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tbl reset r/w spr 268 (read), 284 (write) note: = undefined. tbrefu bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tbrefu reset r/w r/w addr (immr & 0xffff0000) + 0x204 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tbrefu reset r/w r/w addr (immr & 0xffff0000) + 0x206 note: = undefined.
system interface unit 12-16 mpc823e reference manual motorola system interface unit 12 tbrefltimebase reference lower these bits represent the 32-bit reference value for the lower part of the timebase. 12.6.3 timebase status and control register the 16-bit read/write timebase status and control register (tbscr) controls the timebase count enable and interrupt generation. it is also is used for reporting the source of the interrupts and can be read at any time. a status bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. tbirqtimebase interrupt request this field determines the interrupt priority level of the timebase. to specify a certain level, the appropriate bit must be set. refa and refbreference interrupt status if set, these bits indicate that a match has been detected between the corresponding reference register (tbrefu for refa and tbrefl for refb) and the timebase low register. each bit must be cleared by writing a 1. tbrefl bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tbrefl reset r/w r/w addr (immr & 0xffff0000) + 0x208 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tbrefl reset r/w r/w addr (immr & 0xffff0000) + 0x20a note: = undefined. tbscr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tbirq refa refb reserved refae refbe tbf tbe reset 0 00 0 0000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x200
system interface unit motorola mpc823e reference manual 12-17 system interface unit 12 bits 10C11reserved these bits are reserved and must be set to 0. refae and refbereference interrupt enable if one of these bits is asserted, the timebase generates an interrupt on assertion of the refa or refb bit. otherwise, the interrupt is disabled. tbftimebase freeze enable 0 = the timebase and decrementer are unaffected. 1 = the frz signal stops the timebase and decrementer. tbetimebase enable 0 = disables timebase and decrementer operation. 1 = enables timebase and decrementer operation. 12.7 the real-time clock the real-time clock is a 45-bit counter that is clocked by the pitrtclk clock. it is used to provide time-of-day indication to the operating system and application software. the counter is not affected by reset and operates in all low-power modes. it is initialized by the software. the real-time clock can be programmed to generate a maskable interrupt when the time value matches the value programmed in the alarm register. it can also be programmed to generate an interrupt once every second. a control and status register is used to enable or disable the different functions and report the interrupt source. the real-time clock registersrtcsc, rtc, rtsec, and rtcalare protected (locked) from accidental writes after poreset . to unlock the registers, you must write a key word (0x55ccaa33) to the rtck register. refer to section 5.4.2 keep-alive power for more information. figure 12-4. real-time clock block diagram pitrtclk frz divide 32-bit counter 32-bit register sec alarm = clock disable divide mux 38k interrupt interrupt by 9,600 by 8,192 clock rtsec
system interface unit 12-18 mpc823e reference manual motorola system interface unit 12 12.7.1 real-time clock status and control register the real-time clock status and control (rtcsc) register is used to enable the different real-time clock functions and for reporting the source of the interrupts. a status bit is cleared by writing a 1 (writing a zero has no effect) and more than one status bit can be cleared at a time. this register can be read at any time. rtcirqreal-time clock interrupt request this field controls the real-time clocks interrupt priority level. seconce per second interrupt this status bit is set every second and must be cleared by the software. alralarm interrupt this status bit is set when the value of the real-time clock is equal to the value programmed in the rtcal register. bit 10reserved this bit is reserved and must be set to 0. 38kreal-time clock source select the software must set this bit to get the proper timing of a second. 0 = assumes that it is driven by a 32.768khz crystal 1 = assumes that it is driven by a 38.4khz crystal. sieseconds interrupt enable this bit allows the real-time clock to generate an interrupt when the sec bit is set. 0 = disables seconds interrupt. 1 = the real-time clock generates an interrupt. rtcsc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rtcirq sec alr res 38k sie ale rtf rte reset 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x220 note: = undefined.
system interface unit motorola mpc823e reference manual 12-19 system interface unit 12 alealarm interrupt enable this bit allows the real-time clock to generate an interrupt when the alr bit is set. 0 = disables the seconds interrupt. 1 = the real-time clock generates an interrupt. rtfreal-time clock freeze enable 0 = the real-time clock is unaffected by the frz signal. 1 = the frz signal stops the real-time clock. rtereal-time clock enable 0 = the real-time clock timers are disabled. 1 = the real-time clock timers are enabled. 12.7.2 real-time clock register the 32-bit real-time clock (rtc) register contains the current value of the real-time clock. the maximum value is approximately 136 years. rtcreal-time clock this field represents time measured in seconds. each unit represents one second. rtc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rtc reset r/w r/w addr (immr & 0xffff0000) + 0x224 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rtc reset r/w r/w addr (immr & 0xffff0000) + 0x226 note: = undefined.
system interface unit 12-20 mpc823e reference manual motorola system interface unit 12 12.7.3 real-time clock alarm seconds register the 32-bit real-time clock alarm seconds register (rtsec) contains the value which divides the oscillator by 8,192 or 9,600 to generate one clock per second. this register is cleared when the rtc register is written. under normal conditions (rtcsc[38k] = 0), pitrtclk is assumed to be 8,192 hz (4.192 mhz/512 or 32.768 khz/4). rtsec resets at 8,192 and increments rtc. thus, rtc contains the time in seconds and rtsec functions as a pre- divider. for a 38.4khz crystal (instead of 32.768khz), rtcsc[38k] must be set to make rtsec reset at 9,600 instead of 8,192. counterclock seconds counter bits (fraction of a second). bit 13 is always the lsb of the count. 8,192 = the 38k field of the rtcsc is set to zero. pitrtclk is assumed to be 8192hz (4.192mhz/512 or 32.768khz/4). 9600 = the 38k field of the rtcsc is set to one. pitrtclk is assumed to be 9,600hz (38.4khz/4). bits 14C31reserved these bits are reserved and must be set to 0. rtsec bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field counter res reset r/w r/w r/w addr (immr & 0xffff0000) + 0x228 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset r/w r/w addr (immr & 0xffff0000) + 0x22a note: = undefined.
system interface unit motorola mpc823e reference manual 12-21 system interface unit 12 12.7.4 real-time clock alarm register the 32-bit read/write real-time clock alarm (rtcal) register is an alarm reference register. when the rtc register increments to the value stored in this register, an alarm interrupt is generated. alarmalarm reference counter this field indicates that an alarm interrupt will be generated as soon as there is a match between this field and the corresponding bits in the rtc register. the alarm has a 1 second resolution. rtcal bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field alarm reset r/w r/w addr (immr & 0xffff0000) + 0x22c bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field alarm reset r/w r/w addr (immr & 0xffff0000) + 0x22e note: = undefined.
system interface unit 12-22 mpc823e reference manual motorola system interface unit 12 12.8 the periodic interrupt timer the periodic interrupt timer consists of a 16-bit counter clocked by a pitrtclk clock supplied by the clock module. it decrements to zero when loaded with a value from the periodic interrupt timer count register (pitc) and after the timer reaches zero, the ps bit is set and an interrupt is generated if the pie bit is a logic 1. at the next input clock edge, the value in the pitc register is loaded into the counter and the process starts all over again. when a new value is loaded into the pitc register, the periodic interrupt timer is updated, the divider is reset, and the counter starts counting. if the ps bit is not cleared, it generates an interrupt at the interrupt controller and the interrupt remains pending until it is cleared. if the ps bit is set again, prior to being cleared, the interrupt remains pending until the ps bit is cleared. any write to the pitc register stops the current countdown and the count resumes with a new value in the pitc. if the pte bit is not set, the periodic interrupt timer is unable to count and retains the old count value. reads of the periodic interrupt timer have no effect on it. the timeout period is calculated as: solving this equation using a 32.768khz external clock gives: this gives a range from 122 microseconds with a pitc of 0x0000 to a maximum of 8 seconds with a pitc of 0xffff. figure 12-5. periodic interrupt timer block diagram clock frz 16-bit pitc pitrtclk ps pie pit pte disable clock modulus counter interrupt pit period pitc 1 + f pitrtclk ------------------------ - pitc 1 + externalclock 1or128 ----------------------------------------- - ? ?? 4 ? ----------------------------------------------------------- - = = pitperiod pitc 1 + 8192 ------------------------ - =
system interface unit motorola mpc823e reference manual 12-23 system interface unit 12 12.8.1 periodic interrupt status and control register the read/write periodic interrupt status and control register (piscr) contains the interrupt request level and the interrupt status bits. it also controls the 16 bits to be loaded in a modulus counter. pirqperiodic interrupt request level this field allows you to configure any interrupt level for periodic interrupts. see figure 12-2 for interrupt request levels. psperiodic interrupt status this bit can be negated by writing a 1 to it (zero has no effect). 0 = the periodic interrupt timer is unaffected. 1 = the periodic interrupt timer has issued an interrupt. bits 9C12reserved these bits are reserved and must be set to 0. pieperiodic interrupt enable 0 = disables the ps bit. 1 = enables the ps bit to generate an interrupt. pitfperiodic interrupt timer freeze enable 0 = the periodic interrupt timer is unaffected by the frz signal. 1 = the frz signal stops the periodic interrupt timer. pteperiodic timer enable 0 = the periodic interrupt timer is disabled. 1 = the periodic interrupt timer is enabled. piscr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pirq ps reserved pie pitf pte reset 0 0 0 001 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x240
system interface unit 12-24 mpc823e reference manual motorola system interface unit 12 12.8.2 periodic interrupt timer count register the read/write periodic interrupt timer count (pitc) register contains a 16-bit value that will be loaded into the periodic interrupt down counter. pitcperiodic interrupt timer count this field contains the count for the periodic timer. if this field is loaded with the value 0xffff, the maximum count period will be selected. bits 16C31reserved these bits are reserved and must be set to 0. pitc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pitc reset r/w r/w addr (immr & 0xffff0000) + 0x244 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x246 note: = undefined.
system interface unit motorola mpc823e reference manual 12-25 system interface unit 12 12.8.3 periodic interrupt timer register the periodic interrupt timer register (pitr) is a read-only register that shows the current value in the periodic interrupt down counter. writes to this register do not affect this register and reads of this register do not have any affect on the counter. pitperiodic interrupt timing count this field contains the current count remaining for the periodic timer. writes have no effect on this field. bits 16C31reserved these bits are reserved and must be set to 0. pitr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pit reset r/w r addr (immr & 0xffff0000) + 0x248 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r addr (immr & 0xffff0000) + 0x24a note: = undefined.
system interface unit 12-26 mpc823e reference manual motorola system interface unit 12 12.9 the software watchdog timer the system interface unit provides the software watchdog timer (swt) option that prevents system lockout when the software gets trapped in loops without a controlled exit. the software watchdog timer is enabled after system reset to automatically generate a system reset if it times out. if you do not need the software watchdog timer, you must clear the swe bit in the system protection control register (sypcr) to disable it. if it is used, the software watchdog timer requires a special service sequence to be executed on a periodic basis. if this periodic servicing action does not occur, the software watchdog timer times out and issues a reset or a nonmaskable interrupt, which is programmed in the swri bit of the sypcr. once the sypcr register is written by the software, the state of the swe bit cannot be changed. refer to section 12.12.1 system configuration and protection registers for more information. to service the software watchdog timer, write 0x556c and 0xaa39 to the software service register. this sequence clears the watchdog timer and the timing process begins again. if any value other than 0x556c or 0xaa39 is written to the software service register (swsr), the entire sequence must start over. although the writes must occur in the correct order before a timeout occurs, any number of instructions may be executed between the writes. this allows interrupts and exceptions to occur between the two writes when necessary. refer to figure 12-6 for more information. although most software disciplines permit or encourage the watchdog concept, some systems require a selection of timeout periods. for this reason, the software watchdog timer must provide a selectable range for the timeout period. figure 12-7 illustrates the present method for handling this requirement. figure 12-7 also shows the range that the value in the swtc field determines. this value is then loaded into a 16-bit decrementer clocked by the system clock. when necessary, an additional divide by 2,048 prescaler is used. figure 12-6. software watchdog timer service state diagram 0x556c / dont_reload reset 0xaa39 / reload state 0 waiting for 0x556c state 1 waiting for 0xaa39 not 0xaa39 / dont_reload not 0x556c / dont_reload
system interface unit motorola mpc823e reference manual 12-27 system interface unit 12 the decrementer begins counting when it is loaded with a value from the swtc field. after the timer reaches 0x0, a software watchdog expiration request is issued to the reset or nmi control logic. at reset, the value in the swtc register is set to the maximum value and is loaded into the software watchdog register (swr) again, thus starting the process over. when a new value is loaded into the swtc register, the software watchdog timer will not be updated until the servicing sequence is written to the swsr register. if the swe bit is loaded with the value 0, the modulus counter will not count. 12.9.1 software service register the software service register (swsr) is the location that the software watchdog timer servicing sequence writes to. to prevent a swt timeout, a write of 0x556c followed by 0xaa39 must be written to this register. the swsr can be written at any time, but returns all zeros when read. seqsequence this field is the pattern that is used to control the state of the software watchdog timer. figure 12-7. software watchdog timer block diagram swsr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field seq reset 0 r/w w addr (immr & 0xffff0000) + 0x00e disable clock frz swr / decrementer timeout 16-bit swtc swe service logic reload rollover = 0 reset swsr mux 2,048 core swp clock divide by or nmi
system interface unit 12-28 mpc823e reference manual motorola system interface unit 12 12.10 freeze operation when the frz signal is asserted, the clocks to the software watchdog, periodic interrupt timer, real-time clock, timebase counter, and decrementer can be disabled. this is controlled by the associated bits in the control register of each timer. if they are programmed to stop counting when frz is asserted, the counters maintain their values until frz is negated. the bus monitor, however, will be enabled regardless of this signals state. 12.10.1 low-power stop operation when the powerpc core is set in a low-power mode (doze, sleep, deep sleep), the software watchdog timer is frozen. it remains frozen and maintains its count value until the core exits this mode and continues to execute instructions. the periodic interrupt timer, decrementer, and timebase are not influenced by these low-power modes and they continue to run at their respective frequencies. these timers can generate an interrupt to bring the mpc823e out of the low-power modes.
system interface unit motorola mpc823e reference manual 12-29 system interface unit 12 12.11 multiplexing the system interface unit pins due to the limited number of pins available in the mpc823e package, some of the functionalities share pins. the actual mpc823e pinout is illustrated in section 2 external signals . the following table shows how the functionality is controlled on each pin. table 12-2. multiplexing control pin name pin configuration control tsiz0/reg dynamically active depending if the transaction addresses a slave controlled by the pcmcia interface. bdip /gpl_b5 rsv /irq2 kr /retry /irq4 /spkrout dp[0:3]/irq [3:6] frz/irq6 programmed in the siumcr. cs6 /ce1_b cs7 /ce2_b address matching and bank valid bits. when there is a transfer such that there is a match in either memory controller bank 6 or any pcmcia bank mapped to slot b, the cs 6/ce1_b will be asserted. when there is a transfer such that there is a match in either memory controller bank 7 or any pcmcia bank mapped to slot b, the cs 7/ce2_b will be asserted. we0 /bs_ab0 /iord we1 /bs_ab 1 /iowr we2 /bs_ab 2 /pcoe we3 /bs_ab 3 /pcwe dynamically active depending on the machine (gpcm, upmb, or pcmcia interface) assigned to control the required slave. gpl_a0 /gpl_b0 dynamically active depending on the machine (upma or upmb) assigned to control the required slave. oe /gpl_a1 /gpl_b1 dynamically active depending on the machine (gpcm, upma, or upmb) assigned to control the required slave. gpl_a [2:3]/gpl_b [2:3]/ cs [2:3] gpl_a [2:3]/gpl_b [2:3]: dynamically active depending on the machine (upma or upmb) assigned to control the required slave. gpl_a [2:3]/cs [2:3]: programmed in the siumcr. ale_b/dsck/at1 ip_b[0:1]/iwp[0:1]/vfls[0:1] ip_b2/iois16_b /at2 ip_b3/iwp2/vf2 ip_b4/lwp0/vf0 ip_b5/lwp1/vf1 ip_b6/dsdi/at0 ip_b7/ptr /at3 tdi/dsdi tck/dsck tdo/dsdo programmed in the siumcr and hard reset configuration. upwaita/gpl_a4/as programmed in the siumcr and mamr of the memory controller. op2/modck2/sts op3/modck2/dsdo at power-on reset, this functions as modck[1:2] otherwise, programmed in the siumcr and hard reset configuration.
system interface unit 12-30 mpc823e reference manual motorola system interface unit 12 12.12 programming the system interface unit 12.12.1 system configuration and protection registers 12.12.1.1 siu module configuration register. the siu module configuration register (siumcr) contains bits that configure various features in the system interface unit. earbexternal arbitration if the earb bit is set, then external arbitration is assumed. if it is cleared, internal arbitration is performed. for more information, see section 13.4.6 arbitration phase-related signals . earpexternal arbitration request priority this field defines the priority of the external masters arbitration request. this field is valid when earb is cleared. 000 is the lowest priority level and 111 the highest. for more information, refer to figure 13-20 in section 13 external bus interface. bits 4C7, 13, 24, and 28C31reserved these bits are reserved and must be set to 0. dshwdata show cycles this bit selects the show cycle mode to be applied to data cycles. instruction show cycles are programmed in the ictrl register. refer to section 20.6.2 development port registers for more information. this bit is locked by the dlk bit. 0 = disable show cycles for all internal data cycles. 1 = show address and data of all internal data cycles. siumcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field earb earp reserved dshw dbgc dbpc res frc dlk reset 00 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field opar pncs dpc mpre mlrc aeme seme res gb5e b2dd b3dd reserved reset 0000 0 000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x002
system interface unit motorola mpc823e reference manual 12-31 system interface unit 12 dbgcdebug pin configuration this field configures the debug pin functionality. the default value is set by the hard reset configuration word, as shown in section 4.3.1.1 hard reset configuration word . 00 = ip_b[0:1]/iwp[0:1]/vfls[0:1] functions as ip_b[0:1]. ip_b3/iwp2/vf2 functions as ip_b3. ip_b4/lwp0/vf0 functions as ip_b4. ip_b5/lwp1/vf1 functions as p_b5. op2/modck1/sts functions as op2. ale_b/dsck/at1 functions as ale_b. ip_b2/at2 functions as ip_b2. ip_b6/dsdi/at0 functions as ip_b6. ip_b7/ptr /at3 functions as ip_b7. op3/modck2/dsdo functions as op3. 01 = ip_b[0:1]/iwp[0:1]/vfls[0:1] functions as iwp[0:1]. ip_b3/iwp2/vf2 functions as iwp2. ip_b4/lwp0/vf0 functions as lwp0. ip_b5/lwp1/vf1 functions as lwp1. op2/modck1/sts functions as sts . ale_b/dsck/at1 functions as at1. ip_b2/at2 functions as at2. ip_b6/dsdi/at0 functions as at0. ip_b7/ptr /at3 functions as at3. op3/modck2/dsdo functions as op3. 10 = reserved. 11 = ip_b[0:1]/iwp[0:1]/vfls[0:1] functions as vfls[0:1]. ip_b3/iwp2/vf2 functions as vf2. ip_b4/lwp0/vf0 functions as vf0. ip_b5/lwp1/vf1 functions as vf1. op2/modck1/sts functions as sts . ale_b/dsck/at1 functions as at1. ip_b2/at2 functions as at2. ip_b6/dsdi/at0 functions as at0. ip_b7/ptr /at3 functions as at3. op3/modck2/dsdo functions as op3. dbpcdebug port pins configuration this field determines the active pins for the development port. the default value is set by the hard reset configuration word, as shown in section 4.3.1.1 hard reset configuration word . 00 = ale_b/dsck/at1 functions as defined by dbgc. ip_b6/dsdi/at0 functions as defined by dbgc. op3/modck2/dsdo functions as defined by dbgc. ip_b7/ptr /at3 functions as defined by dbgc. tck/dsck functions as dsck.
system interface unit 12-32 mpc823e reference manual motorola system interface unit 12 tdi/dsdi functions as dsdi. tdo/dsdo functions as dsdo. 01 = ale_b/dsck/at1 functions as defined by dbgc. ip_b6/dsdi/at0 functions as defined by dbgc. op3/modck2/dsdo functions as defined by dbgc. ip_b7/ptr /at3 functions as defined by dbgc. tck/dsck functions as tck. tdi/dsdi functions as tdi. tdo/dsdo functions as tdo. 10 = reserved. 11 = ale_b/dsck/at1 functions as dsck. ip_b6/dsdi/at0 functions as dsdi. op3/modck2/dsdo functions as dsdo. ip_b7/ptr /at3 functions as ptr . tck/dsck functions as tck. tdi/dsdi functions as tdi. tdo/dsdo functions as tdo. frcfrz pin configuration this bit configures the functionality of the frz/irq6 pin. 0 = frz/irq6 functions as frz. 1 = frz/irq6 functions as irq6 . dlkdebug register lock if this bit is set, bits 8C15 are locked and writes to those bits are no longer performed. these bits are writable in test mode once the internal frz signal is asserted, regardless of the state of dlk. this bit is cleared by reset. oparodd parity this bit is used to program odd or even parity. it can also be used to generate parity errors for testing purposes by writing the memory with opar = 1 and reading the memory with opar = 0. pncsparity enable for nonmemory controller regions this bit enables parity generation/checking for memory regions not controlled by the mpc823e memory controller. dpcdata parity pins configuration this bit configures the functionality of the dp[0:3]/irq [3:6] pins. 0 = dp[0:3]/irq [3:6] functions as irq [3:6]. 1 = dp[0:3]/irq [3:6] functions as dp[0:3].
system interface unit motorola mpc823e reference manual 12-33 system interface unit 12 mpremultiprocessors reservation enable if this bit is set, then the interprocessor reservation protocol is enabled. the rsv pin functions as defined in section 13.4.10 storage reservation protocol . 0 = rsv /irq2 functions as irq2 . 1= rsv /irq2 functions as rsv . mlrcmulti-level reservation control this field configures the functionality of the kr /retry /irq4 /spkrout pins. 00 = kr /retry /irq4 /spkrout functions as irq4 . 01 = kr /retry /irq4 /spkrout is three-stated. 10 = kr /retry /irq4 /spkrout functions as kr /retry . 11 = kr /retry /irq4 /spkrout functions as spkrout. aemeasynchronous external master enable this bit configures how the memory controller refers to external asynchronous masters initiating a transaction. if this bit is set, the memory controller interprets any assertion on the as pin as an external asynchronous master initiating a transaction. if it is reset, the memory controller ignores the value of the as pin. this bit and the gpla4dis bit of the machine a mode register (described in section 15.3.1.5 machine a mode register ) controls the direction and functionality of the upwaita/gpl_a4/as pins. semesynchronous external master enable this bit configures how the memory controller refers to external synchronous masters initiating a transaction. if this bit is set, the memory controller interprets any assertion on the ts pin the external bus does not own as an external synchronous master initiating a transaction. if it is reset, the memory controller ignores the value of the ts pin when it does not own the external bus. when the mpc823e owns the bus, the memory interprets the assertion of the ts pin as an internal request. gb5egpl_b5 enable 0 = the bdip functionality is active. 1 = the gpl_b 5 of the memory controller functionality is active. b2ddbank 2 double drive if this bit is set, the cs2 signal is reflected on gpl_x2 . aeme gpla4dis pin usage upwait value as value x 0 functions as gpl_a4 gnd vcc 0 1 functions as upwait pin value vcc 1 1 functions as as gnd pin value
system interface unit 12-34 mpc823e reference manual motorola system interface unit 12 b3ddbank 3 double drive if this bit is set, the cs3 signal is reflected on gpl_x3 . 12.12.1.2 internal memory map register. the internal memory map register (immr) is located within the powerpc special register space. it contains the identification of a specific device, as well as a base for the internal memory map. based on the value read from this register, the software can deduce the availability and location of any on-chip system resource. the contents of this register can be read by the mfspr instruction and the isb field can be written by the mtspr instruction. however, the partnum and masknum fields are mask programmed and cannot be changed for any device. isbinternal space base this read/write field defines the base address of the internal memory space. the initial value of this field can be configured at reset to one of four addresses and changed to any value by the software. the number of programmable bits in this field and the resolution of the location of internal space depends on the internal memory space of the specific implementation. in the mpc823e, you can program all 16 bits. for information on the devices internal memory map, refer to section 3 memory map and for the available default initial values refer to section 4.3.1.1 hard reset configuration word . partnumpart number this read-only field is mask programmed with a code corresponding to the part number of the part on which the system interface unit is located. it is intended to help with factory test and user code that is sensitive to part refinements. this field changes as the part number changes. for example, it would change if a new module is added or if the size of the memory module is revised. however, it would not change if the part is revised to fix a bug in an existing module. the mpc823e has a part number of 0x24. the other byte of information reflects the revision number. refer to our website for the corresponding revision number for your particular version of the silicon. immr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field isb reset 0 r/w r/w addr spr 638 (decimal) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field partnum masknum reset 00100000 * r/w rr addr spr 638 (decimal) note: * the value of this field depends on the mask revision.
system interface unit motorola mpc823e reference manual 12-35 system interface unit 12 masknummask number this read-only field is mask-programmed with a code corresponding to the mask number of the part on which the system interface unit is located. it is intended to help with factory test and user code that is sensitive to part refinements. as a result, the value of this field depends on the mask revision. 12.12.1.3 system protection control register. the system protection control register (sypcr) controls the system monitors, software watchdog period, and bus monitor timing. this register can be read at any time, but can only be written once after system reset. swtcsoftware watchdog timer count this field contains the count value for the software watchdog timer. bmebus monitor enable this bit controls the operation of the bus monitor when an internal to external bus cycle is executed. 0 = disable the bus monitor. 1 = enable the bus monitor. bmtbus monitor timing this field defines the timeout period, in 8 system clock resolution, for the bus monitor. the maximum timeout is 2,040 clocks. bits 25C27reserved these bits are reserved and must be set to 0. sypcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field swtc reset 1 r/w r/w addr (immr & 0xffff0000) + 0x004 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field bmt bme reserved swf swe swri swp reset 1 0 0 0111 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x006 note: if the bus monitor is disabled, the transfer error conditions will not assert the tea pin.
system interface unit 12-36 mpc823e reference manual motorola system interface unit 12 swfsoftware watchdog freeze 0 = the software watchdog timer continues counting even if the frz signal is asserted. 1 = the software watchdog timer stops counting when the frz signal is asserted. swesoftware watchdog enable this bit enables the software watchdog timer. to disable the software watchdog timer, it must be cleared by the software after a system reset. swrisoftware watchdog reset/interrupt select 0 = the software watchdog timer causes a nonmaskable interrupt to the core. 1 = the software watchdog timer causes a system reset (default). swpsoftware watchdog prescale 0 = the software watchdog timer is not prescaled. 1 = the software watchdog timer is prescaled by a factor of 2,048. 12.12.1.4 transfer error status register. the transfer error status register (tesr) contains a bit for each exception source generated by a transfer error. a bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were cleared. the bits are cleared by reset or by writing a 1 to the appropriate bit. canceled speculative accesses that do not cause an interrupt may set these bits. the register has two identical sets of fieldsCone is associated with instruction transfers and the other with data transfers. bits 0C17 and 24C25reserved these bits are reserved and must be set to 0. tesr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r addr (immr & 0xffff0000) + 0x020 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved iext itmt ipb0 ipb1 ipb2 ipb3 reserved dext dtmt dpb0 dpb1 dpb2 dpb3 reset 0 000000 0 000000 r/w r rrrrrr r rrrrrr addr (immr & 0xffff0000) + 0x022
system interface unit motorola mpc823e reference manual 12-37 system interface unit 12 iextinstruction external transfer error acknowledge this bit is set if the cycle is terminated by an externally generated tea signal when an instruction fetch is initiated. itmtinstruction transfer monitor timeout this bit is set if the cycle is terminated by a bus monitor timeout when an instruction fetch is initiated. ipb0Cipb3instruction parity error on bytes 0C3 there are four parity error status bits for each byte lane. one of these is set for the byte that had a parity error when an instruction was fetched. parity check for a memory region that is not controlled by the memory controller is enabled by the pncs bit in the siumcr, as shown in section 12.12.1.1 siu module configuration register . dextdata external transfer error acknowledge this bit is set if the cycle is terminated by an externally generated tea signal when a data load or store is requested by an internal master. dtmtdata transfer monitor timeout this bit is set if the cycle is terminated by a bus monitor timeout when a data load or store is requested by an internal master. dpb0Cdpb3data parity error on bytes 0C3 there are four parity error status bits for each byte lane. one of these is set for the byte that had a parity error when a data load was requested by an internal master. parity check for a memory region that is not controlled by the memory controller is enabled by the pncs bit in the siumcr, as shown in section 12.12.1.1 siu module configuration register .
motorola mpc823e reference manual 13-1 external bus 13 interface section 13 external bus interface the mpc823e bus is synchronous and burstable. signals driven on this bus are required to make the setup and hold time relative to the bus clocks rising edge. this bus has the ability to support multiple masters. the mpc823e architecture supports byte, half-word, and word operands allowing access to 8-,16-, and 32-bit data ports through the use of synchronous cycles controlled by the transfer size output (tsizx) signals. the slave access to 16- and 8-bit ports is controlled by the memory controller. 13.1 features the following is a list of the bus interfaces main features: ? 26-bit address bus with transfer size indication ? 32-bit data bus ? ttl-compatible interface ? compatible with powerpc ? architecture ? interfaces to slave devices easily ? synchronous bus operation ? data parity support 13.2 transfer signals the bus transfers information between the mpc823e and the external memory or peripheral device. external devices can accept or provide 8,16, and 32 bits in parallel and must follow the handshake protocol. the maximum number of bits accepted or provided during a bus transfer is defined as the port width. the mpc823e contains an address bus that specifies the transfers address and a data bus that transfers the data. control signals indicate the beginning and type of the cycle, as well as the address space and size of the transfer. the selected device then controls the length of the cycle with the signal used to terminate the cycle. a strobe signal for the address bus indicates the validity of the address and provides timing information for the data. the mpc823e bus is synchronous, but the bus and control input signals must be timed to setup and hold times relative to the rising edge of the clock. in this situation, bus cycles can be completed in two clock cycles.
external bus interface 13-2 mpc823e reference manual motorola external bus 13 interface furthermore, for all inputs, the mpc823e latches the level of the input during a sample window around the rising edge of the clock signal. this window is illustrated in figure 13-1, where tsu and tho are the input setup and hold times, respectively. to ensure that an input signal is recognized on a specific falling edge of the clock, the input must be stable during the sample window. if an input makes a transition during the window time period, the level recognized by the mpc823e is not predictable. however, the mpc823e always resolves the latched level to either a logic high or low before using it. in addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. figure 13-1. input sample window clock signal tho tsu sample window
external bus interface motorola mpc823e reference manual 13-3 external bus 13 interface 13.2.1 control signals the mpc823e initiates a bus cycle by driving the address, size, address type, cycle type, and read/write outputs. at the beginning of a bus cycle, the tsiz0 and tsiz1 signals are driven with the at signals. tsizx indicates the number of bytes to be transferred during an operand cycle that consists of one or more bus cycles. these signals are valid at the rising edge of the clock in which the ts signal is asserted. the rd/wr signal determines the direction of the transfer during a bus cycle. driven at the beginning of a bus cycle, rd/wr is valid at the rising edge of the clock in which the ts signal is asserted. however, rd/wr only transitions when a write cycle is preceded by a read cycle or vice versa. the signal may remain low for consecutive write cycles. figure 13-2. mpc823e bus signals a[6:31] rd / wr burst tsiz[0:1] at[0:3] sts ts bi kr /retry d[0:31] ta tea bdip dp[0:3] br bg bb 26 1 1 2 4 1 1 1 1 32 1 1 4 1 1 1 1 address and transfer attributes transfer start arbitration data transfer termination reservation protocol cycle rsv 1 ptr 1
external bus interface 13-4 mpc823e reference manual motorola external bus 13 interface 13.3 bus signal descriptions the following table decribes each bus interface signal. more detailed descriptions can be found in subsequent sections of this manual. table 13-1. bus interface signals mnemonic pins active i/o description address and transfer attributes a[6:31] 26 high o address bus driven by the mpc823e when it owns the external bus. it specifies the physical address of the bus transaction. these signals can change during a transaction when controlled by the memory controller. i sampled by the mpc823e when an external device initiates a transaction and the memory controller was configured to handle external master accesses. rd/wr 1 high o read/write driven by the mpc823e along with the address when it owns the external bus. driven high indicates that a read access is in progress and driven low indicates that a write access is in progress. i sampled by the mpc823e when an external device initiates a transaction and the memory controller was configured to handle external master accesses. burst 1 low o burst transfer driven by the mpc823e along with the address when it owns the external bus. driven low indicates that a burst transfer is in progress and driven high indicates that the current transfer is not a burst. i sampled by the mpc823e when an external device initiates a transaction and the memory controller was configured to handle external master accesses. tsiz[0:1] 2 high o transfer size driven by the mpc823e along with the address when it owns the external bus. it specifies the data transfer size for the transaction. i sampled by the mpc823e when an external device initiates a transaction and the memory controller was configured to handle external master accesses. at[0:3] 3 high o address type driven by the mpc823e along with the address when it owns the external bus. it provides additional information about the address on the current transaction. i used only for testing purposes. rsv 1 low o reservation transfer driven by the mpc823e along with the address when it owns the external bus. it provides additional information about the address on the current transaction. i used only for testing purposes. ptr 1 low o program trace driven by the mpc823e along with the address when it owns the external bus. it provides additional information about the address on the current transaction. i used only for testing purposes.
external bus interface motorola mpc823e reference manual 13-5 external bus 13 interface bdip 1 low o burst data in progress driven by the mpc823e when it owns the external bus. it is part of the burst protocol. asserted indicates that the second beat in front of the current one is requested by the master. this signal is negated prior to the end of a burst to terminate the burst data phase early. i used only for testing purposes. transfer start ts 1 low o transfer start driven by the mpc823e when it owns the external bus.it indicates the start of a transaction on the external bus. i sampled by the mpc823e when an external device initiates a transaction and the memory controller was configured to handle external master accesses. sts 1 low o special transfer start driven by the mpc823e when it owns the external bus. it indicates the start of a transaction on the external bus or an internal transaction in show cycle mode. reservation protocol kr /retry 1 low i kill reservation/retry when a bus cycle is initiated by a stwcx instruction that was issued by the core to a nonlocal bus on which the storage reservation has been lost, this signal is used by the nonlocal bus interface to back-off the cycle. refer to section 13.4.10 storage reservation protocol . for a regular transaction, this signal is driven by the slave device to indicate that the mpc823e has to relinquish ownership of the bus and retry the cycle. data d[0:31] 32 high i/o data bus the data bus has the following byte lane assignments: data byte byte lane d[0:7] 0 d[8:15] 1 d[16:23] 2 d[24:31] 3 o driven by the mpc823e when it owns the external bus and has initiated a write transaction to a slave device. for single beat transactions, if external a[6:31] and tsiz[0:1] do not select the byte lanes for transfer, they will not supply valid data. i driven by the slave in a read transaction. for single beat transactions, if external a[6:31] and tsiz[0:1] do not select the byte lanes for transfer, they will not be sampled by the mpc823e. it is also sampled by the mpc823e when the external master acquires the bus. table 13-1. bus interface signals (continued) mnemonic pins active i/o description
external bus interface 13-6 mpc823e reference manual motorola external bus 13 interface dp[0:3] 4 high i/o parity bus each parity signal corresponds to each one of the data bus lanes: data bus byte parity line d[0:7] dp0 d[8:15] dp1 d[16:23] dp2 d[24:31] dp3 o driven by the mpc823e when it owns the external bus and has initiated a write transaction to a slave device. each parity signal has the parity value (even or odd) of the corresponding data bus byte. for single beat transactions, if external a[6:31] and tsiz[0:1] do not select the byte lanes for transfer, they will not have a valid parity line. i driven by the slave in a read transaction. each parity signal is sampled by the mpc823e and checked (if enabled) against the expected value parity value (even or odd) of the corresponding data bus byte. for single beat transactions, if external a[6:31] and tsiz[0:1] do not select the byte lanes for transfer, they will not be sampled by the mpc823e and its parity signals will not be checked. transfer cycle termination ta 1 low i transfer acknowledge driven by the slave device the current transaction was addressed to. it indicates that the slave has received the data on the write cycle or returned the data on the read cycle. if the transaction is a burst, ta must be asserted for each one of the transaction beats. o driven by the mpc823e when the slave device is controlled by the on-chip memory controller. tea 1 low i transfer error acknowledge driven by the slave device the current transaction was addressed to. it indicates that an error condition has occurred during the bus cycle. o driven by the mpc823e when the internal bus monitor detects an erroneous bus condition. bi 1 low i burst inhibit driven by the slave device the current transaction was addressed to. it indicates that the current slave does not support burst mode. o driven by the mpc823e when the slave device is controlled by the on-chip memory controller. table 13-1. bus interface signals (continued) mnemonic pins active i/o description
external bus interface motorola mpc823e reference manual 13-7 external bus 13 interface 13.4 bus interface operation the mpc823e generates a system clock output (clkout) that sets the frequency of operation for the bus interface. internally, the mpc823e uses a phase-lock loop (pll) circuit to generate a master clock for all of the core circuitry, which is phase-locked to the clkout output signal. all signals for the mpc823e bus interface are specified with respect to the rising-edge of the external clkout and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. since the same clock edge is referenced for driving or sampling the bus signals, the possibility of clock skew could exist between various modules in a system because of routing or using multiple clock lines. it is your responsibility to handle any clock skew problems that could occur as a result of layout, lead-length, and physical routing. arbitration br 1 low i bus request when the internal arbiter is asserted, it indicates that an external master is requesting the bus. o driven by the mpc823e when the internal arbiter is disabled and the chip is not parked . bg 1 low o bus grant when the internal arbiter is enabled, the mpc823e asserts this signal to indicate that an external master can assume ownership of the bus and begin a bus transaction. the bg signal must be qualified by the master requesting the bus to ensure it is the bus owner: qualified bg = bg & bb i when the internal arbiter is disabled, the bg is sampled and properly qualified by the mpc823e when an external bus transaction is to be executed by the chip. bb 1 low o bus busy when the internal arbiter is enabled, the mpc823e asserts this signal to indicate that it is the current owner of the bus. when the internal arbiter is disabled, it will assert this signal after the external arbiter grants the chip ownership of the bus and it is ready to start the transaction. i when the internal arbiter is enabled, the mpc823e samples this signal to get an indication of when the external master ended its bus tenure (bb negated). when the internal arbiter is disabled, the bb is sampled to properly qualify the bg line when an external bus transaction is to be executed by the chip. note: o indicates an output from the mpc823e and i indicates an input. table 13-1. bus interface signals (continued) mnemonic pins active i/o description
external bus interface 13-8 mpc823e reference manual motorola external bus 13 interface 13.4.1 basic transfers the basic transfer protocol defines the sequence of actions that must occur on the mpc823e bus to perform a complete bus transaction. the chronological sequence or phase of a typical bus transfer is as follows: 1. arbitration 2. address transfer 3. data transfer 4. termination this protocol provides for an arbitration phase and an address and data transfer phase. the arbitration phase specifies the master that initiates the next transaction. the address phase specifies the address for the transaction and the transfer attributes that describe the transaction. the data phase performs the transfer of data. it can transfer a single beat of data (4 bytes or less) for nonburst operations, a 4-beat burst of data, an 8-beat burst of data, or a 16-beat burst of data. 13.4.2 single beat transfers during the data transfer phase, data is transferred from master to slave on write cycles or from slave to master on read cycles. on a write cycle, the master drives the data as soon as it can, but never before the cycle following the address transfer phase. the master has to take into consideration the one dead clock cycle when switching between drivers to avoid electrical contention. the master can stop driving the data bus as soon as it samples the ta line asserted on the rising edge of the clkout. on a read cycle the master accepts the data bus contents as valid at the rising edge of the clkout in which the ta signal is sampled asserted.
external bus interface motorola mpc823e reference manual 13-9 external bus 13 interface 13.4.2.1 single beat read flow. the basic read cycle begins with a bus arbitration, followed by the address transfer and the data transfer. the handshakes are illustrated in the following diagrams as applicable to the fixed transaction protocol. figure 13-3. basic flow diagram of a single beat read cycle request bus (br ) receives bus grant (bg ) from arbiter asserts bus busy (bb ) if no other master is driving assert transfer start (ts ) drives address and attributes receives address returns data asserts transfer acknowledge (ta ) receives data slave master
external bus interface 13-10 mpc823e reference manual motorola external bus 13 interface figure 13-4. single beat read cycleCbasic timingCzero wait states clkout a[6:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst tsiz[0:1],at[0:3]
external bus interface motorola mpc823e reference manual 13-11 external bus 13 interface figure 13-5. single beat read cycleCbasic timingCone wait state clkout a[6:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst tsiz[0:1],at[0:3] wait state
external bus interface 13-12 mpc823e reference manual motorola external bus 13 interface 13.4.2.2 single beat write flow. the basic write cycle begins with a bus arbitration, followed by the address transfer and the data transfer. the handshakes are illustrated in figure 13-6, figure 13-7, figure 13-8, and figure 13-9 as applicable to the fixed transaction protocol. figure 13-6. basic flow diagram of a single beat write cycle master slave request bus (br ) receives bus grant (bg ) from arbiter asserts bus busy (bb ) if no other master is driving assert transfer start (ts ) drives address and attributes drives data asserts transfer acknowledge (ta ) stops driving data receives address receives data
external bus interface motorola mpc823e reference manual 13-13 external bus 13 interface figure 13-7. single beat write cycleCbasic timingCzero wait states clkout a[6:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled burst tsiz[0:1],at[0:3]
external bus interface 13-14 mpc823e reference manual motorola external bus 13 interface figure 13-8. single beat write cycle of one wait state clkout a[6:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled burst tsiz[0:1],at[0:3] wait state
external bus interface motorola mpc823e reference manual 13-15 external bus 13 interface a typical single beat transfer assumes that the external memory has a 32-bit port size. the mpc823e provides an effective mechanism for interfacing with 16-bit port size memories and 8-bit port size memories, thus allowing transfers to these devices when they are controlled by the internal memory controller. the port size (ps) timing shown in the following figures is representative of the ps field, which is described in section 15.3.1.1 base registers . figure 13-9. single beat, 32-bit data, write cycle from a 16-bit port size clkout a[6:31] ts br bg bb data ta rd/wr burst tsiz[0:1] ps 10 00 10 a a + 2 abcdefgh efghefgh sts
external bus interface 13-16 mpc823e reference manual motorola external bus 13 interface 13.4.3 burst transfers the mpc823e uses burst transfers to access 16-byte operands. a burst accesses a block of 16 bytes that must be aligned to a 16-byte memory boundary by supplying a starting address that points to the critical words and requiring the memory device to sequentially drive/sample each word on the data bus. the selected slave device must internally increment the external a[28:29] signal (or a30 for a 16-bit port size slave device) of the supplied address for each transfer, thus causing the address to wrap around at the end of the 4-word block. the address and transfer attributes supplied by the mpc823e remain stable during the transfers and the selected device terminates each transfer by driving/ sampling the word on the data bus and asserting the ta signal. the mpc823e also supports burst-inhibited transfers for slave devices that are unable to support bursting. for this type of bus cycle, the selected slave device supplies/samples the first word the mpc823e points to and asserts the bi signal with ta for the first transfer of the burst access. the mpc823e responds by terminating the burst and accessing the remainder of the 16-byte block, thus using three read/write cycle bus (each one for a word) for a 32-bit port width slave, seven read/write cycle bus for a 16-bit port width slave, or fifteen read/write cycle bus for an 8-bit port width slave. burst transfers assume that the external memory has a 32-bit port size. the mpc823e provides an effective mechanism for interfacing with 16- and 8-bit port size memories that allow burst transfers to these devices when they are controlled by the internal memory controller. the mpc823e attempts to initiate a burst transfer as normal. if the slave device responds to a cycle prior to the ta signal for the first beat, its port size is 8 or 16 bits and the mpc823e completes a burst of 8- or 16-bit beats. effectively, each of the data beats of the burst transfers only 1 or 2 bytes. this 8- or 16-beat burst is also considered an atomic transaction, so the mpc823e will not allow other unrelated master accesses or bus arbitration to intervene between the transfers. 13.4.4 the burst mechanism the mpc823e burst mechanism consists of one signal indicating that the cycle is a burst cycle, one indicating the duration of the burst data, and another signal indicating whether the slave is burstable. these signals are in addition to the basic signals of the bus. at the start of the burst transfer, the master drives the address, address attributes, and burst signal to indicate that a burst transfer is being initiated, along with the assertion of the ts signal. if the slave is burstable, it negates the bi signal. if the slave cannot burst, it must assert the bi signal. during the data phase of a burst write cycle the master drives the data. it also asserts the bdip signal if it intends to drive a subsequent data beat after the current data beat. when the slave has received the data, it asserts the ta signal to let the master know it is ready for the next data transfer. the master again drives the next data and asserts or negates the bdip signal. if the master does not intend to drive another data beat after the current one, it negates the bdip signal to let the slave know that the next subsequent data beat transfer is the last data of the burst write transfer. during the data phase of a burst read cycle, the master receives data from the addressed slave. if the master needs more than one data, it asserts the bdip signal. when the data is received prior to the last data, the master negates the bdip signal. thus, the slave stops driving new data after it receives the negation of the bdip signal at the rising edge of the clock. see figure 13-10 for details.
external bus interface motorola mpc823e reference manual 13-17 external bus 13 interface figure 13-10. basic flow diagram of a burst read cycle master slave request br receive bg from arbiter assert bb if no other master is driving assert ts assert address and attributes receive address return data assert ta receive data assert burst assert bdip bdip asserted yes return data assert ta receive data bdip asserted yes return data assert ta receive data bdip asserted yes return data assert ta receive data negate bdip no do not drive data no do not drive data no do not drive data negate burst stop driving address and attributes negate bb
external bus interface 13-18 mpc823e reference manual motorola external bus 13 interface figure 13-11. burst-read cycleC32-bit port sizeCzero wait state clkout a[6:31],at[0:3] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 ps 00
external bus interface motorola mpc823e reference manual 13-19 external bus 13 interface figure 13-12. burst-read cycleC32-bit port sizeCone wait state clkout a[6:31],at[0:3] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 wait state ps 00
external bus interface 13-20 mpc823e reference manual motorola external bus 13 interface figure 13-13. burst-read cycleC32-bit port sizeCwait states between beats clkout a[6:31],at[0:3] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 wait state 00 ps
external bus interface motorola mpc823e reference manual 13-21 external bus 13 interface figure 13-14. basic flow diagram of a burst write cycle master slave request br receive bg from arbiter assert bb if no other master is driving assert ts assert address and attributes receive address assert ta drive data assert burst drive data bdip asserted yes assert ta assert ta stop driving data negate bdip no do not sample next data assert bdip drive data bdip asserted yes assert ta no do not sample next data drive data bdip asserted yes no do not sample next data negate bb negate burst stop driving address and attributes receive data receive data receive data receive data
external bus interface 13-22 mpc823e reference manual motorola external bus 13 interface figure 13-15. burst-read cycleC16-bit port sizeCone wait state between beats clkout a[6:31],at[0:3] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip 00 ps 10
external bus interface motorola mpc823e reference manual 13-23 external bus 13 interface figure 13-16. burst-write cycleC32-bit port sizeCzero wait states clkout a[6:31],at[0:3] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is sampled is sampled is sampled is sampled last beat will drive another data 00
external bus interface 13-24 mpc823e reference manual motorola external bus 13 interface figure 13-17. burst-inhibit cycleC32-bit port size clkout a[6:27] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip 00 bi a[28:29] a[30:31] n n+1 mod 4 n+2 mod 4 n+3 mod 4
external bus interface motorola mpc823e reference manual 13-25 external bus 13 interface 13.4.5 transfer alignment and packaging the mpc823e external bus only supports natural address alignment that forces the following restrictions: ? byte access can have any address alignment ? half-word access must have address bit 31 equal to 0 ? word access must have address bits 30-31 equal to 0 ? for burst access must have address bits 30-31 equal to 0 the mpc823e can perform operand transfers through its 32-bit data port. if the transfer is controlled by the internal memory controller, the mpc823e can support 8- and 16-bit data port sizes. the bus requires that the portion of the data bus used for a transfer to or from a particular port size to be fixed. a 32-bit port must reside on data bus bits 0-31, a 16-bit port must reside on bits 0-15, and an 8-bit port must reside on bits 0-7. the mpc823e always tries to transfer the maximum amount of data on all bus cycles and for a word operation it always assumes that the port is 32 bits wide at the beginning of the bus cycle. in figure 13- 18 and figure 13-19 and table 13-2 and table 13-3, the following operand conventions have been adopted: ? op0 is the most-significant byte of a word operand and op3 is the least-significant byte. ? the two bytes of a half-word operand are op0 (most-significant) and op1 or op2 (least-significant) and op3, depending on the address of the access. ? the single byte of a byte-length operand is op0, op1, op2, or op3, depending on the address of the access. note: although this is a 32-bit machine, only 26 of the bits are visible outside the chip. figure 13-18. internal operand representation op0 op1 op2 0 31 word half-word byte op0 op1 op2 op3 op0 op1 op2 op3 op3
external bus interface 13-26 mpc823e reference manual motorola external bus 13 interface figure 13-19 illustrates the device connections on the data bus. table 13-2 lists the bytes for read cycles required on the data bus. figure 13-19. interface to different port size devices table 13-2. data bus requirements for read cycles transfer size tsize [0:1] internal address 32-bit port size 16-bit port size 8-bit port size a30 a31 d0Cd7 d8Cd15 d16Cd23 d24Cd31 d0Cd7 d8Cd15 d0Cd7 byte 0 1 0 0 op0 op0 op0 0 1 0 1 op1 op1 op1 0 1 1 0 op2 op2 op2 0 1 1 1 op3 op3 op3 half-word 1 0 0 0 op0 op1 op0 op1 op0 1 0 1 0 op2 op3 op2 op3 op2 word 0 0 0 0 op0 op1 op2 op3 op0 op1 op0 note: denotes that a byte is not required during that read cycle. 32-bit port size op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 16-bit port size 8-bit port size d[0:7] d[8:15] d[16:23] d[24:31] interface output register
external bus interface motorola mpc823e reference manual 13-27 external bus 13 interface table 13-3 lists the patterns of the data transfer for write cycles when accesses are initiated by the mpc823e. 13.4.6 arbitration phase-related signals the external bus design provides for a single bus master, either the mpc823e or an external device. one or more of the external devices on the bus has the capability of becoming bus master for the external bus. bus arbitration may be handled either by an external central bus arbiter or by the internal on-chip arbiter. in the latter case, the system is optimized for one external bus master besides the mpc823e. the arbitration configuration (external or internal) is set at system reset. see section 15.6 external master support for more information. each bus master must have br , bg , and bb signals. the device that needs the bus asserts the br signal. the device then waits for the arbiter to assert the bg signal. in addition, the new master must look at the bb signal to ensure that no other master is driving the bus before it can assert bb and assume ownership of the bus. if the arbiter has taken the bg away from the master and the master wants to execute a new cycle, the master must rearbitrate before a new cycle can be initiated. the mpc823e, however, guarantees data coherency for burst accesses to a small port size. this means that the mpc823e will not release the bus until the transactions (atomic) complete. table 13-3. data bus contents for write cycles transfer size tsize [0:1] internal address external data bus pattern a30 a31 d0Cd7 d8Cd15 d16Cd23 d24Cd31 byte 0100 op0 0101 op1 op1 0110 op2 op2 0111 op3 op3 op3 half-word 1000 op0 op1 1010 op2 op3 op2 op3 word 0000 op0 op1 op2 op3 note: denotes that a byte is not required during that write cycle.
external bus interface 13-28 mpc823e reference manual motorola external bus 13 interface figure 13-20 illustrates the basic protocol for bus arbitration. for more information, see section 12.12.1.1 siu module configuration register . 13.4.6.1 bus request signal. the potential bus master asserts the br signal to request bus mastership. br must be negated once the bus is granted, the bus is not busy, and the new master can drive the bus. if more requests are pending, the master can keep asserting its bus request as long as needed. when configured for external central arbitration, the mpc823e drives this signal when it needs bus mastership. when the internal on-chip arbiter is used, this signal is an input to the internal arbiter and must be driven by the external bus master. figure 13-20. bus arbitration flowchart requesting device arbiter request the bus 1. assert br terminate arbitration 1. negate bg (may choose to 1. wait for bb to be 3. negate br keep it asserted to park bus master) operate as bus master 1. preform data transfer release bus mastership 1. negate bb acknowledge bus mastership negated 2. assert bb to become next master grant bus arbitration 1. assert bg
external bus interface motorola mpc823e reference manual 13-29 external bus 13 interface 13.4.6.2 bus grant signal. the bg signal is asserted by the arbiter to indicate that the bus is granted to the requesting device. the bg signal can be negated after br is negated. the current bus master may choose to keep bg asserted to park the bus and maintain ownership without rearbitrating until another master makes a request. this reduces arbitration time, which then improves performance. when configured for external central arbitration, the bg becomes an input signal to the mpc823e from the external arbiter. when the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master. 13.4.6.3 bus busy signal. the bb signal indicates that the current bus master is using the bus. new masters must not begin transferring until this signal is negated. the bus owner must not relinquish or negate this signal until its transfer is complete. to avoid contention on the bb signal, masters must three-state this signal when it gets a logical 1 value. this situation implies that the connection of an external pull-up resistor is needed to ensure that a master acquiring the bus recognizes that the bb signal is negated, regardless of how many cycles have passed since the previous master relinquished the bus. refer to figure 13-21 for more information. figure 13-21. basic bus busy connection external bus mpc823e slave 2 master ts bb
external bus interface 13-30 mpc823e reference manual motorola external bus 13 interface at system reset, the mpc823e can be configured to use the internal bus arbiter and it will be parked on the bus. the priority of the external device relative to the internal mpc823e bus masters is programmed in the siumcr, as described in section 12.12.1.1 siu module configuration register . if the external device requests the bus and the mpc823e does not need it or the external device has priority over the current internal bus master, the mpc823e grants the bus to the external device. figure 13-23 illustrates the internal finite state machine that implements the arbiter protocol. figure 13-22. bus arbitration timing diagram clkout br0 bg1 addr + attr bg0 br1 master 0 turns on and master 0 negates bb and turns off drives signals bb ts ta master 1 turns on and drives signals
external bus interface motorola mpc823e reference manual 13-31 external bus 13 interface 13.4.7 address transfer phase-related signals 13.4.7.1 transfer start signal. the ts signal indicates the beginning of a cycle initiated by the bus master. this signal must be asserted by a master only after ownership of the bus is granted by the arbitration protocol. this signal is only asserted for the first clock cycle of the transaction and is negated in the successive clock cycles. the master must three-state this signal when it relinquishes the bus to avoid contention between two or more masters in this signal. this configuration requires an external pull-up resistor to be connected to the ts signal. this will prevent a slave from responding to a bogus ts assertion. refer back to figure 13-21 for more information. figure 13-23. internal bus arbitration state machine idle bg = 1 bb = t.s ext owner bg = 0 ext master br = 0 ext master release bus mpc823e bus wait bg = 1 bb = t.s bb = t.s bb = 0 mpc823e owner bg = 1 bb = 0 bb = 1 bb = 1, br =1 br = 0 requests bus br = 1 the external device that has a higher priority than the current internal bus master requests the bus mpc823e internal master with higher priority than the external device requires the bus mpc823e needs mpc823e no longer the bus needs the bus mpc823e still needs the bus
external bus interface 13-32 mpc823e reference manual motorola external bus 13 interface 13.4.7.2 address bus. the 26-bit address bus consists of address bits 6C31 and bit 6 is most-significant. the bus is byte addressable, so each address can address one or more bytes. the address and its attributes are driven on the bus with the ts signal and stay valid until the bus master received a ta signal from the slave. to distinguish the individual byte, the slave device must observe the tsizx signals. 13.4.7.3 transfer attributes. the transfer attributes consist of the rd/wr , burst , tsizx, atx, sts , and bdip signals. these signals, except for the bdip , are available at the same time as the address bus. 13.4.7.3.1 read/write signal. when the rd/wr signal is high it indicates a read access and when it is low it indicates a write access. 13.4.7.3.2 burst signal. the burst signal and the address are driven by the bus master at the beginning of the bus cycle to indicate that the transfer is a burst transfer. the burst size is always 16 bytes. with a 32-bit port size, the burst includes 4 beats. when its port size is 16 bits and controlled by the internal memory controller, the burst includes 8 beats. when its port size is 8 bits and controlled by the internal memory controller, the burst includes 16 beats. the mpc823e bus supports critical data word first for burst. the order of the wraparound goes back to the critical word. for example, assuming data 2 is the critical word: ? case burst of four beats: data 2 ? data 3 ? data 0 ? data 1 ? case burst of eight beats: data 2 ? data 3 ? data 4 ? ......... ? data 7 ? data 0 ? data 1 note: although this is a 32-bit machine, only 26 of the bits are visible outside the chip.
external bus interface motorola mpc823e reference manual 13-33 external bus 13 interface 13.4.7.3.3 transfer size signal. the tsizx signals indicate the size of the requested data transfer and they can be used with the burst and a[30:31] signals to determine the byte lanes of the data bus that are involved in the transfer. for nonburst transfers, the tsizx signals specify the number of bytes starting from the byte location addressed by the a[30:31] signals. in burst transfers, the value of the tsizx signal is always 00. 13.4.7.3.4 address space attributes. the address space attributes consist of the address type (at[0:3]), program trace (ptr ), and reservation (rsv ) signals, which are all outputs that indicate one of 16 address types to which the address applies. these types are designated as either a normal/alternate master cycle, problem/privilege (user or supervisor), and instruction or data types. the address space signals are valid at the rising edge of the clock in which the sts signal is asserted. address space signals reflect the current status of the master originating the access, not necessarily the status in which the original access to this location has occurred. an example of this situation is when a copyback of a dirty line in the data cache occurs after the privilege state of the processor has been changed since the last access to the same line. functional usage of the atx, ptr , and rsv signals is for the reservation protocol described in section 13.4.10 storage reservation protocol . table 13-5 provides the space definition encoded by the sts , ts , atx, ptr , and rsv signals. show cycles are accesses to the cores internal bus devices. these accesses are driven externally for emulation, visibility, and debugging purposes. a show cycle can have one address phase and one data phase (or just an address phase for the instruction show cycles). the cycle can be a write or read access and the data for both the read and write accesses must be driven by the bus master. this is different than the normal bus read and write accesses. the address of the show cycle must be valid on the bus for one clock and the data of the show cycle must be valid on the bus for one clock. the data phase must not require a transfer acknowledge to terminate the bus-show cycle. in a burst show cycle only the first data beat will be shown externally. 13.4.7.3.5 special transfer start signal. the sts signal is driven by the mpc823e when it owns the external bus. it indicates the start of a transaction on the external bus or an internal transaction in show cycle mode. table 13-4. burst /tsize encoding burst tsizx transfer size 1 01 byte 1 10 half-word 111 x 1 00 word 0 00 burst (16 bytes)
external bus interface 13-34 mpc823e reference manual motorola external bus 13 interface table 13-5. address space definitions s ts ts at[0] at[1] at[2] at[3] ptr rsv definitions core/cpm problem state/ privilege state instruction/ data reservation/ program trace program trace reservation 1 x x x x x 1 1 no transfer or no first transaction of a transfer 0 x x x x x x x start of a transaction x 0 0 0 0 0 0 1 core, normal instruction, program trace, privilege state 1 1 1 core, normal instruction, privilege state 1 0 1 0 core, reservation data, privilege state 1 1 1 core, normal data, privilege state 1 0 0 0 1 core, normal instruction, program trace, problem state 1 1 1 core, normal instruction, problem state 1 0 1 0 core, reservation data, problem state 1 1 1 core, normal data, problem state 1 ch0 ch1 ch2 1 1 no core, normal, (ch indicates channel number)
external bus interface motorola mpc823e reference manual 13-35 external bus 13 interface x 1 0 0 0 0 0 1 core, show cycle address instruction, program trace, privilege state 1 1 1 core, show cycle address instruction, privilege state 1 0 1 0 core, reservation show cycle data, privilege state 1 1 1 core, show cycle data, privilege state 1 0 0 0 1 core, show cycle address instruction, program trace, problem state 1 1 1 core, show cycle address instruction, problem state 1 0 1 0 core, reservation show cycle data, problem state 1 1 1 core, show cycle data, problem state 1 ch0 ch1 ch2 1 1 no core, show cycle data (ch indicates channel number) table 13-5. address space definitions (continued) s ts ts at[0] at[1] at[2] at[3] ptr rsv definitions core/cpm problem state/ privilege state instruction/ data reservation/ program trace program trace reservation
external bus interface 13-36 mpc823e reference manual motorola external bus 13 interface 13.4.7.3.6 burst data in progress signal. the bdip signal is sent from the master to the slave to indicate that there is a data beat following the current data beat. the master uses this signal to give the slave advanced warning of the remaining data in the burst. by negating the bdip signal, you can terminate a burst cycle early. refer to section 13.4.2 single beat transfers and section 13.4.4 the burst mechanism for more information. 13.4.8 data transfer phase-related signals 13.4.8.1 data signal. the d[0:31] signals are driven by the mpc823e when it owns the external bus and has initiated a write transaction to a slave device. during a read transaction the d[0:31] signals are driven by the slave device. see table 13-2 for byte lane assignments. 13.4.9 termination phase-related signals 13.4.9.1 transfer acknowledge signal. the ta signal indicates the normal completion of a bus transfer. during burst cycles, the slave asserts this signal with every data beat returned or accepted. this signal must be pulled up to v dd with a pull-up resistor. 13.4.9.2 burst inhibit signal. the bi signal is sent from the slave to the master to indicate that the addressed device does not have burst capability. if this signal is asserted or equal to 0, the master must transfer in multiple cycles and increment the address for the slave to complete the burst transfer. for a system that does not use the burst mode at all, this signal can be permanently tied low. this signal must be pulled up to v dd with a pull-up resistor. 13.4.9.3 transfer error acknowledge signal. the tea signal terminates the bus cycle under bus error conditions. the current bus cycle must be aborted. this signal must override any other cycle termination signals, such as the ta signal. this signal must be pulled up to v dd with a pull-up resistor.
external bus interface motorola mpc823e reference manual 13-37 external bus 13 interface 13.4.9.4 protocol for termination signals. the transfer protocol was defined to avoid electrical contention on signals that can be driven by various sources. to do that, a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own. the slave must disconnect from signals immediately after it has acknowledged the cycle and no later than the termination of the next address phase cycle. this indicates that the termination signals must be connected to power through a pull-up resistor to avoid a situation in which a master samples an undefined value in any of these signals when no real slave is addressed. see figure 13-24 and figure 13-25 for more information. figure 13-24. termination signals protocol basic connection figure 13-25. termination signals protocol timing diagram external bus mpc823e slave 2 slave 1 acknowledge/termination signals (ta , tea , bi ) clkout a[6:31] ts ta ,bi ,tea rd/wr tsiz[0:1] slave 1 slave 2 slave 1 allowed to drive slave 1 negates acknowledge signals and turns off acknowledge signals slave 2 allowed to drive slave 2 negates acknowledge signals and turns off acknowledge signals data
external bus interface 13-38 mpc823e reference manual motorola external bus 13 interface 13.4.10 storage reservation protocol the mpc823e storage reservation protocol supports multilevel bus structure. for each local bus, storage reservation is handled by the local reservation logic. the protocol tries to optimize reservation cancellation so that a powerpc processor is notified of storage reservation loss on a remote bus only when it has issued a stwcx cycle to that address. in other words, the reservation loss indication comes as part of the stwcx cycle. this method avoids the need to have fast storage reservation loss indication signals routed from every remote bus to every powerpc master. the storage reservation protocol makes the following assumptions: ? each processor has, at most, one reservation flag ? lwarx sets the reservation flag ? lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and again sets the reservation flag ? stwcx by the same processor clears the reservation flag ? a store by the same processor does not clear the reservation flag ? some other processor (or other mechanism) store to the same address as an existing reservation clears the reservation flag ? if the storage reservation is lost it is guaranteed that stwcx will not modify the storage
external bus interface motorola mpc823e reference manual 13-39 external bus 13 interface the reservation protocol for a single-level (local) bus is illustrated in figure 13-26. it assumes that external logic on the bus performs the following functions: ? snoops accesses to all local bus slaves ? holds one reservation for each local master capable of storage reservations ? sets the reservation when that master issues a load and reserve request ? clears the reservation when some other master issues a store to the reservation address figure 13-26. reservation on local bus s r reservation logic external bus interface lwarx q enable external stwcx access e-bus mpc823e master bus a[6:31] clkout at[0:3], rsv ,r/w ,ts
external bus interface 13-40 mpc823e reference manual motorola external bus 13 interface the local bus interface block implements a reservation flag for the local bus master. the reservation flag is set by the local bus interface when a load with reservation is issued by the local bus master and the reservation address is located on the remote bus. the flag is reset when an alternative master on the remote bus accesses the same location in a write cycle. if the mpc823e begins a memory cycle to the previously reserved address (located in the remote bus) as a result of a stwcx instruction, one of the following conditions can occur: ? if the reservation flag is set, the local bus interface acknowledges the cycle in a normal way. ? if the reservation flag is reset, the local bus interface must assert kr . however, the local bus interface must either not perform the remote bus write access or abort it if the
external bus interface motorola mpc823e reference manual 13-41 external bus 13 interface remote bus supports aborted cycles. the failure of the stwcx instruction is reported to the core. 13.4.11 exception control cycles the mpc823e bus architecture requires the ta signal to be asserted from an external device to indicate that the bus cycle is complete. ta is not asserted when one of the following conditions occur: ? the external device does not respond ? other application-dependent errors occur figure 13-27. reservation on multilevel bus hierarchy s r local bus interface bus interface q kr mpc823e external bus mpc823e at[0:3], rsv , r/w , ts a[6:31] remote bus master in the remote bus writes to the reserved location external device
external bus interface 13-42 mpc823e reference manual motorola external bus 13 interface the external circuitry can provide tea when no device responds by asserting ta within an appropriate period of time after the mpc823e initiates the bus cycle. this allows the cycle to terminate and the processor to enter exception processing for the error condition. to properly control termination of a bus cycle for a bus error, tea must be asserted simultaneously or before ta is asserted. tea must be negated before the second rising edge after it was sample-asserted to avoid detecting an error for the next initiated bus cycle. tea is an open-drain pin that allows the wire-or of any different error generation sources. 13.4.11.1 retry signal. when an external device asserts the retry signal during a bus cycle, the mpc823e enters a sequence in which it terminates the current transaction, relinquishes ownership of the bus, and retries the cycle using the same address, address attributes, and data. figure 13-28 illustrates the behavior of the mpc823e when the retry signal is detected as a termination of a transfer. the figure illustrates that when the internal arbiter is enabled, the mpc823e negates the bb signal and asserts the bg signal in the clock cycle following retry detection. this allows any external master to gain bus ownership. in the next clock cycle, a normal arbitration procedure may occur. the figure also shows that the external master did not use the bus, so the mpc823e initiates a new transfer with the same address and attributes as before. in figure 13-29 the same situation is illustrated to show that the mpc823e is working with an external arbiter. in the clock cycle after the cpu recognizes that the retry signal is asserted, the br and bb signals are negated. one clock cycle later, the normal arbitration procedure may occur. this input signal requires a pull-up resistor.
external bus interface motorola mpc823e reference manual 13-43 external bus 13 interface figure 13-28. retry transfer timingCinternal arbiter clkout a[6:31] ts br bg (output) bb data ta rd/wr burst tsiz[0:1] retry aa allow external master to gain the bus
external bus interface 13-44 mpc823e reference manual motorola external bus 13 interface figure 13-29. retry transfer timingCexternal arbiter clkout a[6:31] ts br (output) bg bb data ta rd/wr burst tsiz[0:1] retry aa allow external master to gain the bus
external bus interface motorola mpc823e reference manual 13-45 external bus 13 interface when a burst access is initiated by the mpc823e, the bus interface only recognizes the retry assertion as a retry termination if it detects it before the first data beat is acknowledged by the slave device. when the retry signal is asserted as a termination signal on the second or third data beat of the access, the mpc823e recognizes it as a transfer error acknowledgement. if a non burst access to a small port size device is initiated by the mpc823e, the transfer size of the access is bigger than the slave port size, and the first transfer of this access is normally acknowledged by the assertion of ta , the mpc823e initiates the following single beat transfers to complete the access and recognize the retry assertion as a transfer error acknowledge. figure 13-30. retry on burst cycle clkout a[6:31] ts br bg (output) bb data ta rd/wr burst tsiz[0:1] retry aa allow external master to gain the bus bi if asserted will cause transfer error
external bus interface 13-46 mpc823e reference manual motorola external bus 13 interface in reference to figure 13-30, if the bi signal is asserted at the first beat of a burst, then the remaining beats of the 16-byte transfer retry are recognized as a transfer error acknowledge. table 13-6 summarizes how the mpc823e recognizes the termination signals provided by the slave device that the initiated transfer addressed. table 13-6. termination signal protocol tea ta retry /kr action asserted x x transfer error termination negated asserted x normal transfer termination negated negated asserted retry transfer termination / kill reservation
motorola mpc823e reference manual 14-1 endian modes 14 section 14 endian modes this section will discuss how the mpc823e supports three system endian configurations: ? little-endian system ? big-endian system ? powerpc ? little-endian system a general description of the different endian modes can be found in the powerpc microprocessor family: the programming environments (mpcfpe/ad) manual that is available from motorola. throughout the mpc823e reference manual , the term system refers to the devices that reside on the mpc823e bus. the mpc823e core operates in the big-endian mode of a big-endian system and in the powerpc little-endian mode of two other configurations. table 14-2 contains possible programming configurations. table 14-1. little-endian effective address modification for individual aligned scalar data length (bytes) address modification 1 xor with 0b111 2 xor with 0b110 4 xor with 0b100 8 (no change) note: there are no 8-byte scalars in the mpc823e . table 14-2. endian mode programming for core data structures mode msr le (and msr ile ) dc_csr les big-endian mode 0 0 little-endian mode 0 1 powerpc little-endian mode 1 0 reserved 1 1
endian modes 14-2 mpc823e reference manual motorola endian modes 14 the hardware operations that are used to support the different endian modes are: ? address munging in the core is controlled by the msr le bit. refer to the powerpc microprocessor family: the programming environments for 32-bit microprocessors manual for more information. ? the mpc823e internal bus signal is driven by the master that informs the system interface unit to swap and perform address demunging or leave the current access as it is. table 10-1 defines the dc_csr les bit for core and cache accesses. ? address munging and data bytes format in the communication processor module (cpm) that is controlled by the bo field of the function code register. figure 14-1. general mpc823e system diagram note: some peripheral component interconnect (pci) bridge devices cannot be used in little-endian mode. core system communication internal i / o devices system memory memory u-bus e-bus pci interface pci devices mpc823e processor module interface unit
endian modes motorola mpc823e reference manual 14-3 endian modes 14 14.1 little-endian features the following is a list of the little-endian systems main features: ? system memory organization and e-bus format are little-endian ? u-bus data, instruction and data caches, and internal memory format are big-endian ? data access constraints that follow the powerpc little-endian rules ? same byte order between the media and system memory ? for core accesses, swap and address demunging are performed by the system interface unit on the u-bus to the system path ? the cores load/store unit swapper uses munged addresses to put the data on the right byte lanes when half-word or byte accesses are performed ? the communication processor module performs data swapping according to information in the buffer descriptors the following tables describe how to handle the little-endian program or data in the little-endian system that is built around the mpc823e for various port sizes. table 14-3. little-endian program/data path between the register and 32-bit memory fetch/ load store type little- endian address u-bus and caches address external bus address data in the register u-bus and caches format e-bus format little-endian program/data 0123012301233210 word 0 0 0 11 12 13 14 11 12 13 14 14 13 12 11 11 12 13 14 half-word 0 2 0 21 22 21 22 22 21 21 22 half-word 2 0 2 31 32 31 32 32 31 31 32 byte 0 3 0 a a a a byte 1 2 1 b b b b byte 2 1 2 c c c c byte 3 0 3 d d d d
endian modes 14-4 mpc823e reference manual motorola endian modes 14 table 14-4. little-endian program/data path between the register and 16-bit memory fetch/ load store type little- endian address u-bus and caches address external bus address data in the register u-bus and caches format e-bus format little-endian program/data 0123012301233210 word 0 0 0 11 12 13 14 11 12 13 14 14 13 13 14 2 1211 1112 half-word 0 2 0 21 22 21 22 22 21 21 22 half-word 2 0 2 31 32 31 32 32 31 31 32 byte 0 3 0 a a a a byte 1 2 1 b b b b byte 2 1 2 c c c c byte 3 0 3 d d d d table 14-5. little-endian program/data path between the register and 8-bit memory fetch/ load store type little- endian address u-bus and caches address external bus address data in the register u-bus and caches format e-bus format little-endian program/data 0123012301233210 word 0 0 0 11 12 13 14 11 12 13 14 14 14 11313 21212 31111 half-word 0 2 0 21 22 21 22 22 22 12121 half-word 2 0 2 31 32 31 32 32 32 33131 byte 0 3 0 a a a a byte 1 2 1 b b b b byte 2 1 2 c c c c byte 3 0 3 d d d d
endian modes motorola mpc823e reference manual 14-5 endian modes 14 14.2 big-endian system features the following is a list of the big-endian systems main features: ? caches, u-bus, e-bus, system memory, and i/o organization format is big-endian ? same byte order between the media and system memory ? communication processor module writes and reads big-endian u-bus data ? pci bridge operates in big-endian mode as needed 14.3 powerpc little-endian system features the following is a list of the powerpc little-endian systems main features: ? caches, u-bus, e-bus, system memory, and e-bus attached i/o organization format is big-endian ? pci bus format is little-endian ? data access constraints that follow the powerpc little-endian rules ? address munging in the core and communication processor module follows the guidelines in table 14-1 ? the pci bridge operates in little-endian mode as needed. swap and address demunging is performed by the pci bridge on the pci i/o to the system memory path. ? the stream hit mechanisms of the instruction and data caches operate less efficiently when address munging is performed on cache accesses. some performance degradation is expected when working in this mode. 14.4 setting the endian mode of operation the endian mode must be set early in the reset routine and remain unchanged for the duration of system operation. the mpc823e core is in big-endian mode after reset. to switch between the different endian modes of operation, the core must run in serialized mode and the caches must be disabled. it is not recommended that you switch back and forth between modes. to transfer the system to little-endian mode, the dc_csr les bit must be set by writing 0b0101 to the cmd field of the dc_csr with an mtspr instruction on an even word boundary (a29=0). further instructions must be little-endian. however, there are some idiosyncrasies with little-endian mode itself. to transfer the system to the powerpc little-endian mode, the msr le and msr ile bits must be changed with an mtmsr instruction on an odd word boundary (a29=1). the instruction that is executed next will be fetched from this address plus 8. if the instruction resides on an even word boundary (a29=0), then this instruction will be executed twice because of address munging. the instruction to transfer the system back to the big-endian mode must reside on an even word boundary (a29=0). the next instruction will be fetched from this address plus 12. the bo field of the function code registers (fcrs) in the communication processor module must be set to the required endian format for the buffer descriptor.
motorola mpc823e reference manual 15-1 memory controller 15 section 15 memory controller the memory controller is responsible for controlling a maximum of eight memory banks shared between a general-purpose chip-select machine and a pair of sophisticated user-programmable machines. it supports a glueless interface to sram, eprom, flash eprom, regular dram devices, self-refresh drams, extended data output dram devices, synchronous drams, and other peripherals. this flexible memory controller allows you to implement memory systems with very specific timing requirements. it supports external address multiplexing, periodic timers, and timing generation for row address and column address strobes to allow for a glueless interface to dram devices. the periodic timers allow refresh cycles to be initiated while the address muxing provides row and column addresses. you can define different timing patterns for the control signals that govern a memory device. these patterns define how the external control signals behave in read-access, write-access, burst read-access, or burst write-access requests. you decide how the external control signals toggle when the periodic timers reach the maximum programmed value for refresh operation. 15.1 features the following is a list of the memory controllers main features: ? eight memory banks o 32-bit address decode with mask o various block sizes (32k to 4g) o byte parity generation/checking o write-protection capability o address types match qualifying memory bank accesses for internal masters o timing pattern machine selected according to the type of memory device accessed o support for external master access to memory banks o synchronous and asynchronous external masters support ? general-purpose chip-select machine o compatible with sram, eprom, feprom, and peripherals o global (boot) chip-select available at system reset o boot chip-select support for 8-, 16-, and 32-bit devices o two clock accesses to external device o four byte write enable (we [0:3]) signals o output enable (oe ) signal
memory controller 15-2 mpc823e reference manual motorola memory controller 15 ? two user-programmable machines o ram-based machine controls the timing of the external signals with a granularity of one quarter of a system clock period o user-specified patterns run when a single read access, single write access, burst read access or burst write access is requested by an internal or external synchronous master o user-specified patterns run when a single read access or single write access is requested by an external asynchronous master o upm periodic timer initiates an automatic pattern when it expires (refresh) o user-specified patterns run under software control o each upm can be defined to support dram devices with depths of 64k,128k, 256k, 512k, 1m, 2m, 4m, 8m, 16m, 32m, 64m, 128m, and 256m o four byte-select lines for each upm o six external general-purpose lines controlled by each upm o supports 8-, 16-, and 32-bit dram port sizes o glueless interface to one bank of dram (only external buffers are required for additional simm banks) o page mode support for successive transfers within a burst for all on-chip and external synchronous masters o internal address multiplexing for all on-chip bus masters supporting 64k, 128k, 256k, 512k, 1m, 2m, 4m, 8m, 16m, 32m, 64m, 128m, 256m page banks o glueless interface to edo, self refresh, and synchronous dram devices a block diagram of the memory controller is illustrated in figure 15-1.
memory controller motorola mpc823e reference manual 15-3 memory controller 15 figure 15-1. memory controller block diagram (single upm) option register (or) base register (br) option register (or) base register (br) option register (or) base register (br) option register (or) option register (or) base register (br) option register (or) base register (br) option register (or) base register (br) option register (or) general-purpose chip-select machine wait state counter attributes scy[0:3] user- programmable machine memory periodic timer memory command register (mcr) memory data register (mdr) memory disable timer machine mode register (m x mr) turn on disable timer enable upm access request upm access acknowledge upm access request upm command burst, rd/wr address latch multiplexer and incrementor na and amx fields parity logic parity error wp error dp[0:3] d[0:31] (command) upm arbiter done expired load cs [0:7] we [0:3] oe cs [0:7] bs_ x[0:3] gpl x [0:5] ta dlt3 (internal) upwaitx base register (br) base register (br) address[0:16], at[0:2] (a or b) write-protect logic wp rd/wr memory periodic timer prescale register (mptpr) memory status register (mstat) memory address register (mar)
memory controller 15-4 mpc823e reference manual motorola memory controller 15 15.2 architecture the memory controller consists of three basic machines: ? general-purpose chip-select machine ? user-programmable machine a ? user-programmable machine b as illustrated in figure 15-2, each bank can be assigned to any one of these machines via the ms field in the base register. when a memory address matches the ba field of the base register, the corresponding machine takes ownership of the external signals that control access until the cycle terminates. the general-purpose chip-select machine (gpcm) provides a glueless interface to eprom, sram, flash eprom, and other peripherals. general-purpose chip-select signals are available on cs [0:7]. cs0 also functions as the boot chip-select signal that allows the cpu to access the boot eprom from reset. each chip-select allows a maximum of 30 wait states. figure 15-2. memory controller machine selection user-programmable user-programmable general-purpose bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 ms field ms field ms field ms field ms field ms field ms field ms field machine a machine b machine chip-select
memory controller motorola mpc823e reference manual 15-5 memory controller 15 some features are common to all eight memory banks. the full 32-bit decode is available internally, even if all 32 address bits are not visible outside the mpc823e. for external master transactions, the memory controller extends the 26-bit external address line to 32 bits and the six most-significant bits are zero. the variable block size of each memory bank can be between 32k and 64m for a total memory capacity of 512m. parity can be generated and checked for any memory bank and each memory bank can be selected for read-only or read/write operation. for system protection purposes, you can use certain address type codes to cause the memory controller to restrict access to a memory bank. for additional flexibility, address type comparisons provide you with a mask option. the memory controller functionality helps you design mpc823e-based systems with little or no glue logic required. in figure 15-3, cs0 is used as the 16-bit boot eprom with the ms field of the base register 0 configured to select the gpcm. cs1 is used as the ras signal for 32-bit dram with the ms field of base register 1 configured to select upma. the bs_a signals are used as casx signals on the dram. mpc823e figure 15-3. simple system configuration ce oe w eprom address we data dram address ras cas [0:3] data parity cs1 we [0:1] rd/wr gpl1 /oe dp[0:3] address data cs0 bs_a [0:3] gpcm upma
memory controller 15-6 mpc823e reference manual motorola memory controller 15 the two user-programmable machines (upma and upmb) in the memory controller provide a flexible interface to many types of memory devices. each upm can control the address multiplexing necessary to access dram devices, the timing of the bs signals, and the timing of the gpl x signals. each memory bank can be assigned to either upm. there are a total of eight csx signals that can be split between the two upms. each user-programmable machine is a ram-based machine controlled by software. the software toggles the memory controller external signals when an external single word read/write access or an external burst read/write access is initiated by an internal or external master. the upm also controls address multiplexing, address increment, and transfer acknowledge assertion for a specific memory access. the upm can be programmed to run a specific signal pattern for a certain duration of clock cycles. at every clock cycle, the logical value of the external signals specified in the ram array is output on the corresponding upm pins. when a new access to external memory is requested by any of the internal or external masters, the address of the transfer and the address type is compared to each one of the valid banks defined in the memory controller. notice that all of the a[0:16] and at[0:2] signals are maskable. when an address match is found in one of the memory bank chip-select ranges, the corresponding ms field in the base register defines the machine that handles the memory access. see figure 15-4 for details. the memory controller provides four parity (dp[0:3]) signals, one for each data byte lane on the mpc823e system bus. the parity on the bus is only checked if the memory bank accessed in the current transaction has parity enabled. parity checking/generation can be enabled for a specific memory bank in the base register. the type of parity is defined in the system interface unit module configuration register, which is explained in section 12.12.1.1 siu module configuration register . also, system protection is provided by defining each memory bank as read-only or read/write.
memory controller motorola mpc823e reference manual 15-7 memory controller 15 15.3 register model the status bits for each one of the memory banks are in the memory controller status (mstat) register, which is used by the entire memory controller. each of the eight memory banks has a base register (brx) and an option register (orx). the mstat reports write- protect violations that occur and parity errors for every bank. the base register contains a v bit that indicates when the information for the chip-select is valid. each base register defines the starting address of its memory bank and each option register defines the attributes for its memory bank. the option registers also define the initial address multiplexing for a memory cycle controlled by a upm. the machine a mode register (mamr) and machine b mode register (mbmr) define most of the global features for the user-programmable machines. the memory command register (mcr) and memory data register (mdr) are used to initialize the upms ram array. the mad field of the memory command register specifies the location in the ram array to be executed as defined by the mcr. the memory address register (mar) allows a specific address pattern to be output onto the a[6:31] signals. the memory periodic timer prescaler register (mptpr) defines the divisor of the brgclk used as the memory periodic timer input clock. figure 15-4. basic memory controller operation signals timing generator internal/external memory access request programmable machine a general-purpose chip-select signals timing generator ms address comparator bank select mux external signals address, user- programmable machine b user- machine field address type
memory controller 15-8 mpc823e reference manual motorola memory controller 15 the memory controller registers are used by the general-purpose chip-select machine and the user-programmable machines as specified in table 15-1. see section 15.3.1 register descriptions for specific register information. the memory controller supports multiple port sizes. predefined 8-bit ports can be accessed as odd or even bytes, predefined 16-bit ports can be accessed as odd or even bytes and even half-words on data bus bits 0 through 15. predefined 32-bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words, or words on word boundaries. the port size is specified by the ps field in the base register. the wp bit of the base register restricts write accesses to a certain address range. if you try to write in this area, a write-protect violation occurs and the wper bit in the memory status register is set. each time an internal or external bus cycle access is requested, the address and its corresponding address type are compared to each one of the banks. if a match is found on one of the memory controller banks, the attributes defined for that bank in the base and option registers are used to control the memory access. however, if multiple matches are found, the lowest numbered matched bank handles the memory access. it must be noted that when external masters access memory controller-managed slaves on the bus, the internal at signals to the memory controller are forced to 100. parity can be configured for any bank. it is generated and checked on a per-byte basis using the dp[0:3] signals for the bank if the pare bit is set in the base register. the opar bit in the siumcr (described in section 12.12.1.1 siu module configuration register ) determines the type of parity. any parity error causes the associated per bit in the memory status register to be set. it also asserts the tea signal and sets the corresponding dpb bit in the tesr, which is described in section 12.12.1.4 transfer error status register . the memory controller asserts an internal transfer error signal when a parity error occurs (if enabled). table 15-1. memory controller register usage register used by the gpcm used by a upm base register bank 0-7 register (brx) ?? option register bank 0-7 register (orx) ?? memory status register (mstat) ?? memory command register (mcr) ? machine a mode register (mamr) ? machine b mode register (mbmr) ? memory data register (mdr) ? memory address register (mar) ? memory periodic timer prescaler register (mptpr) ?
memory controller motorola mpc823e reference manual 15-9 memory controller 15 15.3.1 register descriptions 15.3.1.1 base registers. the base registers (br0-7) contain the base address and address types that are used by the memory controller to compare the address bus with the current address accessed. it also includes a memory attribute and selects the machine for memory operation handling. after reset, br0 is referred to as the boot br0 and it has a special functionality until the first write to or0. boot br0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ba reset 0 r/w r/w addr (immr & 0xffff0000) + 0x 100 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ba at ps pare wp ms reserved v reset 00 * 00 0 0 * r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x 102 * this value depends on the value of the hard reset configuration word. br x bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ba reset 0 r/w r/w addr (immr & 0xffff0000) + 0x100 (br0), 0x 108 (br1), 0x 110, (br2), 0x 118 (br3), 0x 120 (br4), 0x 128 (br5), 0x 130 (br6), 0x 138 (br7) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ba at ps pare wp ms reserved v reset 0 0 0000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x102 (br0), 0x 10a (br1), 0x 112, (br2), 0x 11a (br3), 0x 122 (br4), 0x 12a (br5), 0x 132 (br6), 0x 13a (br7)
memory controller 15-10 mpc823e reference manual motorola memory controller 15 babase address this field, the upper 17 bits of each base address register, and the at field are compared to the address on the address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. these bits are used in conjunction with the am field of the option register. ataddress type this field can be used to limit accesses to the memory bank to a certain address space type. these bits are used in conjunction with the atm field of the option register. psport size this field specifies the port size of the memory region. after system reset, the value of this bit in br0 depends on the bps field value in the hard reset configuration word, which is described in section 4.3.1.1 hard reset configuration word . 00 = 32-bit port size. 01 = 8-bit port size. 10 = 16-bit port size. 11 = reserved. pareparity enable this bit is used to enable parity checking on this bank. 0 = parity checking is disabled. 1 = parity checking is enabled. wpwrite-protect this bit may restrict write accesses within the address range of a base register. if you try to write to the range of addresses specified in a base address register that has this bit set, the bus monitor logic asserts the tea signal which then terminates the cycle. 0 = both read and write accesses are allowed. 1 = only read accesses are allowed. the csx and ta signals are not asserted by the memory controller on write cycles to this memory bank. the wper bit is set in the mstat register if you try to write to this memory bank. msmachine select this field specifies the machine that is selected for memory operations handling. 00 = gpcm. 01 = reserved. 10 = upma. 11 = upmb.
memory controller motorola mpc823e reference manual 15-11 memory controller 15 bits 26C30reserved these bits are reserved and must be set to 0. vvalid this bit indicates that the contents of the base and option registers are valid. the csx signal does not assert until this bit is set. an access to a region that does not have this bit set can cause a bus monitor timeout. after a system reset, the value of this bit in br0 depends on the bdis bit value in the hard reset configuration word, which is described in section 4.3.1.1 hard reset configuration word . 0 = this bank is invalid. 1 = this bank is valid. 15.3.1.2 option registers. the option registers (or0-7) contain the address mask and address type mask bit for address bus comparison. it also includes the cs general field and all the gpcm parameters. after reset, or0 is referred to as the boot or0 and it has a special functionality until the first write to or0. boot or0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field am reset 0 r/w r addr (immr & 0x ffff0000) + 0x 104 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field am atm csnt/ sam acs/g5la,g5ls bih scy seta trlx ehtr res reset 0 0 1 11 1 1 0100 r/w r r r r r r rrrr addr (immr & 0x ffff0000) + 0x 106
memory controller 15-12 mpc823e reference manual motorola memory controller 15 amaddress mask this read/write field provides masking on any corresponding bits in the associated base register. by masking the address bits independently, external devices of different size address ranges can be used. any cleared bit masks the corresponding address bit and any set bit causes the corresponding address bit to be used in address pin comparison. the am field can be set or cleared in any order in the field, thus allowing a resource to reside in more than one area of the address map. atmaddress type mask this field masks certain bits in an address type, thus allowing more than one address space type to be assigned to a chip-select. any set bit causes the corresponding address type code bits to be used as part of the address comparison. any cleared bit masks the corresponding address type code bit. the atm field must be cleared so that address type codes are ignored as part of the address comparison. csntchip-select negation time/samstart address multiplex this bit is used for the gpcm and the sam bit is used for the upm. the csnt bit, in conjunction with acs and trlx, is used to control negation of the csx and wex signals during an external memory write access handled by the general-purpose chip-select machine. this function provides extended address/data hold time for slower memories and peripherals. see table 15-2 (page 15-28) for more information. the sam bit determines the address output on the first cycle of an external memory access. 0 = address pins reflect the address requested by the internal master. 1 = address pins reflect the address requested by the internal master multiplexed according to the ama field (if upma is selected to control the memory access) or the amb field (if upmb is selected). or x bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field am reset 0 r/w r/w addr (immr & 0x ffff0000) + 0x 104 (or0), 0x 10c (or1), 0x 114 (or2), 0x 11c (or3), 0x 124 (or4), 0x 12c (or5), 0x 134 (or6), 0x 13c (or7) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field am atm csnt/ sam acs/g5la,g5ls bih scy seta trlx ehtr res reset 0 0 0 0 0 0 0000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0x ffff0000) + 0x 106 (or0), 0x 10e (or1), 0x 116 (or2), 0x 11e (or3), 0x 126 (or4), 0x 12e (or5), 0x 136 (or6), 0x 13e (or7) note: the reset value of or0 has predefined values as shown in the boot or0 register table.
memory controller motorola mpc823e reference manual 15-13 memory controller 15 acsaddress to chip-select setup/g5la this field is used for the gpcm and the g5la and g5ls fields are used for the upm. this field controls csx signal assertion in relation to address lines valid. 00 = cs x is output at the same time as the address lines. 01 = reserved. 10 = cs x is output a quarter of a clock later than the address lines. 11 = cs x is output half a clock later than the address lines. g5lsgeneral-purpose line 5 a this field determines how the internal timing generator (gpl5 ) signal is output when the memory access is handled by the upma or upmb. g5la (only valid for upmb): 0 = output the internal gpl5 signal on the gpl_b5 pin. 1 = output the internal gpl5 signal on the gpl_a5 pin. g5ls (valid for upma or upmb): 0 = the gpl5 signal is driven low on the falling edge of gclk1 during the first clock cycle of a read or write memory access. 1 = the gpl5 signal is driven high on the falling edge of gclk1 during the first clock cycle of a read or write memory access. bihburst inhibit this bit determines whether or not this memory bank supports burst accesses. when a burst does not occur, the memory controller drives the bi signal active when accessing this memory region. if the machine selected to handle this access is the gpcm, this bit must be set to 1. 0 = the bi signal is negated. the bank supports burst accesses. 1 = the bi signal is asserted. the bank does not support burst accesses. scyselect cycle length (gpcm only) this field determines the number of wait states inserted in the cycle when the general-purpose chip-select machine handles the external memory access. it is one of the parameters that control the cycles length. the total cycle length is controlled by this parameter and the trlx field. refer to table 15-2 (page 15-28) for the total number of cycles.
memory controller 15-14 mpc823e reference manual motorola memory controller 15 if you want to use an external ta response (seta bit = 1), then these bits are not used. 0000 = 0 clock cycle wait state. 0001 = 1 clock cycle wait state. 0010 = 2 clock cycle wait states. 0011 = 3 clock cycle wait states. 0100 = 4 clock cycle wait states. 0101 = 5 clock cycle wait states. 0110 = 6 clock cycle wait states. 0111 = 7 clock cycle wait states. 1000 = 8 clock cycle wait states. 1001 = 9 clock cycle wait states. 1010 = 10 clock cycle wait states. 1011 = 11 clock cycle wait states. 1100 = 12 clock cycle wait states. 1101 = 13 clock cycle wait states. 1110 = 14 clock cycle wait states. 1111 = 15 clock cycle wait states. setaselect external transfer acknowledge (gpcm only) this bit indicates when the ta signal is externally generated once the gpcm is selected to handle the memory access that was initiated to this memory region. regardless of other setup parameters for the gpcm, if seta = 1, then all control signals of the memory controller are negated after the externally generated ta signal is recognized. 0 = internal or external transfer acknowledge can acknowledge this memory access, whichever comes first. 1 = transfer acknowledge must be provided by external logic. trlxtiming relaxed (gpcm only) when this bit is set, it extends the timing of the signals controlling the memory devices once the gpcm is selected to handle the memory access that was initiated to this memory region. refer to table 15-2 (page 15-28) for more information. 0 = timing is defined by the gpcm. 1 = relaxed timing is defined by the gpcm. note: regardless of other gpcm setup parameters, if the seta bit equals one, then all memory controller signals are negated after the externally generated ta signal is recognized.
memory controller motorola mpc823e reference manual 15-15 memory controller 15 ehtrextended hold time on read when this bit is set, it adds one clock cycle after a read from the current bank and any cpu write or read to a different bank. 0 = timing is defined by the memory controller. 1 = extended hold time is defined on the current read access. bit 31reserved this bit is reserved and must be set to 0. 15.3.1.3 memory status register. the memory status (mstat) register reports parity and write-protect errors encountered during an external bus access initiated by the memory controller. to clear a specific bit, write a one to it (writing zero has no effect). per0parity error bank 0 when this bit is set it indicates that a parity error was detected during a bank 0 read cycle initiated by the memory controller. per1parity error bank 1 when this bit is set it indicates that a parity error was detected during a bank 1 read cycle initiated by the memory controller. per2parity error bank 2 when this bit is set it indicates that a parity error was detected during a bank 2 read cycle initiated by the memory controller. per3parity error bank 3 when this bit is set it indicates that a parity error was detected during a bank 3 read cycle initiated by the memory controller. per4parity error bank 4 when this bit is set it indicates that a parity error was detected during a bank 4 read cycle initiated by the memory controller. per5parity error bank 5 when this bit is set it indicates that a parity error was detected during a bank 5 read cycle initiated by the memory controller. mstat bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field per0 per1 per2 per3 per4 per5 per6 per7 wper reserved reset 000000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x178
memory controller 15-16 mpc823e reference manual motorola memory controller 15 per6parity error bank 6 when this bit is set it indicates that a parity error was detected during a bank 6 read cycle initiated by the memory controller. per7parity error bank 7 when this bit is set it indicates that a parity error was detected during a bank 7 read cycle initiated by the memory controller. wperwrite-protection error this bit is set when a write-protect error has occurred on a write cycle to a write-protected bank. the write-protect error is also stored in the transfer error status register of the system interface unit. see section 12.12.1.4 transfer error status register for more information. if the bus monitor is enabled, then tea is asserted. the tea signal will generate a machine check exception if it occurs between a ts and ta signal. when a ta is asserted before a write-protection error is detected, the tea that occurs will not generate a machine check exception. refer to section 12.4 the bus monitor for more information. bits 9C15reserved these bits are reserved and must be set to 0. note: if the bus monitor is disabled and the write-protect error occurs, tea assertion will not occur. see section 12.12.1.4 transfer error status register for more information.
memory controller motorola mpc823e reference manual 15-17 memory controller 15 15.3.1.4 memory command register. the memory command register (mcr) allows you to issue commands to stimulate upm routine execution. this capability enables the cpu to perform special memory operations in addition to the standard read/write and periodic timer service operations. opcommand opcode this field defines the operation to be executed by the user-programmable machine that is specified in the um field. 00 = writes the contents of the memory data register into the ram location indexed by the mad field. (write command) 01 = reads the contents of the ram location indexed by the mad field and stores it in the memory data register. (read command) 10 = executes the ram word in the ram array that services one of the eight memory banks specified in the mb field. the executed ram word is referenced by the mad field. if the executed ram word has the last bit set, it will be the last ram word executed. (run command) 11 = reserved. bits 2C7reserved these bits are reserved and must be set to 0. umuser machine this bit selects the user-programmable machine for this command. 0 = upma. 1 = upmb. bits 9C15reserved these bits are reserved and must be set to 0. mcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field op reserved um reserved reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x168 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field mb res mclf reserved mad reset 00 0 0 0 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x16a
memory controller 15-18 mpc823e reference manual motorola memory controller 15 mbmemory bank this field selects the appropriate csx pin when a run command is executed. 000 = cs0 is selected. 001 = cs1 is selected. 010 = cs2 is selected. 011 = cs3 is selected. 100 = cs4 is selected. 101 = cs5 is selected. 110 = cs6 is selected. 111 = cs7 is selected. bits 19 and 24C25reserved these bits are reserved and must be set to 0. mclfmemory command loop field this field specifies the number of times a loop is executed for a run command. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times. madmemory array index this field specifies an index to one of 64 ram words in the ram array for command execution.
memory controller motorola mpc823e reference manual 15-19 memory controller 15 15.3.1.5 machine a mode register. the machine a mode register (mamr) contains the configuration for the user-programmable machine a. see figure 15-1 (page 15-3) for more information. ptaperiodic timer a period this field affects the periodic timer a and determines the timer period service rate using the following equation: ncs is an integer between 1 and 8 that represents the number of enabled chip-selects that select this upm. the dfbrg field is the division factor for the brgclk, which can be divided by 1 (default), 4, 16, or 64 and is programmed in the sccr (described in section 5.2.1 system clock and reset control register ). for example, for dram to maintain data integrity an access or refresh must occur every 15.6 m s. use the equation above to determine the pta value for upma to perform memory refresh. given that you have a 25mhz system clock with the required service rate of 15.6 m s, a periodic timer prescaler equal to 32, and a dfbrg field that is equal to 0, then the pta value must be (25 15.6) / (2 2 0 32 1) = 12. if you want to perform more than one refresh per service, use the tlfa field. mamr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pta ptae ama res dsa res reset 0 0 0 000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x170 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field g0cla gpla4 dis rlfa wlfa tlfa reset 01000 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x172 note: the upm refresh is done in a round robin manner. if more than one chip-select uses the same upm, the refreshes will progress through each one. for example, if you have three chip-selects using upma, you would need to set the periodic timer a period to one-third the normal refresh. pta system clock (mhz) service duration (s) 2 2 dfbrg prescaler (ptp) ncs -------------------------------------------------------------------------------------------------------------------- - =
memory controller 15-20 mpc823e reference manual motorola memory controller 15 ptaeperiodic timer a enable this bit allows the periodic timer a to request service. 0 = periodic timer a is disabled. 1 = periodic timer a is enabled. amaaddress multiplex size a this field specifies the number of address lines to be output on the bus at the first clock of the memory cycle (see table 15-7 on page 15-60 for more information). the amx field of the ram array entry controls the output of the address lines, as shown in table 15-3 (page 15-37). for example, these address lines can be used to connect to the dram devices that require row and columns to be multiplexed on the same pin. bits 12 and 15reserved these bits are reserved and must be set to 0. dsadisable timer period this bit guarantees a minimum time between accesses to the same memory bank if it is controlled by the upma. the todt bit turns on the disable timer in the ram array and, when expired, the upma allows the machine access to issue a memory pattern to the same memory region. accesses to different memory regions using two or more chip-selects can be handled by this same upma, assuming they have the same timing. the maximum disable period is four clock cycles. when switching to a different bank that requires more than four clock cycles, you must add more upm ram word to meet your time requirement. refer to section 15.5.4.2 ram word operation for more specific dram example information. 00 = 1-cycle disable period. 01 = 2-cycle disable period. 10 = 3-cycle disable period. 11 = 4-cycle disable period. g0clageneral line 0 control a this field selects the address line that is output to the internal gpl0 signal when the upma is selected to control memory access. it can be used for precharge control on sdrams. 000 = a12 is selected. 001 = a11 is selected. 010 = a10 is selected. 011 = a9 is selected. 100 = a8 is selected. 101 = a7 is selected. 110 = a6 is selected. 111 = a5 is selected.
memory controller motorola mpc823e reference manual 15-21 memory controller 15 gpla4disgpla4 output line disable this bit determines whether or not the upwaita/gpl_a4 pin will behave as an output line controlled by the internal gpl4 signal and the upm ram word. 0 = upwaita/gpl_a4 is defined as gpl_a4 . 1 = upwaita/gpl_a4 is defined as upwaita. rlfaread loop field a this field specifies the number of times a loop defined in the upma ram word is executed for a burst read or single beat read cycle. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times. wlfawrite loop field a this field specifies the number of times a loop defined in the upma ram word is executed for a burst write or a single beat write cycle. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times.
memory controller 15-22 mpc823e reference manual motorola memory controller 15 tlfatimer loop field a this field specifies the number of times a loop defined in the upma ram word is executed for a periodic timer service. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times. 15.3.1.6 machine b mode register. the machine b mode register (mbmr) contains the configuration for the user-programmable b machine. see figure 15-1 (page 15-3) for more information. mbmr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ptb ptbe amb res dsb res reset 0 0 0 000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x174 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field g0clb gplb4 dis rlfb wlfb tlfb reset 01000 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x176 note: the upm refresh is done in a round robin manner. if more than one chip-select uses the same upm, the refreshes will progress through each one. for example, if you have three chip-selects using upma, you would need to set the periodic timer a period to one-third the normal refresh.
memory controller motorola mpc823e reference manual 15-23 memory controller 15 ptbperiodic timer b this field affects the periodic timer b and determines the timer period using the following equation: ncs is an integer between 1 and 8 that represents the number of enabled chip-selects that select this upm. the dfbrg field is the division factor for the brgclk, which can be divided by 1 (default), 4, 16, or 64 and is programmed in the sccr (described in section 5.2.1 system clock and reset control register ). for example, for dram to maintain data integrity an access or refresh must occur every 15.6 m s. use the equation above to determine the ptb value for upmb to perform memory refresh. given that you have a 25mhz system clock with the required service rate of 15.6 m s, a periodic timer prescaler equal to 32, and a dfbrg field that is equal to 0, then the ptb value must be (25 15.6) / (2 2 0 32 1) = 12. if you want to perform more than one refresh per service, use the tlfb field. ptbeperiodic timer b enable this bit allows the periodic timer b to request service. 0 = periodic timer b is disabled. 1 = periodic timer b is enabled. ambaddress multiplex size b this field specifies the number of address lines to be output on the bus at the first clock of the memory cycle (see table 15-7 on page 15-60 for more information). the amx field of the ram array entry controls the output of the address lines, as shown in table 15-3 (page 15-37). for example, these address lines can be used to connect to the dram devices that require row and columns to be multiplexed on the same pin. bits 12 and 15reserved these bits are reserved and must be set to 0. dsbdisable timer period this bit guarantees a minimum time between accesses to the same memory bank if it is controlled by the upmb. the todt bit turns on the disable timer in the ram array and, when expired, the upmb allows the machine access to issue a memory pattern to the same memory region. accesses to different memory regions using two or more chip-selects can be handled by this same upmb, assuming they have the same timing. the maximum disable period is four clock cycles. when switching to a different bank that requires more than four clock cycles, you must add more upm ram word to meet your time requirement. ptb system clock (mhz) service duration (s) 2 2 dfbrg prescaler (ptp) ncs -------------------------------------------------------------------------------------------------------------------- - =
memory controller 15-24 mpc823e reference manual motorola memory controller 15 refer to section 15.5.4.2 ram word operation for more specific dram example information. 00 = 1-cycle disable period. 01 = 2-cycle disable period. 10 = 3-cycle disable period. 11 = 4-cycle disable period. g0clbgeneral line 0 control b this field selects the address line that is output to the internal gpl0 signal when the upmb is selected to control memory access. it can be used for precharge control on sdrams. 000 = a12 is selected. 001 = a11 is selected. 010 = a10 is selected. 011 = a9 is selected. 100 = a8 is selected. 101 = a7 is selected. 110 = a6 is selected. 111 = a5 is selected. gplb4disgplb4 output line disable this bit determines whether or not the upwaitb/gpl_b4 pin will behave as an output line controlled by the internal gpl4 signal and the upm ram word. 0 = upwaitb/gpl_b4 is defined as gpl_b4 . 1 = upwaitb/gpl_b4 is defined as upwaitb. rlfbread loop field b this field specifies the number of times a loop defined in the upmb ram word is executed for a burst read or single beat read cycle. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times.
memory controller motorola mpc823e reference manual 15-25 memory controller 15 wlfbwrite loop field b this field specifies the number of times a loop defined in the upmb ram word is executed for a burst write or a single beat write cycle. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times. tlfbtimer loop field b this field specifies the number of times a loop defined in the upmb ram word is executed for a periodic timer service cycle. 0001 = the loop is executed 1 time. 0010 = the loop is executed 2 times. 0011 = the loop is executed 3 times. 0100 = the loop is executed 4 times. 0101 = the loop is executed 5 times. 0110 = the loop is executed 6 times. 0111 = the loop is executed 7 times. 1000 = the loop is executed 8 times. 1001 = the loop is executed 9 times. 1010 = the loop is executed 10 times. 1011 = the loop is executed 11 times. 1100 = the loop is executed 12 times. 1101 = the loop is executed 13 times. 1110 = the loop is executed 14 times. 1111 = the loop is executed 15 times. 0000 = the loop is executed 16 times.
memory controller 15-26 mpc823e reference manual motorola memory controller 15 15.3.1.7 memory data register. the memory data register (mdr) contains the data to be written to or read from the ram array for upm command operations. this register must be set up before you issue a write command to the memory command register. mdmemory data this field contains the ram array word. 15.3.1.8 memory address register. the memory address register (mar) contains an address to be output on the address lines that are controlled by the amx field in the ram word of the ram array. mamemory address this field contains a 32-bit address to be output on the address bus if the amx field is equal to 11. refer to section 15.5.4 the ram array for more information. mdr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field md reset 0 r/w r/w addr (immr & 0xffff0000) + 0x17c bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field md reset 0 r/w r/w addr (immr & 0xffff0000) + 0x17e mar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ma reset 0 r/w r/w addr (immr & 0xffff0000) + 0x164 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ma reset 0 r/w r/w addr (immr & 0xffff0000) + 0x166
memory controller motorola mpc823e reference manual 15-27 memory controller 15 15.3.1.9 memory periodic timer prescaler register. the memory periodic timer prescaler register (mptpr) defines the divisor of the brgclk used as the memory periodic timer input clock. refer to section 5.3.4 internal clock signals for details. ptpperiodic timers prescaler this field determines the division factor that is shown below. 001x xxxx = divide by 2. 0001 xxxx = divide by 4. 0000 1xxx = divide by 8. 0000 01xx = divide by 16. 0000 001x = divide by 32. 0000 0001 = divide by 64. 1xxx xxxx = reserved. 01xx xxxx = reserved. bits 8C15reserved these bits are reserved and must be set to 0. 15.4 the general-purpose chip-select machine the general-purpose chip-select machine (gpcm) allows a glueless and flexible interface between the mpc823e, sram, eprom, feprom, rom devices, and external peripherals. the gpcm contains three basic register groups that you can use to configure itbase registers 0C7, option registers 0C7, and the memory status register. 15.4.1 configuration if the ms field in the brx of the selected bank selects the general-purpose chip-select machine, the attributes for the memory cycle initiated are taken from the orx. these attributes include the csnt, acs, scy, trlx, ehtr, and seta fields. see table 15-2 for signal behavior and system response. mptpr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ptp reserved reset 00000001 00000000 r/w r/w r/w addr (immr & 0xffff0000) + 0x17a
memory controller 15-28 mpc823e reference manual motorola memory controller 15 anywhere from 0 to 30 wait states can be programmed for ta generation. the wex signals are available for each byte that is written to memory. also, an oe signal is provided to eliminate external glue logic. on system reset, a global chip-select (cs0 ) is asserted to provide a boot rom chip-select before the system is fully con?gured. table 15-2. gpcm strobe signal behavior option register attributes signal behavior trlx access type ebdf csnt acs address to cs x asserted address to oe asserted address to we x asserted data to we x asserted cs x negated to add/data invalid we x negated to add/data invalid total number of cycles 0 read 00 0 3/4*clock 1/4* clock 2+scy 10 1/4*clock 11 1/2*clock write 0 00 0 1/4*clock 10 1/4*clock 3/4*clock -1/4*clock 11 1/2*clock 00 1 00 0 1/2*clock 10 1/4*clock 1/2*clock 11 1/2*clock 01 00 0 1/4*clock 3/8*clock 10 1/4*clock 3/8*clock 11 1/2*clock 1 read 00 0 3/4*clock 1/4*clock 2+2*scy 10 (1+1/4)*clock 1+3/4*clock 3+2*scy 11 (1+1/2)*clock 1+3/4*clock write 0 00 0 3/4*clock -1/4*clock 1/4*clock 2+2*scy 10 (1+1/4)*clock 1+3/4*clock 3/4*clock 3+2*scy 11 (1+1/2)*clock 1+3/4*clock 3/4*clock 00 1 00 0 3/4*clock -1/4*clock 1+1/2*clock 10 (1+1/4)*clock 1+3/4*clock 3/4*clock 1+1/2*clock 4+2*scy 11 (1+1/2)*clock 1+3/4*clock 3/4*clock 01 00 0 3/4*clock -1/4*clock 1/4*clock 1+3/8*clock 3+2*scy 10 (1+1/4)*clock 1+3/4*clock 3/4*clock 1+3/8*clock 4+2*scy 11 (1+1/2)*clock 1+3/4*clock 3/4*clock note: scy is the number of wait cycles from the option register.
memory controller motorola mpc823e reference manual 15-29 memory controller 15 next, the banks selected by the general-purpose chip-select machine support an option to output the csx signal at different timings with respect to the external address bus. csx can be output in any of the following con?gurations: ? simultaneous with the external address ? one quarter of a clock later ? one half of a clock later this all depends, of course, on the value in the acs ?eld of the orx register, plus an additional cycle if the trlx bit is set. the general-purpose chip-select machine allows you to connect to devices that have long disconnect times on data by delaying new bus transactions addressing other memory banks for additional clock cycles. finally, the banks selected to operate with the general-purpose chip-select machine support termination of an external cycle by sensing the ta signal asserted by the addressed external slave. refer back to table 15-2 for more information. figure 15-5 illustrates a basic connection between the mpc823e and a static memory device. in this case, the csx signal is connected directly to the ce signal of the memory device. the wex signals are connected to the respective w signal of the memory device in which each wex signal corresponds to a different data byte. mpc823e memory figure 15-5. gpcm memory device interface address ce oe w data address cs x oe we x data
memory controller 15-30 mpc823e reference manual motorola memory controller 15 as illustrated in figure 15-6, the timing of the csx signal is the same as the timing of the address lines. the strobes for the transaction are supplied by the oe or wex signals, depending on the transaction direction (read or write). the negation of the wex signal is controlled by the csnt bit of the orx register. the csx signal is generated when the acs field in the corresponding orx register is set to 00. figure 15-6. gpcm memory device basic timing (acs = 00, csnt = 1, and trlx = 0) clock address cs x we x oe data ts ta csnt = 1
memory controller motorola mpc823e reference manual 15-31 memory controller 15 figure 15-7 illustrates the basic connection between the mpc823e and an external peripheral device. in this case, csx is connected directly to the ce signal of the memory device and the r/w signal is connected to the respective r/w signal in the peripheral device. the csx signal is the strobe output for the memory access. figure 15-8 illustrates the csx signal as defined by the setup time required between the address lines and the ce signal. the mpc823e memory controller allows you to specify the csx signal to meet this requirement using the acs field of the option register. memory peripheral figure 15-7. gpcm peripheral device interface figure 15-8. gpcm peripheral device basic timing (acs = 10 or 11 and trlx = 0) address ce r/w data address cs x r/w data clock address ts ta cs x r/w data acs = 10 acs = 11
memory controller 15-32 mpc823e reference manual motorola memory controller 15 the general-purpose chip-select machine also provides a csnt attribute in the option register that controls the timing for the appropriate strobe negation in write cycles. when this attribute is asserted, the strobe is negated one quarter of a clock before the normal case. for example, when the acs field equals 00 and csnt is set, wex is negated one quarter of a clock earlier and when acs does not equal 00 and csnt is set, wex and csx are negated one quarter of a clock earlier. for more information, see figure 15-6, figure 15-8, and table 15-2. the trlx field in the option register is provided for memory systems that require more relaxed timing between signals. when trlx is set and the acs field is not equal to 00, an additional cycle between the address and strobes is inserted by the mpc823e memory controller, as shown in figure 15-9. when trlx and csnt are set in a write-memory access, the strobe lines (wex and csx , if acs is not equal to 00) are negated one clock earlier than in the normal case, as shown in figure 15-11. when a bank is selected to operate with external transfer acknowledge (seta and trlx are set), the memory controller does not support external devices that provide the ta signal to complete the transfer with zero wait states. the minimum access duration in this case is three clock cycles. figure 15-9. mpc823e gpcmCrelaxed timingCread access (acs = 10 or 11, scy = 1, and trlx = 1) clock address ts ta cs x r/w we x data oe acs = 10 acs = 11
memory controller motorola mpc823e reference manual 15-33 memory controller 15 figure 15-10. mpc823e gpcmCrelaxed timingCwrite access (acs = 10 or 11, scy = 0, csnt = 0, and trlx = 1) figure 15-11. mpc823e gpcmCrelaxed timingCwrite access (acs = 10 or 11, scy = 0, csnt = 1, and trlx = 1) clock address ts ta cs x r/w we x data oe acs = 10 acs = 11 clock address ts ta cs x r/w we x data oe acs = 10 acs = 11
memory controller 15-34 mpc823e reference manual motorola memory controller 15 15.4.1.1 programmable wait state configuration. the general-purpose chip-select machine supports internal ta signal generation. it allows fast accesses to external memory through an internal bus master or it allows a maximum 17-clock access. this can be done by programming the scy field in the option register. the internal ta generation mode is enabled if the seta field in the option register is cleared. if the ta pin is externally asserted at least two clock cycles before the wait state counter has expired, the current memory cycle is terminated. when the trlx bit is set, the number of wait states inserted by the memory controller is defined by 2 x scy or a maximum of 30 wait states. 15.4.1.2 extended hold time on read accesses. slow memory devices that require a long delay on data read accesses must set the ehtr field in the corresponding option register. any gpcm access to the external bus following a read access to the slower memory bank is delayed by one clock cycle, unless it is a read access to the same bank. refer to figure 15-13 through figure 15-16 for details. figure 15-12. mpc823e gpcmCrelaxed timingCwrite access (acs = 00, scy = 0, csnt = 1, and trlx = 1) clock address ts ta cs x r/w we x data oe
memory controller motorola mpc823e reference manual 15-35 memory controller 15 figure 15-13. gpcm read followed by write (ehtr = 0) figure 15-14. gpcm write followed by read (ehtr = 1) clock address ts ta cs x cs y r/w data oe hold time clock address ts ta cs x cs y r/w data oe hold time long hold time allowed
memory controller 15-36 mpc823e reference manual motorola memory controller 15 figure 15-15. gpcm read followed by read from different banks (ehtr = 1) figure 15-16. gpcm read followed by read from same bank (ehtr = 1) clock address ts ta cs x cs y r/w data oe hold time long hold time allowed clock address ts ta cs x cs y r/w data oe hold time
memory controller motorola mpc823e reference manual 15-37 memory controller 15 15.4.1.3 boot chip-select operation. boot chip-select operation allows address decoding for a boot rom before system initialization occurs. the cs0 signal is the boot chip-select output and its operation differs from the other external chip-select outputs on system reset. when the mpc823e internal core begins accessing memory at system reset, cs0 is asserted for every address, unless an internal register is accessed. the boot chip-select provides a programmable port size during system reset by using the bps field of the hard reset configuration word, as shown in section 4.3.1.1 hard reset configuration word . setting these appropriately allows a boot rom to be located anywhere in the address space. the boot chip-select does not provide write protection and responds to all address types. cs0 operates this way until the first write to the option register 0 and it can be used as any other chip-select register once the preferred address range is loaded into base register 0. after the first write to option register 0, the boot chip-select can only be restarted on system reset. the initial values of the boot bank in the memory controller are described in table 15-3. table 15-3. boot bank field values after reset field value base register 0 ps from hard reset configuration word pare 0 wp 0 ms 00 v from hard reset configuration word option register 0 am 00000000000000000 atm 000 csnt 1 acs 11 bi 1 scy 1111 seta 0 trlx 1 ehtr 0
memory controller 15-38 mpc823e reference manual motorola memory controller 15 15.4.1.4 sram interface. figure 15-17 illustrates a simple connection between an sram device and the mpc823e. 15.4.1.5 external asynchronous master support. figure 15-18 illustrates the basic interface between an asynchronous external master and the gpcm to allow connection to static ram memory. memory 32-bit wide sram figure 15-17. gpcm to sram configuration figure 15-18. asynchronous external master configuration for gpcm-handled memory devices we x ce oe address data we x cs x gpl_ x 1 / oe a[15:29] d[0:31] 128k address ce oe w data address cs x oe we x data asynchronous external master as ta ta as address data memory mpc823e
memory controller motorola mpc823e reference manual 15-39 memory controller 15 figure 15-19 illustrates the timing for trlx = 0 when an external asynchronous master accesses sram. the ta signal remains asserted with the wex and oe signals until the as signal is negated by the external master. when an external asynchronous master performs an access to a memory device via the general-purpose chip-select machine in the memory controller, the csnt bit in the option register is configured as dont care. figure 15-19. asynchronous external master, gpcm-handled memory access timing (trlx = 0) clock address cs we oe data ta as
memory controller 15-40 mpc823e reference manual motorola memory controller 15 15.5 user-programmable machines each of the two user-programmable machines (upms) is a flexible interface that connects to a wide range of memory devices. at the heart of each upm is an internal memory ram array that specifies the logical value driven on the external memory controller pins for a given clock cycle. each word in the ram array provides bits that allow a memory access to be controlled with a resolution of one quarter of the system clock period on the byte-select and chip-select lines. figure 15-20 illustrates the basic operation of each upm. a upm cycle is initiated when: ? any internal or external master requests an external memory access ? a memory periodic timer expires and requests a transaction ? a transfer error or reset generates an exception request ? the memory command register receives a run command (software) from the cpu the ram array contains 32-bit entries referred to as ram words. if the upm reads a ram word with the waen bit set, the external upwaitx signal is sampled and synchronized by the memory controller and the current request is frozen. the signal timing generator will load the ram word from the ram array to drive the general-purpose lines, byte-selects, and chip-selects. figure 15-20. user-programmable machine block diagram signals timing generator internal signals latch array generator internal/external memory memory periodic timer software request ram array increment request access request (last = 0) wait request logic waen bit hold index upwait index gpl x , bs x , cs x internal controls index exception request
memory controller motorola mpc823e reference manual 15-41 memory controller 15 memory controller 15 15.5.1 requests the user-programmable machine has four basic requests that can initiate a upm cycle. there is a special start address in the ram array that is associated with each of the following cycle types: ? read single beat start address (rss) ? read burst cycle start address (rbs) ? write single beat start address (wss) ? write burst cycle start address (wbs) ? periodic timer start address (pts) ? exception condition start address (exs) figure 15-21 illustrates the first locations addressed by the upm, according to the different cycle types. software requests, however, can point to any of the 64 upm ram entries. figure 15-21. ram array indexing 64 rss wss rbs wbs pts burst read request burst write request read single beat request write single beat request periodic timer request exs exception condition ram array array index generator ram words
memory controller 15-42 mpc823e reference manual motorola memory controller 15 15.5.1.1 internal/external memory access requests. when any of the internal masters request a new access to external memory, the address and type of the transfer are compared to each one of the valid banks defined in the base register. the value of the ms field in the base register selects the upm that will handle the memory access. you must ensure that the appropriate upm entries are created prior to your request. the external memory access requests consist of read single beat, read burst, write single beat, and write burst. a single beat cycle is generated by the master to a cache-inhibited memory bank. a typical burst cycle is generated to the memory that allows multiple accesses. it only occurs when your memory is burstable. a single beat cycle starts out with one transfer start and ends with one transfer acknowledge. for a 32-bit access, the burst cycle starts out with one transfer start but ends with four transfer acknowledges. for a 16-bit bus, there are eight transfer acknowledges. for an 8-bit bus, there are 16 transfer acknowledges. 15.5.1.2 memory periodic timer requests. each upm contains a periodic timer that can be programmed to generate periodic service requests that will be indexed into the ram array. figure 15-22 illustrates the hardware associated with memory periodic timer request generation. in general, the periodic timer is used for refresh cycle operation. figure 15-22. memory periodic timer request block diagram note: the upm refresh is done in a round robin manner. if more than one chip-select uses the same upm, the refreshes will progress through each one. for example, if you have three chip-selects using upma, you would need to set the periodic timer a period to one-third the normal refresh. upma periodic upmb periodic periodic memory system brg prescaler timer request timer request clock periodic timer prescaler (in the mptpr) timer a (pta) periodic timer b (ptb) (in the sccr)
memory controller motorola mpc823e reference manual 15-43 memory controller 15 memory controller 15 15.5.1.3 software requests. the software can initiate a request to the user-programmable machine by issuing one of three commandsread, write, or execute a ram wordto the memory command register. every memory device has its own signal handshaking protocol to put it into self-refresh mode or any special protocol mode. in the user-programmable machine there are unused areas that enable you to write a special ram word for this protocol. any unused area in the upm ram can be used to store these ram words. typically, software requests are used to put the memory in self-refresh mode. you can use this method to maintain memory integrity before entering low-power modes. a new command must be issued to exit self-refresh mode or any special protocol mode after returning to normal operation. 15.5.1.4 exception requests. when an access to a memory device is initiated by the mpc823e under upm control, the external device may assert a tea , sreset , or hreset signal. the upm provides a mechanism that allows you to handle the memory control signals to meet the timing requirements of the device without losing data. 15.5.2 programming the user-programmable machine the user-programmable machine is a micro-sequencer that requires micro-instructions or ram words to generate signal timings for different memory cycles. you must program the user-programmable machine in the following order: 1. write a program into the ram array. 2. set up the base and option registers. 3. program the memory periodic timer prescaler register. 4. program the machine mode register. each user-programmable machine has a machine mode register (mxmr) that defines the general attributes for operation. the pta field of the mamr and the ptb field of the mbmr defines the period for the timers associated with upma and upmb. if the ptae bit is set, the periodic timer of upma requests a transaction when the timer period expires. if the ptbe bit is set, the periodic timer of upmb requests a transaction when the timer period expires. to initiate a software request, issue the appropriate command to the memory command register with the mad field indexing the first entry of the upm entry word. command execution is accomplished by accessing consecutive ram words (one per clock) until the word with the last bit set is encountered. the words read from the ram provide information about the value and timing of the external signals controlled by the upm and about specific strobes that control internal memory controller resources. there is a disable timer mechanism associated with each user-programmable machine that is only active between memory accesses. this timer is used to provide a delay between successive memory cycles to the same bank.
memory controller 15-44 mpc823e reference manual motorola memory controller 15 each of the upms can control how the address of the current access is output to the external pins. address multiplexing configurations for a specific memory or device can be selected in the machine mode register. there is also a multiplexing field in the ram word that is used to control cycle-by-cycle accesses. specific user-programmable machine register information is located in section 15.3.1 register descriptions . 15.5.3 clock timing the ram word includes fields that specify the value of the various external signals at each clock edge. the signal timing generator causes the external signals to behave according to the timing specified in the current ram word. figure 15-23 and figure 15-24 illustrate the clock schemes of the user-programmable machines in the memory controller. the clock phases shown in these figures reflect timing windows that specify when generated signals can change state. figure 15-23 represents the clock scheme selected when the ebdf field of the system clock and reset control register is equal to 00. as indicated in the figure, clkout is the same as system clock. in figure 15-24, if the ebdf field of the system clock and reset control register is equal to 01, then clkout is equal to the system clock divided by 2. notice that in this scheme gclk1 does not have a 50% duty cycle. the state of the external signals may change (if specified in the ram array) at any edge of gclk1 and gclk2, plus a propagation delay. figure 15-23. upm clock scheme one (division factor = 1) clkout gclk1 gclk2 system clock clock phase 1 2 3 4 1 2 3
memory controller motorola mpc823e reference manual 15-45 memory controller 15 memory controller 15 the csx signals are handled in a similar way, except that only the csx signal corresponding to the currently accessed bank is modified. the bs signal assertion and negation timing is also specified for each cycle in the ram word, but the final value of each one of these signals depends on the port size of the specified bank, the external address accessed, and the value of the tsizx pins. figure 15-25 and figure 15-26 provide examples of how to control the timing of the csx , gpl1 , and gpl2 signals. a ram word is read on the rising edge of every gclk2 cycle or in phase 3 of the previous clock cycle. it determines the value of the cst1C4, g1t3, g1t4, g2t3, and g2t4 bits, which specifies the timing of chip-selects, byte-selects, and gplx signals based on any edge of gclk1 or gclk2. figure 15-24. upm clock scheme two (division factor = 2) clkout gclk1 gclk2 system clock 1234123 4 clock phase
memory controller 15-46 mpc823e reference manual motorola memory controller 15 the clock phases shown in these figures refer to the timing windows when the signals controlled by these bits in the ram word are driven. figure 15-25. upm signals timing example one (division factor = 1, ebdf = 00) clkout gclk1 gclk2 cs x gpl1 gpl2 cst4 cst1 cst2 cst3 cst4 cst1 cst2 cst3 g1t4 g1t3 g1t4 g1t3 g2t4 g2t3 g2t4 g2t3 ram word 1 ram word 2 system clock 1234123 clock phase
memory controller motorola mpc823e reference manual 15-47 memory controller 15 memory controller 15 figure 15-26. upm signals timing example two (division factor = 2, ebdf = 01) clkout gclk1 gclk2 cs x gpl1 gpl2 cst4 cst2 cst3 cst4 cst2 cst3 g1t4 g1t3 g1t4 g1t3 g2t4 g2t3 g2t4 g2t3 ram word 1 ram word 2 system clock cst1 cst1 1 234 12 3 clock phase
memory controller 15-48 mpc823e reference manual motorola memory controller 15 15.5.4 the ram array the ram array size for each upm is 64 locations deep and 32 bits wide as illustrated in figure 15-27. the selected bank is one of eight banks that matches the current address. the signal generation shown at the bottom part of the figure are outputs of the upm and not direct signal outputs of the mpc823e. figure 15-27. ram array and signal generation gclk1 gclk2 gpl0 gpl2 gpl3 gpl4 gpl5 signals timing generator ram array cs signal selector bs signal cs x bs x selected bank tsizx, ps, a[30:31] 32 bits wide 64 gpl1 ram words selector deep cs x bs x
memory controller motorola mpc823e reference manual 15-49 memory controller 15 memory controller 15 15.5.4.1 the ram word. the ram word is a 32-bit wide micro-instruction that is stored in one of 64 locations in the ram array. 15.5.4.1.1 ram word format. the ram word format selects and specifies the timing of all external signals controlled by the user-programmable machine. cst4chip-select timing 4 this bit defines the state of the csx signal during clock phase 1. 0 = the csx signal is asserted at the trailing edge of gclk2. 1 = the csx signal is negated at the trailing edge of gclk2. cst1chip-select timing 1 this bit defines the state of the csx signal during clock phase 2. 0 = the csx signal is asserted at the rising edge of gclk1. 1 = the csx signal is negated at the rising edge of gclk1. cst2chip-select timing 2 this bit defines the state of the csx signal during clock phase 3. 0 = the csx signal is asserted at the rising edge of gclk2. 1 = the csx signal is negated at the rising edge of gclk2. ram word bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cst4 cst1 cst2 cst3 bst4 bst1 bst2 bst3 g0l g0h g1t4 g1t3 g2t4 g2t3 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (mcr mad ) indirect addressing of 1 of 64 entries bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field g3t4 g3t3 g4t4/ dlt3 g4t3/ waen g5t4 g5t3 reserved loop exen amx na uta todt last reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr * note: * all 32 bits of the ram word are addressed as shown in the address row above. = undefined. note: the state of the selected csx signal depends on the value of each cstx bit and the corresponding bank.
memory controller 15-50 mpc823e reference manual motorola memory controller 15 cst3chip-select timing 3 this bit defines the state of the csx signal during clock phase 4. 0 = the csx signal is asserted at the trailing edge of gclk1. 1 = the csx signal is negated at the trailing edge of gclk1. bst4byte-select timing 4 this bit defines the state of the bsx signal during clock phase 1. 0 = the bsx signal is asserted at the trailing edge of gclk2. 1 = the bsx signal is negated at the trailing edge of gclk2. bst1byte-select timing 1 this bit defines the state of the bsx signal during clock phase 2. 0 = the bsx signal is asserted at the rising edge of gclk1. 1 = the bsx signal is negated at the rising edge of gclk1. bst2byte-select timing 2 this bit defines the state of the bsx signal during clock phase 3. 0 = the bsx signal is asserted at the rising edge of gclk2. 1 = the bsx signal is negated at the rising edge of gclk2 bst3byte-select timing 3 this bit defines the state of the bsx signal during clock phase 4. 0 = the bsx signal is asserted at the trailing edge of gclk1. 1 = the bsx signal is negated at the trailing edge of gclk1. g0lgeneral-purpose line 0 lower this field defines the state of the gpl0 signal during clock phases 1 through 3. 10 = the gpl0 signal is asserted at the trailing edge of gclk2. 11 = the gpl0 signal is negated at the trailing edge of gclk2. 00 = the gpl0 signal is driven at the trailing edge of gclk2 as defined in the g0clx field of the mxmr. note: the state of each bsx signal depends on the value of each bstx bit and three other parameter valuesthe ps field in the selected base register and the tsizx and a[30:31] signals in the currently accessed cycle.
memory controller motorola mpc823e reference manual 15-51 memory controller 15 memory controller 15 g0hgeneral-purpose line 0 higher this field defines the state of the gpl0 signal during clock phase 4. 10 = the gpl0 signal is asserted at the trailing edge of gclk1. 11 = the gpl0 signal is negated at the trailing edge of gclk1. 00 = the gpl0 signal is driven at the trailing edge of gclk1 as defined in the g0clx field of the mxmr. g1t4general-purpose line 1 timing 4 this bit defines the state of the gpl1 signal during clock phases 1 through 3. 0 = the gpl1 signal is asserted at the trailing edge of gclk2. 1 = the gpl1 signal is negated at the trailing edge of gclk2. g1t3general-purpose line 1 timing 3 this bit defines the state of the gpl1 signal during clock phase 4. 0 = the gpl1 signal is asserted at the trailing edge of gclk1. 1 = the gpl1 signal is negated at the trailing edge of gclk1. g2t4 general-purpose line 2 timing 4 this bit defines the state of the gpl2 signal during clock phases 1 through 3. 0 = the gpl2 signal is asserted at the trailing edge of gclk2. 1 = the gpl2 signal is negated at the trailing edge of gclk2. g2t3general-purpose line 2 timing 3 this bit defines the state of the gpl2 signal during clock phase 4 0 = the gpl2 signal is asserted at the trailing edge of gclk1. 1 = the gpl2 signal is negated at the trailing edge of gclk1. g3t4general-purpose line 3 timing 4 this bit defines the state of the gpl3 signal during clock phases 1 through 3. 0 = the gpl3 signal is asserted at the trailing edge of gclk2. 1 = the gpl3 signal is negated at the trailing edge of gclk2. g3t3general-purpose line 3 timing 3 this bit defines the state of the gpl3 signal during clock phase 4. 0 = the gpl3 signal is asserted at the trailing edge of gclk1. 1 = the gpl3 signal is negated at the trailing edge of gclk1.
memory controller 15-52 mpc823e reference manual motorola memory controller 15 g4t4/dlt3general-purpose line 4 timing 4/delay time 3 this bit performs two functions depending on the value of the gplx4dis bit in the machine mode register. if the mxmr defines the upwaitx/gpl_x4 pin as an output (gpl_x4 ), then this bit functions as g4t4. if it is defined as an input (upwaitx), then this bit functions as dlt3. if you have configured gplx4dis = 0 in the mxmr, then you have selected g4t4: 0 = the value of the gpl4 signal at the trailing edge of gclk2 will be 0. 1 = the value of the gpl4 signal at the trailing edge of gclk2 will be 1. if you have configured gplx4dis = 1 in the mxmr, then you have selected upwaitx and dlt3 is the controlling function: 0 = the data bus must be sampled at the rising edge of gclk2 for all reads. 1 = the data bus must be sampled at the falling edge of gclk2 for all reads. g4t3/waengeneral-purpose line 4 timing 3/wait enable this bit performs two functions depending on the value of the gplx4dis bit in the machine mode register. if the mxmr defines the upwaitx/gpl_x4 pin as an output (gpl_x4 ), then this bit functions as g4t3. if it is defined as an input (upwaitx), this bit functions as waen. if you have configured gplx4dis = 0 in the mxmr, then you have selected g4t3: 0 = the value of the gpl4 signal at the trailing edge of gclk1 will be 0. 1 = the value of the gpl4 signal at the trailing edge of gclk1 will be 1. if you have configured gplx4dis = 1 in the mxmr, then you have selected upwaitx and waen is the controlling function: 0 = the upwaitx function is disabled. 1 = a freeze in the logical value of the upm-controlled external signals will occur when the upwaitx pin is asserted. the upwaitx signal is sampled on the trailing edge of gclk2. see figure 15-33 for more information. g5t4general-purpose line 5 timing 4 this bit defines the state of the gpl5 signal during clock phases 1 through 3. 0 = the value of the gpl5 signal at the trailing edge of gclk2 will be 0. 1 = the value of the gpl5 signal at the trailing edge of gclk2 will be 1. g5t3general-purpose line 5 timing 3 this bit defines the state of the gpl5 signal during clock phase 4. 0 = the value of the gpl5 signal at the trailing edge of gclk1 will be 0. 1 = the value of the gpl5 signal at the trailing edge of gclk1 will be 1. bits 22 and 23reserved these bits are reserved and must be set to 0.
memory controller motorola mpc823e reference manual 15-53 memory controller 15 memory controller 15 looploop the first ram word in the ram array where loop is 1 is recognized as the loop start word. the next ram word where loop is 1 is recognized as the loop end word. the ram words between the beginning and end are defined as the loop. the upm executes this loop as many times as it is defined in the corresponding loop field of the mxmr. 0 = the current ram word is not the start or end of a loop construct. 1 = the current ram word is the start or end of a loop construct. exenexception enable when an external device asserts the tea or reset signals, this bit allows you to branch to the exception start address (exs) where you would store your exception handler. the exception start address is found at a fixed address in the ram array. 0 = the upm continues executing the remaining ram words. 1 = the current ram word allows a branch to an exception handler after the current cycle if an exception condition is detected. the exception condition can be an external device asserting tea , hreset , or sreset . amxaddress multiplexing this bit determines the source of the a[6:31] signals. 00 = the value of the a[6:31] signals at the trailing edge of gclk1 is the address that is requested by the internal master. for example, column address. 01 = reserved. 10 = the value of the a[6:31] signals at the trailing edge of gclk1 is the address that is requested by the internal master multiplexed according to the ama/amb field of the mxmr. for example, row address. 11 = the value of the a[6:31] signals at the trailing edge of gclk1 is the contents of the memory address register (mar). for example, sdram mode initialization. nanext address this bit determines how much the current address is incremented. 0 = the address increment is disabled. 1 = in conjunction with the ps field in the base register, the increment value of the a[28:31] signals at the trailing edge of gclk1 is as follows: if the accessed bank has a 32-bit port size, the value of the a[28:31] signals are incremented by 4. if the accessed bank has a 16-bit port size, the value of the a[28:31] signals are incremented by 2. if the accessed bank has an 8-bit port size, the value of the a[28:31] signals are incremented by 1. note: the value of the na bit is only relevant when the upm serves a burst-read or burst-write request. under other patterns this bit is reserved.
memory controller 15-54 mpc823e reference manual motorola memory controller 15 utaupm transfer acknowledge this bit controls the state of the ta signal sampled by the external bus interface in the current memory cycle. the ta signal is output at the rising edge of gclk2. 0 = the ta signal is driven low on the next rising edge of gclk2. 1 = the ta signal is driven high on the next rising edge of gclk2. todtturn on disable timer this bit controls the disable timer mechanism. 0 = the disable timer is turned off. 1 = the disable timer for the currently accessed bank is activated. this prevents a new access to the same bank (when controlled by the upms) until the disable timer expires. for example, precharge time. lastlast if this bit is set, it is the last ram word in the program. 0 = the upm continues executing ram words. 1 = the service to the upm request is completed. 15.5.4.2 ram word operation. this section describes how the ram word affects the behavior of the chip-select, byte-select, general-purpose, transfer acknowledgment signals, as well as address multiplexing and the wait mechanism. 15.5.4.2.1 start addresses. each upm request has a special address, except for software requests, which can start at any ram word. table 15-4 provides the start addresses of the upm ram words for each request type. table 15-4. start address locations request to be serviced upm start address read single beat cycle (rss) 0x00 read burst cycle (rbs) 0x08 write single beat cycle (wss) 0x18 write burst cycle (wbs) 0x20 periodic timer request (pts) 0x30 exception (exs) 0x3c
memory controller motorola mpc823e reference manual 15-55 memory controller 15 memory controller 15 15.5.4.2.2 chip-select signals. the ms field in the base register of the accessed memory bank selects a user-programmable machine on the currently requested cycle. the selected upm only affects the assertion and negation of the appropriate csx signal and its timing is specified in the upm ram word. figure 15-28 illustrates how the csx signals are controlled by the upms. figure 15-28. csx signal selection note: the upm refresh is done in a round robin manner. if more than one chip-select uses the same upm, the refreshes will progress through each one. for example, if you have three chip-selects using upma, you would need to set the periodic timer a period to one-third the normal refresh. upma upmb gpcm mux switch bank selected ms[0:1] in brx cs0 cs1 cs2 cs3 cs4 cs5 cs6 cs7 ms[0:1] 00 01 10 11 machine gpcm upma upmb
memory controller 15-56 mpc823e reference manual motorola memory controller 15 15.5.4.2.3 byte-select signals. the ms field in the base register of the accessed memory bank selects a user-programmable machine on the currently requested cycle. the selected upm only affects the assertion and negation of the appropriate bsx signal and its timing as specified in the ram word. the bsx signals are also controlled by the port size of the accessed bank, the transfer size of the transaction, and the address accessed. figure 15-29 illustrates how the bsx signals are controlled by the user-programmable machines. figure 15-29. bsx signal selection upma upmb mux bank selected ms in brx ps in brx tsizx a[30:31] bs0 bs1 bs2 bs3 logic byte- select
memory controller motorola mpc823e reference manual 15-57 memory controller 15 memory controller 15 the uppermost byte select (bs0 ) signal indicates that the most-significant eight bits of the data bus (d0-7) contain valid data during a cycle and the upper-middle byte-select (bs1 ) indicates that the upper-middle eight bits of the data bus (d[8-15]) signal contain valid data during a cycle. the lower-middle byte-select (bs2 ) indicates that the lower-middle eight bits of the data bus (d[16-23]) contain valid data during a cycle and the lowest byte-select (bs3 ) indicates that the least-significant eight bits of the data bus (d[24-31]) contain valid data during a cycle. the manner in which the bsx signals affect 32-, 16-, and 8-bit accesses is shown in table 15-5. it must be noted that for a periodic timer request and a memory command request, the bsx signals are only determined by the port size of the bank. table 15-5. enabling byte-selects transfer size tsizx address 32-bit port size 16-bit port size 8-bit port size a30 a31 bs0 bs1 bs2 bs3 bs0 bs1 bs2 bs3 bs0 bs1 bs2 bs3 byte 0 1 0 0 x x x 01 0 1 x x x 01 1 0 x x x 01 1 1 x x x half-word 1 0 0 0 x x x x x 101 0 xxxx x word 0 0 0 0 xxxxxx x
memory controller 15-58 mpc823e reference manual motorola memory controller 15 15.5.4.2.4 general-purpose signals. the general-purpose (gpl [1:5]) signals have two bits in the ram word that define the logical value of the signal to be changed at the falling edge of gclk1 or gclk2. gpl0 has two 2-bit fields that perform the same function with additional phase control. gpl5 and gpl0 offer the following enhancements beyond the other gpl x signals: ? gpl5 can be controlled during phase 4 of the previous clock cycle according to the value of g5ls. ? gpl0 can be controlled by an address line that is specified in the g0clx field of the mxmr. to use this feature, you must set the g0h and g0l fields in the ram word. for example, if you have a simm with multiple banks, this address line can be used to switch between banks. figure 15-30. early gpl5 control clkout/gclk2 gclk1 ts ram word 1 ram word 2 gpl5 value controlled by g5ls value controlled by g5t4 and g5t3 on upm 412341 clock phase
memory controller motorola mpc823e reference manual 15-59 memory controller 15 memory controller 15 15.5.4.2.5 loop control. the loop bit in the ram word allows you to run a repetitive program fragment a specific number of times. the first time the loop bit is asserted in a ram word, the memory controller recognizes it as a loop start word. at this time, the memory loop counter is loaded with the corresponding contents of the loop field shown in table 15-6. see the appropriate machine mode register (mxmr) for more information. the next ram word encountered with the loop bit set is recognized as a loop end word. at this time, the memory loop counter is decremented by one. continued loop execution depends on the memory loop counter. if the loop counter is not zero, the next ram word executed is the loop start word. otherwise, the next ram word executed is the word following the loop end word. loops can be sequentially executed, but not nested. 15.5.4.2.6 exception handling. when an access to a memory device is initiated by the mpc823e under upm control, the external device may assert the tea , sreset , or hreset signal. an exception occurs when one of these signals is asserted by an external device and the mpc823e begins closing the memory cycle transfer. when an exception is recognized and the exen bit is set in the ram word, the next ram word will branch to the special exception start address (exs). see table 15-4 for more information. you must provide an exception handler to handle output signals controlled by the upm. for dram control, you would provide a handler that would negate ras and casx to prevent data corruption. the exen bit is similar to an exception mask in that if it is 0, then it defers the exception and continues executing. if a ram word is encountered with the exen bit set, the upm performs a branch to the exception start address. when the branch to the exception start address is performed, the upm continues reading until the last bit is set in the ram word. table 15-6. mxmr loop field usage request serviced mxmr loop field read single beat cycle rlfx read burst cycle rlfx write single beat cycle wlfx write burst cycle wlfx periodic timer expired tlfx
memory controller 15-60 mpc823e reference manual motorola memory controller 15 15.5.4.2.7 address multiplexing. you can control the address signals that go to the external bus. the ama and amb fields of the mxmr control how the address signals are multiplexed. the sam bit in the option register determines the address multiplexing for the first clock cycle. the amx field in the ram word determines the multiplexing for subsequent clock cycles. the lower address pins can be multiplexed between the internal upper or lower address signals. the sam bit outputs the upper address signals and the amx field outputs the lower address signals. using the amx field, you can output the contents of the memory address register (mar) on the address pins. see table 15-6 for general configuration. table 15-7 shows how the ama and amb fields can be defined to interface with a wide range of dram modules. figure 15-31 illustrates address multiplex timing. figure 15-31. address multiplex timing table 15-7. address multiplexing pins ama/amb a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 signals 000 res res a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 001 res a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 010 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 011 res a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 100 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 101 res a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 clkout/gclk2 gclk1 ts ram word 1 ram word 2 a[0:31] address controlled by sam address controlled by amx upper address lower address
memory controller motorola mpc823e reference manual 15-61 memory controller 15 memory controller 15 table 15-8. ama/amb definition for dram interface data bus width memory size number of dram row address pins number of dram column address pins mpc823e address pin connection ama/amb in mxmr 8 bits 64k 8 8 a24 - a31 000 128k 9 a23 - a31 256k 10 a22 - a31 512k 11 a21 - a31 1m 12 a20 - a31 2m 13 a19 - a31 4m 14 a18 - a31 256k 9 9 a23 - a31 001 512k 10 a22 - a31 1m 11 a21 - a31 2m 12 a20 - a31 4m 13 a19 - a31 8m 14 a18 - a31 16m 15 a17 - a31 1m 10 10 a22 - a31 010 2m 11 a21 - a31 4m 12 a20 - a31 8m 13 a19 - a31 16m 14 a18 - a31 32m 15 a17 - a31 64m 16 a16 - a31 4m 11 11 a21 - a31 011 8m 12 a20 - a31 16m 13 a19 - a31 32m 14 a18 - a31 64m 15 a17 - a31 16m 12 12 a20 - a31 100 32m 13 a19 - a31 64m 14 a18 - a31 128m 15 a17 - a31 256m 16 a16 - a31
memory controller 15-62 mpc823e reference manual motorola memory controller 15 8 bits 64m 13 13 a19 - a31 101 128m 14 a18 - a31 256m 15 a17 - a31 16 bits 128k 8 8 a23 - a30 000 256k 9 a22 - a30 512k 10 a21 - a30 1m 11 a20 - a30 2m 12 a19 - a30 4m 13 a18 - a30 512k 9 9 a22 - a30 001 1m 10 a21 - a30 2m 11 a20 - a30 4m 12 a19 - a30 8m 13 a18 - a30 16m 14 a17 - a30 2m 10 10 a21 - a30 010 4m 11 a20 - a30 8m 12 a19 - a30 16m 13 a18 - a30 32m 14 a17 - a30 64m 15 a16 - a30 8m 11 11 a20 - a30 011 16m 12 a19 - a30 32m 13 a18 - a30 64m 14 a17 - a30 32m 12 12 a19 - a30 100 64m 13 a18 - a30 128m 14 a17 - a30 256m 15 a16 - a30 128m 13 13 a18 - a30 101 256m 13 a17 - a30 table 15-8. ama/amb definition for dram interface (continued) data bus width memory size number of dram row address pins number of dram column address pins mpc823e address pin connection ama/amb in mxmr
memory controller motorola mpc823e reference manual 15-63 memory controller 15 memory controller 15 32 bits 256k 8 8 a22 - a29 000 512k 9 a21 - a29 1m 10 a20 - a29 2m 11 a19 - a29 4m 12 a18 - a29 1m 9 9 a21 - a29 001 2m 10 a20 - a29 4m 11 a19 - a29 8m 12 a18 - a29 16m 13 a17 - a29 4m 10 10 a20 - a29 010 8m 11 a19 - a29 16m 12 a18 - a29 32m 13 a17 - a29 64m 14 a16 - a29 16m 11 11 a19 - a29 011 32m 12 a18 - a29 64m 13 a17 - a29 64m 12 12 a18 - a29 100 128m 13 a17 - a29 256m 14 a16 - a29 256m 13 13 a17 - a29 101 table 15-8. ama/amb definition for dram interface (continued) data bus width memory size number of dram row address pins number of dram column address pins mpc823e address pin connection ama/amb in mxmr
memory controller 15-64 mpc823e reference manual motorola memory controller 15 15.5.4.2.8 transfer acknowledge and data sample control. during a memory access, the uta bit of the ram word controls the state of the ta signal sampled by the bus master. the ta signal is driven on the rising edge of gclk2. when a read access is handled by the upm and the uta bit is 0, the value of the dlt3 bit in the same ram word indicates when the data input is sampled by the bus master, assuming that the gplx4dis bit is set in the mxmr. figure 15-32 illustrates the data sampling that is controlled by the upm. 15.5.4.2.9 disable timer mechanism. the disable timer associated with each upm allows you to guarantee a minimum time between two successive accesses to the same memory bank. this feature is critical when dram requires a ras precharge time. the todt bit in the ram word turns the timer on to prevent another upm access to the same bank until the timer expires. the disable timer does not affect memory accesses to different banks. if the timing specified by the upm ram word is less than the disable timer period, the access to the next bank will conflict with the current bank access. to avoid conflicts between different banks using the same upm, the number of words in the ram array must be equal to or greater than the period defined in the dsx field of the mxmr. 15.5.4.2.10 last word. when the last bit is read in the ram word, the highest priority pending request (if any) is serviced immediately in the external memory transactions. if the disable timer is activated, the bus will be idle for a number of clock cycles, as specified in the dsx field of the mxmr. figure 15-32. upm read access data sampling to internal data bus gclk2 data bus multiplexer latch latch dlt3 and gplx4dis
memory controller motorola mpc823e reference manual 15-65 memory controller 15 memory controller 15 15.5.5 the wait mechanism if the upm reads a ram word with the waen bit set, the external upwaitx signal is sampled and synchronized by the memory controller and the current request is frozen. if the waen bit is asserted, the logical value of the external signals are frozen to the value defined in the last ram word accessed and the ram address increment is disabled until the upwaitx signal is negated. this allows wait states to be inserted as required by an external device through an external signal. a memory disable timer is associated with each upm. this timer counts down to zero starting at the value programmed in the dsx field in the mxmr. 15.5.5.1 internal and external synchronous master. figure 15-33 illustrates how the waen bit in the word read by the upm and the upwaitx signal is used to hold the upm in a particular state until the upwaitx signal is negated. as illustrated in figure 15-33, the csx and gpl1 states (c12 and f) and the waen value (cc) are frozen until the upwaitx signal is recognized as deasserted. figure 15-33. wait mechanism timing for internal and external synchronous masters clkout gclk1 gclk2 cs x gpl1 waen ram word n ram word n+1 a c1 c2 c3 c4 c5 c6 c7 c8 upwaitx b c d e f c9 c10 c11 c12 c13 c14 g ram word n+2 wait wait ram word n+3 ta aa bb cc dd
memory controller 15-66 mpc823e reference manual motorola memory controller 15 the upwaitx signal is sampled at the falling edge of the clkout. if the signal is asserted and the waen bit is set in the current ram word, the upm is frozen until the upwaitx signal is recognized as negated. the value of the external pins driven by the upm remains as indicated in the word previously read by the upm. when the upwaitx signal is negated, the upm continues with its normal functions. notice that during the wait cycles, the ta signal is negated by the upm. 15.5.5.2 external asynchronous master. the upm supports asynchronous external masters using the as signal. when you use an external asynchronous master, the as signal behaves like the upwaitx signal. the upm enters a wait state if the as signal is asserted and the waen bit is set in the current ram word. as illustrated in figure 15-34, the csx and gpl1 states (c12 and f) and the waen value (cc) are frozen until the as signal is recognized as deasserted. the ta signal that is driven by the upm remains in its previous value until the as signal is negated. the state of the external pins driven by the upm remains as indicated in the word previously read by the upm. to exit a wait state, the as signal must be negated. when as is negated, all external signals controlled by the upm are driven high. the external signals are driven in this state until the last bit is set in a ram word. the todt bit of the ram word is only relevant in the words read by the upm after the as signal is negated. refer to section 15.6 external master support for more information. figure 15-34. wait mechanism timing for an external asynchronous master clkout gclk1 gclk2 cs x gpl1 waen ram word n ram word n+1 a c1 c2 c3 c4 c5 c6 c7 c8 as b c d e f c9 c10 c11 c12 ram word n+2 wait wait ram word n+3 ta aa bb cc dd
memory controller motorola mpc823e reference manual 15-67 memory controller 15 memory controller 15 15.5.5.3 handling variable access time and slow devices. the memory controller provides two different mechanisms to interface with slave devices that are either very slow or cannot guarantee a predefined access timethe wait state and the external ta signal. these devices can be divided into two main types: ? variable access time devices (fifo, hierarchical bus interface, dual-port memory devices) ? slow devices (access time is greater than the maximum allowed by the upm) the wait mechanism is used only in accesses that are controlled by the upm. the gplx4dis bit of the mxmr enables this mechanism. the external ta mechanism is used only in accesses that are controlled by the gpcm. the seta bit in the option register specifies whether ta is generated internally or externally. 15.5.5.3.1 hierarchical bus interface example. on the local bus, the cpu initiates a read cycle that addresses the main storage connected to the system bus. the hierarchical bus interface accepts the local bus request and generates a read cycle on the system bus. you cannot foresee when the data will be valid to be latched by the cpu, since the system bus may be occupied by the dma. ? the wait solutionthe external module signals to the memory controller that the data is not ready by asserting the upwaitx signal. the memory controller synchronized this signal because it is an asynchronous signal. as a result of the upwaitx signal being asserted, the upm will enter a freeze mode at the falling edge of the clkout upon encountering the waen bit being set in the upm word. the upm will remain in that state until the upwaitx signal is asserted. after the negation of upwaitx, the upm will continue executing from the next entry to the end of the pattern (last bit is set). ? the external ta solutionthe bus interface module signals to the memory controller when it can sample the data by asserting the synchronous ta signal. 15.5.5.3.2 slow device interface example. the cpu initiates a read cycle from slow devices whose access time is greater than the maximum allowed by your programming model. ? the wait solutionthe cpu generates a read access from the slow device. the device will react by asserting the upwaitx signal as long as the data is not ready. the cpu will sample the data only after the negation of the upwaitx signal. ? the external ta solutionthe cpu generates a read access from the slow device. when it is ready, the device is responsible for generating the synchronous ta signal.
memory controller 15-68 mpc823e reference manual motorola memory controller 15 15.6 external master support the memory controller supports internal and external bus masters. accesses that originate from the core, cpm, and lcd controller are considered internal and those initiated by an external bus master are external. external bus master support can be enabled in the siu module configuration register (siumcr), as indicated in section 12.12.1.1 siu module configuration register . there are two types of external bus masters: ? synchronous bus masters, which synchronize with clkout and may use the mpc823e memory controller to access a slave device or bypass the memory controller to perform the slave access. ? asynchronous bus masters, which use an address strobe (as ) signal that handshakes with the mpc823e memory controller to access a slave device or bypass the memory controller to perform the slave access. synchronous masters initiate a transfer by asserting the ts signal. the a[6:31], rd/wr , and tsizx signals must be stable prior to the rising edge of clkout after ts assertion and until the last ta signal is negated. since the external master operates synchronously with the mpc823e, proper setup and hold times for all inputs associated with the rising edge of clkout are significant. to support synchronous mode using the memory controller, the seme bit in the siumcr must be set. when the ts signal is asserted, the memory controller compares the address with each one of its defined valid banks and if a match is found, control signals to the slave device are generated and the ta signal is supplied to the external master. if the seme bit is cleared, the memory controller is bypassed and the external synchronous master must provide control signals to the slave device. see figure 15-35 for details. asynchronous masters initiate a transfer by driving the address bus and asserting the as pin. the a[6:31] signals, together with rd/wr and tsizx, must have a proper setup time prior to as pin assertion. to support asynchronous mode using the memory controller, the aeme bit in the siumcr must be set. the memory controller synchronizes as assertion to its internal clock and generates the control signals to the slave device. when the as pin is synchronized, the memory controller compares the address with each one of its defined valid banks and if a match is found, control signals to the slave device are generated and the ta signal is supplied to the external master. all the control signals to the memory device and the ta signal are negated with as pin negation. if the aeme bit is cleared, the memory controller is bypassed and the external asynchronous master must provide control signals to the slave device. in this mode, the as pin of the mpc823e is not available as an input. see figure 15-36 for details. note: when external masters access slaves on the bus, the internal at[0:2] signals reaching the memory controller will be forced to 100. you must make sure this access matches the at field in the base register after it is masked by the atm field in the option register.
memory controller motorola mpc823e reference manual 15-69 memory controller 15 memory controller 15 the a[28:20] pins must be used to generate addresses to memory devices during burst accesses. they duplicate the value of the a[28:20] signals when an internal master initiates a transaction on the external bus. when an external master initiates a transaction on the external bus, the a[28:20] pins reflect the value of the a[28:20] pins on the first clock cycle of the memory access. on subsequent clock cycles, the behavior of the a[28:20] pins depends on the configuration of the upm. figure 15-35. synchronous external master access clkout a[6:27] cs x we x oe data ts ta address match and compare memory device access rd/ wr burst tsizex a[28:31]
memory controller 15-70 mpc823e reference manual motorola memory controller 15 to connect to external memory devices that require address multiplexing, use the gpl_x5 pin. the state of the gpl_x5 signal logic value depends on the configuration defined in table 15-9. the gpl_x5 pin reflects the value of the g5ls bit of the corresponding option register in the first clock cycle of the slave device access. in subsequent clock cycles, the state of gpl_x5 is determined by the g5t4 and g5t3 bits in the ram word. if the upmb controls the slave access, you can use the g5la bit of the option register to select the active gpl_x5 signal. g5ls only applies to memory requests and not ram words executed by internal/external software, exception, or memory periodic timer requests. figure 15-36. asynchronous external master access clkout a[6:27] cs x we x oe data as ta address match and compare memory device access rd/ wr tsizex a[28:31]
memory controller motorola mpc823e reference manual 15-71 memory controller 15 memory controller 15 table 15-9. gpl_x5 signal (pin) behavior machine controlling the memory access machine controlling the slave access clock cycle g5la (orx) g5ls (orx) g5t4 (ram word) g5t3 (ram word) gpl_ x 5 behavior at the controlling clock edge gpcm x n/a n/a x x gpl_a5 and gpl_b5 do not change their value. upma first x 0 x x gpl_a5 is driven low at the falling edge of gclk1. 1 gpl_a5 is driven high at the falling edge of gclk1. second, third... x x 0 x gpl_a5 is driven low at the falling edge of gclk2 in the current upm cycle. 1 x gpl_a5 is driven high at the falling edge of gclk2 in the current upm cycle. x 0 gpl_a5 is driven low at the falling edge of gclk1 in the current upm cycle. x 1 gpl_a5 is driven high at the falling edge of gclk1 in the current upm cycle. upmb first 0 0 x x gpl_b5 is driven low at the falling edge of gclk1. 1 gpl_b5 is driven high at the falling edge of gclk1. 1 0 x x gpl_a5 is driven low at the falling edge of gclk1. 1 gpl_a5 is driven high at the falling edge of gclk1. second, third... 0 x 0 x gpl_b5 is driven low at the falling edge of gclk2 in the current upm cycle. 1 x gpl_b5 is driven high at the falling edge of gclk2 in the current upm cycle. x 0 gpl_b5 is driven low at the falling edge of gclk1 in the current upm cycle. x 1 gpl_b5 is driven high at the falling edge of gclk1 in the current upm cycle. upmb second, third... 1 x 0 x gpl_a5 is driven low at the falling edge of gclk2 in the current upm cycle. 1 x gpl_a5 is driven high at the falling edge of gclk2 in the current upm cycle. x 0 gpl_a5 is driven low at the falling edge of gclk1 in the current upm cycle. x 1 gpl_a5 is driven high at the falling edge of gclk1 in the current upm cycle.
memory controller 15-72 mpc823e reference manual motorola memory controller 15 15.6.1 external master examples a synchronous example interconnection in which an external master and the mpc823e can both share access to a dram bank is illustrated in figure 15-37. notice that cs1 , upma, and gpl_a5 were chosen to assist in the control of dram bank accesses. to perform burst accesses initiated by the external master or mpc823e using this configuration, the a[28:30] signals are connected to the multiplexer controlled by gpl_a5 . figure 15-38 illustrates the timing behavior of control signals when an external master to a dram bank initiates a burst read access. the state of the gpl_a5 pin in the first clock cycle of the memory device access is determined by the value of the g5ls bit in the corresponding option register. in this example, the accessed critical word is addressed at a[28:29] = 10, which then increments and wraps around to the word before the critical word (01) for subsequent beats of this burst access. figure 15-37. synchronous external master interconnect example gpl_a5 r/w a[6:31] bs x cs1 ts burst ta tsizx bi br bg bb d[0:31] dram multiplexer bank external master mpc823e
memory controller motorola mpc823e reference manual 15-73 memory controller 15 memory controller 15 figure 15-38. synchronous external masterCburst read access to page mode dram cst4 (bit 0) 000000000 cst1 (bit 1) 000000000 cst2 (bit 2) 000000001 cst3 (bit 3) 000000001 bst4 (bit 4) 110101010 bst1 (bit 5) 100000000 bst2 (bit 6) 101010101 bst3 (bit 7) 101010101 g0l0 (bit 8) ? g5t4 (bit 20) 011111111 g5t3 (bit 21) 000000000 - (bit 22) - (bit 23) loop (bit 24) 000000000 exen (bit 25) 001010100 amx0 (bit 26) 000000000 amx1 (bit 27) 000000000 na (bit 28) 001010100 uta (bit 29) 101010101 todt (bit 30) 000000001 last (bit 31) 000000001 rbs rbs+1 rbs+2 rbs+3 rbs+4 rbs+5 rbs+6 rbs+7 rbs+8 clkout gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs [0:3] ( cas [0:3]) ( ras ) burst a[28:29] gpl_a5 10 11 00 01
memory controller 15-74 mpc823e reference manual motorola memory controller 15 an asynchronous example interconnection in which an external master and the mpc823e can both share access to a dram bank is illustrated in figure 15-39. notice that cs1 , upma, and gpl_a5 were chosen to assist in the control of dram bank accesses. figure 15-40 illustrates the timing behavior of the gpl_a5 and other control signals when an external master to a dram bank initiates a single beat read access. the state of the gpl_a5 pin in the first clock cycle of the memory device access is determined by the value of the g5ls bit in the corresponding option register. figure 15-39. asynchronous external master interconnect example r/w a[6:31] bs x cs1 as d[0:31] dram multiplexer gpl_a5 ta tsizx br bg bb arbitration signals external master external arbiter mpc823e
memory controller motorola mpc823e reference manual 15-75 memory controller 15 memory controller 15 figure 15-40. asynchronous external master timing example cst4 bit 0 0 0 0 0 0 cst1 bit 1 0 0 0 cst2 bit 2 0 0 1 cst3 bit 3 0 0 1 bst4 bit 4 1 1 0 0 0 bst1 bit 5 1 0 0 bst2 bit 6 1 0 1 bst3 bit 7 1 0 1 ? g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 1 1 g5t3 bit 21 0 1 1 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 exen bit 25 0 0 0 0 0 amx0 bit 26 0 0 0 0 1 amx1 bit 27 0 0 0 0 0 na bit 28 0 0 0 0 0 uta bit 29 1 0 0 0 1 todt bit 30 0 0 0 0 1 last bit 31 0 0 0 0 1 rss rss+1 wait wait rss+2 clkout/gclk2 gclk1 a[6:31] as rd/ wr d[0:31] ta cs x bs_ x ( cas [0:3]) ( ras ) gpl_ x 5
memory controller 15-76 mpc823e reference manual motorola memory controller 15 15.7 memory system interface examples the following examples illustrate how to connect and set up the upm ram array for two types of drampage mode dram and page mode extended data out dram. the values used in these examples apply to either upma or upmb. upma is used in the page mode example and upmb is used in the extended data out example. 15.7.1 page mode dram interface example the configuration for a 1m, 32-bit wide memory system using four 256k x 8-bit drams is illustrated in figure 15-41. also shown is the physical connection between upma and the page mode dram. the cs1 signal is connected to all the ras signals and controlled by the base register. the bs_a [0:3] signals are mapped one-to-one to each of the four drams and are controlled by the upm ram word. the refresh rate is calculated based on a 25mhz baud rate generator clock and the dram that requires a 512-cycle refresh every 8ms. follow these steps to configure a system for page mode dram: 1. determine the system architecture, which includes the mpc823e and the memory system as shown in the example in figure 15-41. 2. use the blank worksheet (figure 15-58) to draw the timing diagrams for all the memory cycles associated with your architecture. you can also use, as a reference, the various timing diagrams in figure 15-42 through figure 15-50. mpc823e figure 15-41. page mode dram interface connection ras cas x w mcm84256 256k x 8 8 a[0:8] d[0:7] ras cas x w mcm84256 256k x 8 8 a[0:8] d[0:7] bs_a [0:3] cs1 r/w a[21:29] d[0:31] ras cas x w mcm84256 256k x 8 8 a[0:8] d[0:7] ras cas x w mcm84256 256k x 8 8 a[0:8] d[0:7] d[0:7] d[8:15] d[16:23] d[24:31] bs_a0 bs_a1 bs_a2 bs_a3
memory controller motorola mpc823e reference manual 15-77 memory controller 15 memory controller 15 3. translate the timing diagrams into ram words for each type of memory access. the bottom half of the figures represent the ram array contents that handle each of the possible cycles and each column represents a different word in the ram array. a blank cell in each figure indicates a dont care bit, which is typically programmed to logic 1 to conserve power. 4. define the upma (or upmb) parameters that control the memory system in the following sequence. for additional details, see table 15-10. program the ram array using the memory command register (mcr) and memory data register (mdr). the ram word must be written into the mdr before you issue the write command to the mcr. repeat this step for all ram word entries. initialize the option and base registers of the specific bank according to the address mapping of the dram device you have chosen. use the ms field of the option register to select the machine you have chosen to control the cycles. notice that the sam bit in the option register determines address multiplexing for the first clock cycle and subsequent cycles are controlled by the upm ram words. also notice that the amx field in the upm ram word controls the address multiplexing for the next clock cycle rather than the current cycle. program the mamr to select the number of columns and refresh timer parameters. table 15-10. upma register settings field register value comments ms br1 10 selects upma ps br1 00 selects 32-bit bus width wp br1 0 allows read and write accesses ptp mptpr 00000010 prescaler divided by two pta mamr 00001100 15.6 m s at a 25mhz clock ptae mamr 1 enables periodic timer a ama mamr 001 selects nine column address pins dsa mamr 01 selects two disable timer clock cycles gpla4dis mamr 0 disables the upwaita signal rlfa mamr 0011 selects three loop iterations for read wlfa mamr 0011 selects three loop iterations for write sam or1 1 selects column address on first cycle bi or1 0 supports burst accesses
memory controller 15-78 mpc823e reference manual motorola memory controller 15 figure 15-42. single beat read access to page mode dram cst4 bit 0 0 0 0 cst1 bit 1 0 0 0 cst2 bit 2 0 0 1 cst3 bit 3 0 0 1 bst4 bit 4 1 1 0 bst1 bit 5 1 0 0 bst2 bit 6 1 0 1 bst3 bit 7 1 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 exen bit 25 0 0 0 amx0 bit 26 0 0 1 amx1 bit 27 0 0 0 na bit 28 0 0 0 uta bit 29 1 0 1 todt bit 30 0 0 1 last bit 31 0 0 1 rss rss+1 rss+2 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] row column (cas [0:3]) ( ras )
memory controller motorola mpc823e reference manual 15-79 memory controller 15 memory controller 15 figure 15-43. single beat write access to page mode dram cst4 bit 0 0 0 0 cst1 bit 1 0 0 0 cst2 bit 2 0 0 1 cst3 bit 3 0 0 1 bst4 bit 4 1 1 0 bst1 bit 5 1 0 0 bst2 bit 6 1 0 1 bst3 bit 7 1 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 exen bit 25 0 0 0 amx0 bit 26 0 0 0 amx1 bit 27 0 0 0 na bit 28 0 0 0 uta bit 29 1 0 1 todt bit 30 0 0 1 last bit 31 0 0 1 wss wss+1 wss+2 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] ( cas [0:3]) ( ras ) row column
memory controller 15-80 mpc823e reference manual motorola memory controller 15 figure 15-44. burst read access to page mode dram (no loop) cst4 bit 0 0 00000000 cst1 bit 1 0 00000000 cst2 bit 2 0 00000001 cst3 bit 3 0 00000001 bst4 bit 4 1 10101010 bst1 bit 5 1 00000000 bst2 bit 6 1 01010101 bst3 bit 7 1 01010101 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 00000000 exen bit 25 0 01010100 amx0 bit 26 0 00000001 amx1 bit 27 0 00000000 na bit 28 0 01010100 uta bit 29 1 01010101 todt bit 30 0 00000001 last bit 31 0 00000001 rbs rbs+1 rbs+2 rbs+3 rbs+4 rbs+5 rbs+6 rbs+7 rbs+8 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] row column 1 column 2 column 3 column 4 ( cas [0:3]) ( ras )
memory controller motorola mpc823e reference manual 15-81 memory controller 15 memory controller 15 figure 15-45. burst read access to page mode dram (loop) cst4 bit 0 0 0 000 cst1 bit 1 0 0 000 cst2 bit 2 0 0 001 cst3 bit 3 0 0 001 bst4 bit 4 1 1 010 bst1 bit 5 1 0 000 bst2 bit 6 1 0 101 bst3 bit 7 1 0 101 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 1 100 exen bit 25 0 0 100 amx0 bit 26 0 0 001 amx1 bit 27 0 0 000 na bit 28 0 0 100 uta bit 29 1 0 101 todt bit 30 0 0 001 last bit 31 0 0 001 rbs rbs+1 rbs+2 rbs+3 rbs+4 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] row column 1 column 2 column 3 column 4 ( cas [0:3]) ( ras )
memory controller 15-82 mpc823e reference manual motorola memory controller 15 figure 15-46. burst write access to page mode dram (no loop) cst4 bit 0 0 0 0 0 0 0 0 0 0 cst1 bit 1 0 0 0 0 0 0 0 0 0 cst2 bit 2 0 0 0 0 0 0 0 0 1 cst3 bit 3 0 0 0 0 0 0 0 0 1 bst4 bit 4 1 1 0 1 0 1 0 1 0 bst1 bit 5 1 0 0 0 0 0 0 0 0 bst2 bit 6 1 0 1 0 1 0 1 0 1 bst3 bit 7 1 0 1 0 1 0 1 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 0 0 0 0 exen bit 25 0 0 1 0 1 0 1 0 0 amx0 bit 26 0 0 0 0 0 0 0 0 1 amx1 bit 27 0 0 0 0 0 0 0 0 0 na bit 28 0 0 1 0 1 0 1 0 0 uta bit 29 1 0 1 0 1 0 1 0 1 todt bit 30 0 0 0 0 0 0 0 0 1 last bit 31 0 0 0 0 0 0 0 0 1 wbs wbs+1 wbs+2 wbs+3 wbs+4 wbs+5 wbs+6 wbs+7 wbs+8 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] row column 1 column 2 column 3 column 4 ( ras ) ( cas [0:3])
memory controller motorola mpc823e reference manual 15-83 memory controller 15 memory controller 15 figure 15-47. burst write access to page mode dram (loop) cst4 bit 0 0 0 000 cst1 bit 1 0 0 000 cst2 bit 2 0 0 001 cst3 bit 3 0 0 001 bst4 bit 4 1 1 010 bst1 bit 5 1 0 000 bst2 bit 6 1 0 101 bst3 bit 7 1 0 101 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 1 100 exen bit 25 0 0 100 amx0 bit 26 0 0 001 amx1 bit 27 0 0 000 na bit 28 0 0 100 uta bit 29 1 0 101 todt bit 30 0 0 001 last bit 31 0 0 001 wbs wbs+1 wbs+2 wbs+3 wbs+4 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] row column 1 column 2 column 3 column 4 ( ras ) ( cas [0:3])
memory controller 15-84 mpc823e reference manual motorola memory controller 15 figure 15-48. refresh cycle (cas before ras) to page mode dram cst4 bit 0 1 0 0 cst1 bit 1 1 0 0 cst2 bit 2 1 0 1 cst3 bit 3 1 0 1 bst4 bit 4 1 0 0 bst1 bit 5 0 0 0 bst2 bit 6 0 0 1 bst3 bit 7 0 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 exen bit 25 0 0 0 amx0 bit 26 0 0 1 amx1 bit 27 0 0 0 na bit 28 0 0 0 uta bit 29 1 1 1 todt bit 30 0 0 1 last bit 31 0 0 1 pts pts+1 pts+2 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] ( cas [0:3]) ( ras )
memory controller motorola mpc823e reference manual 15-85 memory controller 15 memory controller 15 figure 15-49. exception cycle cst4 bit 0 1 cst1 bit 1 1 cst2 bit 2 1 cst3 bit 3 1 bst4 bit 4 1 bst1 bit 5 1 bst2 bit 6 1 bst3 bit 7 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 exen bit 25 0 amx0 bit 26 0 amx1 bit 27 0 na bit 28 0 uta bit 29 1 todt bit 30 1 last bit 31 1 exs clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] ( cas [0:3]) ( ras )
memory controller 15-86 mpc823e reference manual motorola memory controller 15 you can significantly increase the performance of a page read access when you set gpla4dis to 1 in the mamr and ignore the gpl_a4 pin. the processor samples the data bus at the falling edge of gclk1 when the ta signal is asserted. figure 15-50 illustrates how to modify the burst read access to page mode dram (no loop) using this feature. during the four consecutive data beats, the ta signal in the figure is asserted to ensure a data transfer on every data clock. the figure also illustrates how the nine cycles of the burst read access shown in figure 15-43 can be reduced to 6 clock cycles (for 32-bit port size memory). you can reduce the cycles by using faster dram or a slower system clock that meets the dram access time. when a 16-bit port size memory is connected, the reduction is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles.
memory controller motorola mpc823e reference manual 15-87 memory controller 15 memory controller 15 figure 15-50. optimized dram burst read access cst4 bit 0 0 0 0 0 0 1 cst1 bit 1 0 0 0 0 0 1 cst2 bit 2 0 0 0 0 0 1 cst3 bit 3 0 0 0 0 0 1 bst4 bit 4 1 1 1 1 1 1 bst1 bit 5 1 0 0 0 0 1 bst2 bit 6 1 0 0 0 0 1 bst3 bit 7 1 0 0 0 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 dlt3 bit 18 1 1 1 1 1 1 g4t3 bit 19 0 0 0 0 0 0 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 0 exen bit 25 0 0 0 0 0 0 amx0 bit 26 0 0 0 0 1 1 amx1 bit 27 0 0 0 0 0 0 na bit 28 0 1 1 1 0 0 uta bit 29 1 0 1 0 0 1 todt bit 30 0 0 0 0 0 1 last bit 31 0 0 0 0 0 1 rbs rbs+1 rbs+2 rbs+3 rbs+4 rbs+5 clkout/gclk2 gclk1 a[6:31] ts rd/ wr d[0:31] ta cs1 bs_a [0:3] row col 1 ( cas [0:3]) ( ras ) col 2 col 3 col 4 d1 d2 d3 d4
memory controller 15-88 mpc823e reference manual motorola memory controller 15 15.7.2 page mode extended data-out dram interface example the configuration for a 1m, 32-bit wide memory system using two 256k x 16-bit page mode extended data-out (edo) drams is illustrated in figure 15-51. also shown is the physical connection between upmb and the edo drams. the cs2 signal that is controlled by the base register is connected to both of the ras signals. the bs_b [0:1] signals are mapped to the lower dram (d[0:15]) and the bs_b [2:3] signals are mapped to the upper dram (d[16:31]). for this connection, gpl_b1 is connected to the memory device oe pins. the refresh rate is calculated based on a 25mhz baud rate generator clock and the dram that requires a 512-cycle refresh every 8ms. follow these steps to configure a system for edo dram: 1. determine the system architecture, which includes the mpc823e and the memory system as shown in the example in figure 15-52. 2. use the blank worksheet (figure 15-58) to draw the timing diagrams for all the memory cycles associated with your architecture. you can also use, as a reference, the various timing diagrams in figure 15-52 through figure 15-57. 3. translate the timing diagrams into ram words for each type of memory access. the bottom half of the figures represent the ram array contents that handle each of the possible cycles and each column represents a different word in the ram array. a blank cell in each figure indicates a dont care bit, which is typically programmed to logic 1 to conserve power. mpc823e figure 15-51. edo dram interface connection ras casl we mt4c16270 256k x 16 16 a[0:8] d[0:15] bs_b [0:3] cs2 r/w a[21:29] d[0:31] gpl_b1 oe 2 2 16 ras casl we mt4c16270 256k x 16 a[0:8] d[0:15] oe d[16:31] d[0:15] cash cash bs_b0 bs_b1 bs_b3 bs_b2
memory controller motorola mpc823e reference manual 15-89 memory controller 15 memory controller 15 4. define the upmb (or upma) parameters that control the memory system in the following sequence. for additional details, see table 15-11. program the ram array using the memory command register (mcr) and memory data register (mdr). the ram word must be written into the mdr before you issue the write command to the mcr. repeat this step for all ram word entries. initialize the option and base registers of the specific bank according to the address mapping of the dram device you have chosen. use the ms field of the option register to select the machine you have chosen to control the cycles. notice that the sam bit in the option register determines address multiplexing for the first clock cycle and subsequent cycles are controlled by the upm ram words. also notice that the amx field in the upm ram word controls the address multiplexing for the next clock cycle rather than the current cycle. program the mbmr to select the number of columns and refresh timer parameters. table 15-11. upmb register settings field register value comments ms br2 10 selects upmb ps br2 00 selects 32-bit bus width wp br2 0 allows read and write accesses ptp mptpr 00000010 prescaler divided by 32 ptb mbmr 00001100 15.6 m s at a 25mhz clock ptbe mbmr 1 enables periodic timer b amb mbmr 001 selects nine column address pins dsb mbmr 01 selects two disable timer clock cycles gplb4dis mbmr 0 disables the upwaitb signal rlfb mbmr 0011 selects three loop iterations for read wlfb mbmr 0011 selects three loop iterations for write sam or2 1 selects column address on first cycle bi or2 0 supports burst accesses
memory controller 15-90 mpc823e reference manual motorola memory controller 15 figure 15-52. edo dram single beat read access cst4 bit 0 0 0 0 0 0 cst1 bit 1 0 0 0 0 0 cst2 bit 2 0 0 0 0 1 cst3 bit 3 0 0 0 0 1 bst4 bit 4 1 1 0 0 0 bst1 bit 5 1 0 0 0 0 bst2 bit 6 1 0 0 0 1 bst3 bit 7 1 0 0 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 0 0 0 0 0 g1t3 bit 13 0 0 0 0 1 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 exen bit 25 0 0 0 0 0 amx0 bit 26 0 0 0 0 1 amx1 bit 27 0 0 0 0 0 na bit 28 0 0 0 0 0 uta bit 29 1 1 1 0 1 todt bit 30 0 0 0 0 1 last bit 31 0 0 0 0 1 rss rss+1 rss+2 rss+3 rss+4 clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs2 bs_b [0:3] row column 1 ( cas [0:3]) ( ras ) gpl_b1 ( oe )
memory controller motorola mpc823e reference manual 15-91 memory controller 15 memory controller 15 figure 15-53. edo dram single beat write access cst4 bit 0 0 0 0 1 cst1 bit 1 0 0 0 1 cst2 bit 2 0 0 1 1 cst3 bit 3 0 0 1 1 bst4 bit 4 1 1 0 0 bst1 bit 5 1 0 0 0 bst2 bit 6 1 0 0 0 bst3 bit 7 1 0 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 1 1 1 1 g1t3 bit 13 1 1 1 1 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 exen bit 25 0 0 0 0 amx0 bit 26 0 0 0 1 amx1 bit 27 0 0 0 0 na bit 28 0 0 0 0 uta bit 29 1 1 0 1 todt bit 30 0 0 0 1 last bit 31 0 0 0 1 wss wss+1 wss+2 wss+3 clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs2 bs_b [0:3] row column 1 ( cas [0:3]) ( ras ) gpl_b1 ( oe )
memory controller 15-92 mpc823e reference manual motorola memory controller 15 figure 15-54. edo dram burst read access cst4 bit 0 0 0 0 0 0 0 0 0 0 0 0 cst1 bit 1 0 0 0 0 0 0 0 0 0 0 0 cst2 bit 2 0 0 0 0 0 0 0 0 0 0 1 cst3 bit 3 0 0 0 0 0 0 0 0 0 0 1 bst4 bit 4 1 1 0 1 1 0 1 0 1 0 1 bst1 bit 5 1 0 0 1 1 0 1 0 1 0 1 bst2 bit 6 1 0 0 1 0 1 0 1 0 1 1 bst3 bit 7 1 0 0 1 0 1 0 1 0 1 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 0 0 0 0 0 0 0 0 0 0 0 g1t3 bit 13 0 0 0 0 0 0 0 0 0 0 1 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 0 0 0 0 0 0 exen bit 25 0 0 0 1 0 1 0 1 0 0 0 amx0 bit 26 0 0 0 0 0 0 0 0 0 0 1 amx1 bit 27 0 0 0 0 0 0 0 0 0 0 0 na bit 28 0 0 1 0 0 1 0 1 0 0 0 uta bit 29 1 1 1 0 1 0 1 0 1 0 1 todt bit 30 0 0 0 0 0 0 0 0 0 0 1 last bit 31 0 0 0 0 0 0 0 0 0 0 1 rbs rbs+1 rbs+2 rbs+3 rbs+4 rbs+5 rbs+6 rbs+7 rbs+8 rbs+9 rbs+10 clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs2 bs_b [0:3] row column 1 ( cas [0:3]) ( ras ) gpl_b1 ( oe ) column 2 column 3 column 4
memory controller motorola mpc823e reference manual 15-93 memory controller 15 memory controller 15 figure 15-55. edo dram burst write access cst4 bit 0 0 0 0 0 0 0 0 0 0 0 cst1 bit 1 0 0 0 0 0 0 0 0 0 0 cst2 bit 2 0 0 0 0 0 0 0 0 0 1 cst3 bit 3 0 0 0 0 0 0 0 0 0 1 bst4 bit 4 1 1 0 0 0 0 0 1 0 1 bst1 bit 5 1 0 0 0 0 1 0 1 0 1 bst2 bit 6 1 0 0 1 0 1 0 1 0 1 bst3 bit 7 1 0 0 1 0 1 0 1 0 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 1 1 1 1 1 1 1 1 1 1 g1t3 bit 13 1 1 1 1 1 1 1 1 1 1 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 0 0 0 0 0 exen bit 25 0 0 0 1 0 1 0 1 0 0 amx0 bit 26 0 0 0 0 0 0 0 0 0 1 amx1 bit 27 0 0 0 0 0 0 0 0 0 0 na bit 28 0 0 0 1 0 1 0 1 0 0 uta bit 29 1 0 1 1 0 1 0 1 0 1 todt bit 30 0 0 0 0 0 0 0 0 0 1 last bit 31 0 0 0 0 0 0 0 0 0 1 wbs wbs+1 wbs+2 wbs+3 wbs+4 wbs+5 wbs+6 wbs+7 wbs+8 wbs+9 clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs2 bs_b [0:3] row column 1 ( cas [0:3]) ( ras ) gpl_b1 ( oe ) column 2 column 3 column 4
memory controller 15-94 mpc823e reference manual motorola memory controller 15 figure 15-56. edo dram refresh cycle (cas before ras) cst4 bit 0 1 0 0 0 1 cst1 bit 1 1 0 0 0 1 cst2 bit 2 0 0 0 0 1 cst3 bit 3 0 0 0 0 1 bst4 bit 4 0 0 1 1 1 bst1 bit 5 0 1 1 1 1 bst2 bit 6 0 1 1 1 1 bst3 bit 7 0 1 1 1 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 1 1 1 1 1 g1t3 bit 13 1 1 1 1 1 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 0 0 0 0 exen bit 25 0 0 0 0 0 amx0 bit 26 0 0 0 0 1 amx1 bit 27 0 0 0 0 0 na bit 28 0 0 0 0 0 uta bit 29 1 1 1 1 1 todt bit 30 0 0 0 0 1 last bit 31 0 0 0 0 1 pts pts+1 pts+2 pts+3 pts+4 clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs2 bs_b [0:3] ( cas [0:3]) ( ras ) gpl_b1 ( oe )
memory controller motorola mpc823e reference manual 15-95 memory controller 15 memory controller 15 figure 15-57. edo dram exception cycle cst4 bit 0 1 cst1 bit 1 1 cst2 bit 2 1 cst3 bit 3 1 bst4 bit 4 1 bst1 bit 5 1 bst2 bit 6 1 bst3 bit 7 1 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 1 g1t3 bit 13 1 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 0 exen bit 25 0 amx0 bit 26 0 amx1 bit 27 0 na bit 28 0 uta bit 29 1 todt bit 30 1 last bit 31 1 exs clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs2 bs_b [0:3] ( cas [0:3]) ( ras ) gpl_b1 ( oe )
memory controller 15-96 mpc823e reference manual motorola memory controller 15 figure 15-58. blank worksheet for a upm cst4 bit 0 cst1 bit 1 cst2 bit 2 cst3 bit 3 bst4 bit 4 bst1 bit 5 bst2 bit 6 bst3 bit 7 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t4 bit 12 g1t3 bit 13 g2t4 bit 14 g2t3 bit 15 g3t4 bit 16 g3t3 bit 17 g4t4 bit 18 g4t3 bit 19 g5t4 bit 20 g5t3 bit 21 - bit 22 - bit 23 loop bit 24 exen bit 25 amx0 bit 26 amx1 bit 27 na bit 28 uta bit 29 todt bit 30 last bit 31 xxs xxs+1 xxs+2 xxs+3 xxs+4 xx+5 xxs+6 xxs+7 xxs+8 clkout/gclk2 gclk1 a[6:31] rd/ wr d[0:31] ta cs x bs_ x [0:3] ( cas [0:3]) ( ras ) gpl_ x 1 ( oe )
motorola mpc823e reference manual 16-1 communication 16 processor module section 16 communication processor module the mpc823e communication processor module (cpm) provides a flexible and integrated approach to communication-intensive environments. to reduce system frequency and save power, the communication processor module has its own independent risc microcontroller that is optimized and tuned to handle serial communications. the communication processor module offloads the core in the following ways: ? by reducing the interrupt rate. the core is interrupted only upon frame reception or transmission, instead of on a per-character basis. ? by implementing some of the layer-2 multiply-and-accumulate processing, which provides more cpu bandwidth for higher layer processing. ? by supporting multibuffer memory data structures that are convenient for software handling. 16.1 features the following is a list of the communication processor modules main features. for quick reference purposes, the superscripted number following each item below is the page number where the feature is described. ? 32-bit risc microcontroller 4 ? flexibility of four general-purpose 16-bit timers or two 32-bit timers 74 ? a serial interface with a time-slot assigner 112 ? four independent baud rate generators 157 ? two full-duplex serial communication controllers (scc2 and scc3) 163 ? a universal serial bus controller 350 ? two full-duplex serial management controllers (smcs) 382 ? serial peripheral interface (spi) support for master or slave 433 ?i 2 c bus controller support for master or slave 456 ? general-purpose parallel interface ports with open-drain capability 477 ? communication processor module interrupt controller with flexible priorities 499
communication processor module 16-2 mpc823e reference manual motorola communication 16 processor module the following blocks and protocols contain primary programming functionalities that use parameter ram tables as their communication interface. ? risc microcontroller o dual port ram o risc timer table o dsp functions o independent dma ? serial communication controllers o uart protocol o hdlc protocol o appletalk/localtalk protocol o asynchronous hdlc protocol o infra-red protocols (scc2 only) o transparent protocol o ethernet protocol ? universal serial bus controller ? serial management controllers o uart protocol o transparent protocol o gci protocol ? serial peripheral interface ?i 2 c bus controller ? general-purpose parallel interface ports
communication processor module motorola mpc823e reference manual 16-3 communication 16 processor module the block diagram of the communication processor module is illustrated in figure 16-1. figure 16-1. cpm block diagram i 2 c smc2 risc rom timers sdma interrupt controller bus interface parallel i/o ports dual-port serial interface and time-slot assigner u - bus peripheral bus internal bus ram baud rate generators usb scc2 smc1 spi microcontroller mac sequencer alu register file crc scc3
communication processor module 16-4 mpc823e reference manual motorola risc communication 16 processor module the mpc823e offers an extremely flexible set of communication capabilities. the remainder of this section discusses all the possible ways you can configure the communication processor module. figure 16-2 illustrates a sample configuration for a personal digital assistant (pda) application that supports various communication links and protocols. 16.2 the risc microcontroller the 32-bit risc microcontroller for the communication processor module resides on a separate bus from the core and, therefore, does not impact the cores performance. the microcontroller operates in conjunction with the serial channels and parallel port to implement the user-programmable protocols and manage the serial dma (sdma) channels that transfer data between the i/o channels and memory. the risc microcontroller architecture and instruction set are optimized for data communication and data processing functions that are required by many wire-line and wireless communication standards. the microcontroller also contains a multiply and accumulate (mac) unit composed of a 16x16-bit multiplier with two 40-bit accumulators that enable you to implement many dsp applications. basically, the microcontroller handles low-level arithmetic tasks and dma control activities, which leaves the core free to handle the high-level activities. you could say it is the controller of the communication processor module. it manages idma channel operation and contains an internal timer that you can use to implement a maximum of 16 additional software timers. mpc823e figure 16-2. example of a pda application usb scc2 i 2 c smc1 smc2 spi infra-red xcvr usb xcvr usb port infra-red link voice synthesizer i 2 c bus screen digitizer spi bus radio interface rs232 xcvr uart port scc3
communication processor module motorola mpc823e reference manual 16-5 risc communication 16 processor module 16.2.1 risc microcontroller features the following is a list of the risc microcontrollers main features. ? one system clock cycle per instruction ? fixed-length instruction object code ? code is executed from internal rom or dual-port ram ? automatically switches to low-power mode when idle ? 32-bit data path ? optimized for communication processing ? digital signal processing capability using mac arithmetic and special addressing modes ? dma bursts serial data to external memory figure 16-3. risc microcontroller block diagram sequencer decoder arithmetic multiply cyclic register file processing units dma dual-port ram scheduler instruction storage ram rom development support service requests peripheral interface peripheral bus redundancy check logic unit and accumulate
communication processor module 16-6 mpc823e reference manual motorola risc communication 16 processor module 16.2.2 communication between the microcontroller and core the risc microcontroller communicates with the core in the following ways: ? by exchanging parameters using the 8k dual-port ram. with simultaneous accesses, the microcontroller experiences a one-clock delay when accessing the dual-port ram, but the host is never delayed. ? by executing special commands that are issued by the host via the cpm command register (cpcr). these commands must only be issued in special situations like exceptions or error recovery. ? by generating interrupts using the cpm interrupt controller. ? by allowing the core to configure the cpm via the risc controller configuration register ? by allowing the core to read the cpm status and event registers at any time. the core communicates with the cpm by configuring the rccr. 16.2.3 communication between the microcontroller and peripherals the risc microcontroller uses the peripheral bus to communicate with all of its peripherals. the serial communication controllers (sccs) and universal serial bus (usb) have separate receive and transmit fifos. the scc2 fifos are 32 bytes and the scc3 and usb fifos are 16 bytes each. however, the serial management controller, serial peripheral interface, and i 2 c fifo sizes are all double-buffered. the following prioritized list contains the processing order of the microcontroller from highest to lowest priority. 1. reset in cpm command register or at reset 2. sdma bus error 3. commands issued to the command register, including dsp-related commands 4. idma dreq1 (default setting) 5. idma dreq2 (default setting) 6. usb reception (rx) 7. usb transmission (tx) 8. scc2 rx 9. scc2 tx 10. scc3 rx 11. scc3 tx 12. idma dreq1 (option 2) 13. idma dreq2 (option 2) 14. smc1 rx 15. smc1 tx 16. smc2 rx 17. smc2 tx
communication processor module motorola mpc823e reference manual 16-7 risc communication 16 processor module 18. spi rx 19. spi tx 20. i 2 c rx 21. i 2 c tx 22. risc timer tables 23. idma dreq1 (option 3) 24. idma dreq2 (option 3) 16.2.4 executing microcode from ram or rom the microcontroller can execute microcode from a portion of 8k dual-port ram. depending on the size of your microcode, you can program the eram field in the rccr to protect the first 512 bytes, 1,024 bytes, or 2,048 bytes of on-chip ram to allow the microcontroller exclusive access. you can execute microcode from the dual-port ram or on-chip rom. this flexibility not only allows motorola to add more protocols or enhancements to the mpc823e, but it also allows you to obtain binary microcode. refer to table 16-1 for more information. 16.2.5 risc configuration and control registers the 32-bit risc controller configuration register (rccr) and risc microcode development support control (rmds) register are used to configure and control the risc microcontroller. the rccr configures the microcontroller to run microcode from rom or ram and controls the risc internal timer. the rmds determines the regions of the dual-port ram that can contain executable microcode. it is recommended that you write to these two registers as if they were a single 32-bit register. the eram4k bit is cleared in the rmds if the rccrs location is accessed as either part of a half-word or byte access. rmds is used in conjunction with the eram field of the rccr to determine the valid address space for executable microcode. if the eram4k bit is to be set, the rmds register must be accessed as part of a word starting at immr+0x9c4 to immr+0x9c7. rccr-rmds bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field time res timep dr2m dr1m drqp eie scd eram reset 00 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9c4 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved eram4k reserved reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9c6
communication processor module 16-8 mpc823e reference manual motorola risc communication 16 processor module timetimer enable this bit controls whether the microcontrollers internal timer can send a tick to the microcontroller based on the value programmed into the timep field. 0 = stop risc timer table scanning. 1 = start risc timer table scanning. bits 1, 16C23 and 25C31reserved these bits are reserved and must be set to 0. timeptimer period this field controls the microcontrollers timer tick. the risc timer tables are scanned on each timer tick and the input to the timer tick generator is the general system clock divided by 1,024. the formula is (timep + 1) 1,024 = (general system clock period). thus, a value of 0 stored in these bits gives a timer tick of 1 (1,024) = 1,024 general system clocks and a value of 63 (decimal) gives a timer tick of 64 (1,024) = 65,536 general system clocks. dr2midma request 2 mode this bit controls the idma request 1 (dreq2 ) sensitivity mode. 0 = dreq2 is edge-sensitive. 1 = dreq2 is level-sensitive. dr1midma request 1 mode this bit controls the idma request 0 (dreq1 ) sensitivity mode. 0 = dreq1 is edge-sensitive. 1 = dreq1 is level-sensitive. drqpidma emulation request priority this field controls the priority of the external request signals that relate to the serial channels. refer to section 16.2.3 communication between the microcontroller and peripherals for more information. 00 = idma requests have priority over the serial communication controllers and usb (default). 01 = idma requests have priority immediatley following the serial communication controllers (option 2). 10 = idma requests have the lowest priority (option 3). 11 = reserved. eieexternal interrupt enable configure this bit as instructed in the download process of a motorola-supplied ram microcode package. this bit is also used by idma channel 1 to enable single-buffer mode, as described in section 16.6.3.11.4 single-buffer burst fly-by mode . 0 = dreq1 pin cannot interrupt the microcontroller. 1 = dreq1 pin can interrupt the microcontroller.
communication processor module motorola mpc823e reference manual 16-9 risc communication 16 processor module scdscheduler configuration configure this bit as instructed in the download process of a motorola-supplied ram microcode package. 0 = normal operation. 1 = alternate configuration of the scheduler. eramenable ram microcode configure this field as instructed in the download process of a motorola-supplied ram microcode package. this field is used in conjunction with the eram 4k bit to configure the ram microcode space. eram4kenable ram microcode (4k) 0 = microcode is only executed from the first 2,048 bytes of the dual-port ram. 1= microcode is executed from the 2,048 bytes of the second half of the dual-port ram with a 512-byte extension. 16.2.6 risc microcontroller commands to initialize the serial channel or dma, you can issue a command to the cpm command register. the command you issue will ask the communication processor module to perform further device-specific functions based on the information in the devices parameter ram. 16.2.6.1 cpm command register. the core sets the flg bit in the 16-bit, memory-mapped, read/write cpm command register (cpcr) when it issues a command and the communication processor module clears the flg bit when the command is completed. the core is now ready for the next command. subsequent commands to the cpcr can only be given when the flg bit is clear. when issuing the software reset command, the core must also set the flg bit. table 16-1. ram microcode configurations eram (rccr) bit 0 in rmds microcode addresses 01 0 2000-21ff and 2f00-2fff 10 0 2000-23ff and 2f00-2fff 11 0 2000-27ff and 2e00-2fff 01 1 2000-21ff, 2f00-2fff, 3000-37ff, and 3a00-3bff 10 1 2000-23ff, 2f00-2fff, 3000-37ff, and 3a00-3bff 11 1 2000-27ff, 2e00-2fff, 3000-37ff, and 3a00-3bff
communication processor module 16-10 mpc823e reference manual motorola risc communication 16 processor module rstsoftware reset command this bit is set by the core and cleared by the communication processor module and when this command is executed, the rst and flg bits are cleared within two general system clocks. the risc reset routine is approximately 60 clocks long, but you can start initializing the communication processor module immediately after this command is issued. rst is useful when the core wants to reset the registers and parameters for all the channels as well as the risc microprocessor and timer tables. however, this bit does not affect the serial interface or parallel i/o registers. 0 = no reset is issued. 1 = reset is issued. bits 1C3reserved these bits are reserved and must be set to 0. opcodeoperation code this field is used in conjunction with the ch_num field to define a command sent to the cpm. it issues a variety of commands, which are described in table 16-2. for the same operation code, the results may be different, depending on the channel number you select. for example, if your operation code is 0101 ( graceful stop tx ) and your channel number is set to 0100 (scc2), then the operation will gracefully stop the transmit on scc2. if your channel number is set to 0001 (idma1), then the operation will gracefully stop the transmit on idma1. ch_numchannel number this field is set by the core to define the peripheral i/o channel that the command is applied to. some peripherals share channel number encodings if their commands are mutually exclusive. see table 16-2 for more information. bits 12C14reserved these bits are reserved and must be set to 0. cpcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rst reserved opcode ch_num reserved flg reset 00 0 0 00 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9c0
communication processor module motorola mpc823e reference manual 16-11 risc communication 16 processor module flgcommand semaphore flag the bit is set by the core and cleared by the communication processor module. 0 = the communication processor module is ready to receive a new command. 1 = the cpcr contains a command that the communication processor module is currently processing. the communication processor module clears this bit when the command finishes executing or after reset. 16.2.6.2 command definitions. the risc microcontroller requires an opcode and a channel number to determine the command to issue. these opcodes and their definitions are described below. the opcodes and channel numbers that appear in table 16-2 are actually the commands to be issued in the cpcr. table 16-2. risc microcontroller commands opcode channel number scc2 (0100) or scc3 (1000) usb (0000) smc1 (1001) or smc2 (1101) (uart/ trans) smc1 (1001) or smc2 (1101) (gci) spi (0101) i 2 c (0001) idma1 (0001) idma2 (0101) dsp1 rx (1001) dsp2 tx (1101) timer (0101) 0000 init rx and tx params init rx and tx params init rx and tx params init rx and tx params init rx and tx params 0001 init rx params init rx params init rx params init rx params 0010 init tx params init tx params init tx params init tx params 0011 enter hunt mode enter hunt mode 0100 stop tx stop tx endpoint stop tx 0101 graceful stop tx init idma init idma 0110 restart tx restart tx endpoint restart tx 0111 close rx bd close rx bd close rx bd close rx bd 1000 set group address set timer 1001 gci timeout 1010 gci abort request 1011 stop idma stop idma 1100 start dsp start dsp 1101 arm idma arm idma init dsp init dsp 1110 1111 usb command note: = reserved.
communication processor module 16-12 mpc823e reference manual motorola risc communication 16 processor module the risc microcontroller commands consist of the following: ? init tx and rx params the initialize transmit and receive parameter command initializes the transmit and receive parameters in the parameter ram to the values that they had when the communication processor module was last reset. this command is especially useful when switching protocols on a serial channel. ? init rx parameters the initialize receive parameters command initializes the receive parameters of the serial channel. ? init tx parameters the initialize transmit parameters command initializes the transmit parameters of the serial channel. ? enter hunt mode the enter hunt mode command causes the receiver to stop receiving and start looking for a new frame. the exact operation of this command depends on the protocol that is used. ? stop tx the stop transmission command stops transmitting from this channel as soon as the transmit fifo has been emptied. it must only be used when transmissions need to be stopped immediately. transmission continues when the restart tx command is issued. ? graceful stop tx the graceful stop transmission command stops transmitting from this channel as soon as the current frame has been fully transmitted from the transmit fifo. transmission continues when the restart tx command is issued and the r bit is set in the next transmit buffer descriptor. ? restart tx once the stop tx command has been issued, the restart transmission command is used to start transmitting again at the current buffer descriptor. ? close rx bd the close receive buffer descriptor command causes the receiver to close the current receive buffer descriptor, which makes the receive buffer available for you to manipulate. the next available buffer descriptor is used to continue reception. you can use this command to access the data buffer and you wont have to wait until a serial communication controller fills it. ? init idma the initialize idma command initializes the idma internal state to the value it had at system reset. it is only required when the idma autobuffer or buffer chaining modes are used. ? arm idma the arm idma command causes the idma to open the next buffer descriptor in the table. it can be used to reduce the latency of servicing the first idma request. single buffer burst fly-by mode is only available for idma1. ? set timer the set timer command is used to activate, deactivate, or reconfigure the 16 timers of the risc timer table. ? set group address the set group address command sets a hash table bit for the ethernet logical group address recognition function. ? gci abort request the gci abort request command causes the mpc823e receiver to send an abort request on the a bit of the gci bus.
communication processor module motorola mpc823e reference manual 16-13 risc communication 16 processor module ? gci timeout the gci timeout command causes the mpc823e transmitter to send an abort request on the e bit of the gci bus. ? usb the usb commands have the same opcode. see section 16.10 universal serial bus controller for a more detailed description. 16.2.6.2.1 cpm command register example. to perform a complete reset of the communication processor module, you must write 0x8001 to the cpcr, which also sets the rst and flg bits. after you issue this command, the cpcr returns a value of 0x0000 after two clocks. to execute an enter hunt mode command to the scc2, write 0x0341 to the cpcr. while this command is executing, the cpcr returns a 0x0341 value and once it is finished it returns a 0x0340 value, which clears the flg bit. 16.2.6.3 dual-port ram. the communication processor module has 8,192 bytes of static ram that is configured as dual-port memory. a block diagram of the dual-port ram is illustrated in figure 16-4. note: the worst-case command execution latency is 120 clocks and the typical command execution latency is approximately 40 clocks. figure 16-4. dual-port ram block diagram 1,024 bytes 512 bytes 1,024 bytes 1,024 bytes 512 bytes 2,048 bytes 1,024 bytes u bus address risc instruction address risc data address u bus address risc data address u-bus data risc instruction risc data data selectors dual-port ram parameter ram address selectors address selectors data selectors note: the shaded area is implemented on the silicon. 1,024 bytes
communication processor module 16-14 mpc823e reference manual motorola risc communication 16 processor module the dual-port ram can either be accessed by the risc microcontroller or one of two bus mastersthe core or the serial dma channel. when the dual-port ram is accessed by one of these, it is accessed in two clocks. however, when it is accessed by the microcontroller, it is accessed in one clock. when simultaneous accesses occur with at least one write operation, the microcontroller is delayed by one clock. figure 16-5. dual-port ram memory map bd / data /code bd / data / code 0k 6k parameter ram bd / data eram = 10 bd / data / code 7k bd / data / code dpram_base = (immr & 0xffff0000) + 0x2000 dpram_base = (immr & 0xffff0000) + 0x2400 dpram_base = (immr & 0xffff0000) + 0x2800 dpram_base = (immr & 0xffff0000) + 0x3000 dpram_base = (immr & 0xffff0000) + 0x3c00 dpram_base = (immr & 0xffff0000) + 0x2200 dpram_base = (immr & 0xffff0000) + 0x2e00 3k eram =11 4k 5k 2k 1k eram = 01 bd / data / code bd / data / code bd / data dpram_base = (immr & 0xffff0000) + 0x3800 dpram_base = (immr & 0xffff0000) + 0x3400 dpram_base = (immr & 0xffff0000) + 0x3a00 8k bd / data / code
communication processor module motorola mpc823e reference manual 16-15 risc communication 16 processor module when the dual-port ram is accessed by the core or sdma channel, the data and address are passed to and from the u-bus. the microcontroller has access to the entire dual-port ram for data fetches and portions of the system ram for microcode instruction fetches. the dual-port ram is used to complete the following tasks. any two tasks can occur simultaneously. ? to store the parameters associated with the usb, sccs, smcs, spi, i 2 c, and idmas in the 1,024-byte parameter ram. ? to store the buffer descriptors that describe where data is to be received and transmitted. ? to store the data from the serial channels. this is optional because data can also be stored in external memory. ? to store the ram microcode for the risc microcontroller. this feature allows motorola to add protocols in the future. ? to use as an additional scratchpad ram space for your program. only the content of the parameter and microcode ram options require the use of fixed addresses. the buffer descriptors, buffer data, and scratchpad ram can be located in the internal system ram or in any unused parameter ram. for instance, the area that is available when a serial channel or sub-block is not being used. when a microcode from ram is executed, certain portions of the system ram are no longer available. there are three possible configurations for microcode area sizes first 512-byte block with a 256-byte extension (rccr eram=01), first 1,024-byte block with 256-byte extension (rccr eram=10), or first 2,048-byte block with 512-byte extension (rccr eram=11). the remainder of the first 4,096 bytes are available as system ram. see table 16-1 for details. 16.2.6.3.1 buffer descriptors. the universal serial bus, serial communication controllers, serial management controllers, serial peripheral interface, and i 2 c always use buffer descriptors to control data buffers. the table below shows that their buffer descriptor formats are all the same. if the idma channel is used in buffer chaining or autobuffer mode, it also uses buffer descriptors. a data length of zero will set the buffer length to 65536 bytes. 16.2.6.3.2 parameter ram. the communication processor module maintains a section of dual-port ram called the parameter ram. it contains many parameters for a universal serial bus, serial communication controller, serial management controller, serial peripheral interface, i 2 c controller, and idma channel operation. the parameter ram structure is summarized in table 16-3. 0 15 offset + 0 status and control offset + 2 data length offset + 4 high-order data buffer pointer offset + 6 low-order data buffer pointer
communication processor module 16-16 mpc823e reference manual motorola risc communication 16 processor module a definition of the parameter ram is contained in each protocol subsection that describes the device using a parameter ram. for example, in some locations the ethernet parameter ram memory map is defined in the same way that the hdlc-specific parameter ram is defined. table 16-3. parameter ram memory map page addresses peripheral immr + 0x3c00 1 dpram_base+ 0x1c00 usb dpram_base+ 0x1c7f dpram_base+ 0x1c80 i 2 c dpram_base+ 0x1caf dpram_base+ 0x1cb0 misc dpram_base+ 0x1cbf dpram_base+ 0x1cc0 idma1 dpram_base+ 0x1cff immr + 0x3d00 2 dpram_base+ 0x1d00 scc2 dpram_base+ 0x1d7f* dpram_base+ 0x1d80 spi dpram_base+ 0x1daf dpram_base+ 0x1db0 timers dpram_base+ 0x1dbf dpram_base+ 0x1dc0 idma2 dpram_base+ 0x1dff immr + 0x3e00 3 dpram_base+ 0x1e00 scc3 dpram_base+ 0x1e7f ? dpram_base+ 0x1e80 smc1 dpram_base+ 0x1ebf dpram_base+ 0x1ec0 dsp1 dpram_base+ 0x1eff immr + 0x3f00 4 dpram_base+ 0x1f00 reserved dpram_base+ 0x1f7f dpram_base+ 0x1f80 smc2 dpram_base+ 0x1fbf dpram_base+ 0x1fc0 dsp2 dpram_base+ 0x1fff note: dpram_base = (immr & 0xffff0000) + 0x2000. * 0x1da3 for ethernet. ? 0x1ea3 for scc3 ethernet.
communication processor module motorola mpc823e reference manual 16-17 risc communication 16 processor module 16.2.6.4 the risc timer tables. the risc microcontroller can have a maximum of 16 timers that are separate and distinct from the four general-purpose timers and baud rate generators of the communication processor module. these timers are ideal for protocols that do not require extreme precision, but do need to free the host cpu from scanning the softwares timer tables. these timers are clocked from an internal timer that only the microcontroller can access. each pair of timers can be configured as pulse width modulation (pwm) channels. the output of the channel is driven on one of the port b pins and a maximum of six pwm channels are supported. the following list summarizes the main features of the risc timer tables. ? supports a maximum of 16 timers ? supports a maximum of six pwm channels ? three timer modesone-shot, restart, and pwm ? maskable interrupt on timer expiration ? programmable timer resolution as low as 41ms at 25mhz ? maximum timeout period of 172sec at 25mhz ? continuously updated reference counter risc timer table operations are based on a tick in the risc internal timer that is programmed in the risc controller configuration register (rccr). the tick is a multiple of 1,024 general system clocks. the risc timer tables have the lowest priority of all risc microcontroller operations, so if it is busy with other tasks and unable to service the timer during a tick interval, one or more of the timers might not be updated. this behavior can be used to estimate the worst-case loading of the microcontroller. the timer tables are configured in the rccr, the timer table parameter ram, the set timer command that is issued to the cpcr, the timer event register, and the timer mask register.
communication processor module 16-18 mpc823e reference manual motorola risc communication 16 processor module 16.2.6.4.1 risc timer table parameter ram memory map. two areas of internal ram are used for the risc timer tablesrisc timer table parameter ram and the risc timer table entrieswhich are illustrated in figure 16-6. the risc timer table parameter ram area begins at the risc timer base address and is used for the general timer parameters. see table 16-4 for details. note: all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register. figure 16-6. risc timer table ram usage (14 bytes) entries (up to 64 bytes) 16 risc timer table tm_base index pointer risc timer table parameter ram timerbase dual-port ram timer parameter ram immr + 3db0
communication processor module motorola mpc823e reference manual 16-19 risc communication 16 processor module ? tm_basethis index pointer contains a 16-bit offset from the beginning of the dual-port ram to the location of your timer table entry. for the timer table entry area, you must allocate four bytes for each timer used. if you use all 16 timers, you must allocate 64 bytes in the timer table entry area. if you do not use all the timers, the timers must always be allocated in ascending order to save space. for example, if you only need two timers, then 8 bytes are required for the timer table entry area as long as you only enable risc timers 0 and 1. ? tm_ptrthis index pointer is used exclusively by the risc microcontroller to point to the next entry to be executed in the timer table. you must not modify this pointer. table 16-4. risc timer table parameter ram memory map address name width description timer base + 00 tm_base half-word risc timer table base address index pointer timer base + 02 tm_ptr half-word risc timer table pointer timer base + 04 r_tmr half-word risc timer mode register timer base + 06 r_tmv half-word risc timer valid register timer base + 08 tm_cmd word risc timer command register timer base + 0c tm_cnt word risc timer internal counter note: you are only responsible for initializing the items in bold. timer base = (immr & 0xffff0000) + 0x3db0. note: the timer table entry area pointed to by the tm_base must always be aligned to a word boundary that is evenly divisible by four.
communication processor module 16-20 mpc823e reference manual motorola risc communication 16 processor module ? r_tmronly the risc microcontroller uses this register to store the mode of the timerone-shot (0) or restart (1). you must not modify this register. instead, you must use the set timer command in the cpcr to control the timer mode. tmr0C15timer 0C15 0 = no effect. 1 = clears a bit in this register. ? r_tmvonly the risc microcontroller uses this register to determine whether or not a timer is currently enabled. if the corresponding timer is enabled, a bit is 1. you must not modify this register. you must use the set timer command to enable a timer. tmr0C15timer 0C15 0 = no effect. 1 = clears a bit in this register. r_tmr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tmr15 tmr14 tmr13 tmr12 tmr11 tmr10 tmr9 tmr8 tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x3db4 r_tmv bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tmr15 tmr14 tmr13 tmr12 tmr11 tmr10 tmr9 tmr8 tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x3db6
communication processor module motorola mpc823e reference manual 16-21 risc communication 16 processor module ? tm_cmdthis register is used as a parameter location when the set timer command is issued. you must write this location prior to issuing the set timer command. the bits of this register are defined as follows. vvalid 0 = disables the timer. 1 = enables the timer. rrestart 0 = one-shot timer operation. 1 = automatic timer restart. pwmpulse-width modulation mode 0 = normal mode. 1 = pulse-width modulation. bits 3C11reserved these bits are reserved and must be set to 0. timer number this bit is the value from zero to 15 that signifies timer configuration. timer period this bit is the 16-bit timeout value of the timer. the maximum value is 65,536 and is encoded as 0x0000. ? tm_cntthis register is a tick counter that the microcontroller updates after each tick or after the timer table is scanned. it is updated if the microcontrollers internal timer is enabled, regardless of whether any of the 16 timers are enabled, and it can be used to track the number of ticks the microcontroller receives and responds to. tm_cmd bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field v r pwm reserved timer number reset 000 0 0 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x3db8 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field timer period reset 0 r/w r/w addr (immr & 0xffff0000) + 0x3dba
communication processor module 16-22 mpc823e reference manual motorola risc communication 16 processor module 16.2.6.4.2 risc timer table entries. the 16 timers are located in the block of memory that tm_base points to and each timer occupies 4 bytes. the first half-word forms the initial value of the timer written when the set timer command is executed. the next half-word is the current value of the timer that gets decremented until it reaches zero. you must not modify these locations because they must only be used for debugging purposes. 16.2.6.4.3 the set timer command. this command is issued to the cpcr and is used to enable, disable, and configure the 16 timers in the risc timer table. the 0x0851 value must be written to the cpcr, but, first, you must set up the tm_cmd value. 16.2.6.4.4 pwm mode. each pair of timers can be used to generate a pulse-width modulation waveform on one of the port b pins. a maximum of six channels are supported. the first timer (which is even-numbered) is used to control the duty-cycle time of the waveform. in the register above, the timer period entry must be set to the high period of the waveform and the pwm and v bits must be set to 1. the second timer (which is odd- numbered) is used to control the cycle time. the timer period entry must be set to the preferred cycle time, the pwm bit must be set to zero, and the r and v bits must be set to 1. table 16-5 shows the port b pin assignments for the pwm mode. the respective port b pins must be configured as general-purpose outputs in the pbdir, which is described in section 16.14.6.3 port b data direction register. because the cpm has to read the data register, modify it and then write it back, you cannot use open drain output with the pwms if the output can be forced to 0 by external devices. table 16-5. pwm channel pin assignments timer pairs port b pin 0 and 1 pb23 2 and 3 pb22 4 and 5 not available 6 and 7 not available 8 and 9 pb19 10 and 11 pb18 12 and 13 pb17 14 and 15 pb16
communication processor module motorola mpc823e reference manual 16-23 risc communication 16 processor module 16.2.6.5 risc timer event register. the 16-bit risc timer event register (rter) is used to report events recognized by the 16 timers and to generate interrupts. however, an interrupt is only generated if the risc timer table bit is set in the cpm interrupt mask register. more than one bit can be cleared once. tmr0C15timer 0C15 0 = no effect. 1 = clears a bit in the register. 16.2.6.6 risc timer mask register. this 16-bit read/write risc timer mask register (rtmr) is used to enable interrupts that can be generated in the rter. if a bit is set, it enables the corresponding interrupt in the rter. if a bit is cleared, this register masks the corresponding interrupt in the rter. however, an interrupt is only generated if the r-tt bit is set in the cpm interrupt mask register (cimr), which is described in section 16.15.5.3 cpm interrupt mask register . tmr0C15timer 0C15 0 = masks the corresponding interrupt in the rter. 1 = enables the corresponding interrupt in the rter. rter bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tmr15 tmr14 tmr13 tmr12 tmr11 tmr10 tmr9 tmr8 tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9d6 rtmr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tmr15 tmr14 tmr13 tmr12 tmr11 tmr10 tmr9 tmr8 tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9da
communication processor module 16-24 mpc823e reference manual motorola risc communication 16 processor module 16.2.6.7 risc timer initialization sequence example. follow these steps to initialize the risc timers: 1. configure the rccr to determine the preferred tick interval that will be used for the entire timer table. normally, you can set the time bit at this time. however, it can be set later if all risc timers must be synchronized. 2. determine the maximum number of timers to be located in the timer table. configure the tm_base pointer of the risc timer table parameter ram to point to a location in the dual-port ram with 4 n bytes available, where n is the number of timers. if n is less than 16, use timer 0 through timer nC1 to save space. 3. clear the tm_cnt counter of the risc timer table parameter ram to show how many ticks have elapsed since the risc internal timer was enabled (optional). 4. clear the rter, if it is not already cleared. a one clears this register. 5. configure the rtmr to enable the timers that need to generate interrupts. 6. set the r-tt bit in the cimr to generate interrupts to the system. make sure the cpm interrupt controller is properly initialized. 7. configure the tm_cmd register of the risc timer table parameter ram. at this point, determine whether a timer is to be enabled or disabled, one-shot or restart, and what its timeout period must be. if the timer is being disabled, all parameters besides the timer number are ignored. 8. issue the set timer command by writing 0x0851 to the cpcr. 9. repeat steps 7 and 8 for each timer to be enabled or disabled. as an example, the following sequence demonstrates how the risc timer 0 is initialized to generate an interrupt approximately every second using a 25mhz general system clock: 1. write 111111 to the timep field of the rccr to generate the slowest clock. this value generates a tick every 65,536 clocks, which is every 2.6 milliseconds at 25mhz. 2. configure the tm_base pointer of the risc timer table parameter ram to point to a location in the dual-port ram with 4 bytes available. assuming that the beginning of dual-port ram is available, write 0x0000 to tm_base. 3. write 0x0000 to the tm_cnt counter of the risc timer table parameter ram to see how many ticks have elapsed since the risc internal timer was enabled (optional). 4. write 0xffff to the rter to clear any previous events. 5. write 0x0001 to the rtmr to enable risc timer 0 to generate an interrupt. 6. write 0x00020000 to the cpm interrupt mask register so the risc timers will generate a system interrupt. initialize the cpm interrupt configuration register. 7. write 0xc0000ee6 to the tm_cmd register of the risc timer table parameter ram. this enables risc timer 0 to timeout after 3,814 (decimal) ticks. the timer automatically restarts after it times out. 8. write 0x0851 to the cpcr to issue the set timer command. 9. set the time bit in the rccr to operate the risc timer.
communication processor module motorola mpc823e reference manual 16-25 risc communication 16 processor module 16.2.6.8 risc timer interrupt handling example. an interrupt handler for the risc timer tables is normally written in the following sequence: 1. once an interrupt occurs, the rter is read to determine which of the timers have caused interrupts. the risc timer event bits are usually cleared by this time. 2. any additional set timer commands are issued. you do not have to do anything if the timer is automatically being restarted for a repetitive interrupt. 3. the r-tt bit is cleared in the cpm interrupt status register. 4. execute the rfi instruction. 16.2.6.9 risc timer table algorithm. the risc microcontroller scans the timer table once every tick. for each valid timer in the table, the microcontroller decrements the count and checks for a timeout and if no timeout occurs, it moves to the next timer. if a timeout does occur, the microcontroller sets the corresponding event bit in the risc timer event register. then it checks to see if the timer needs to be restarted and if it does, it leaves the r_tmv register and resets the current count to the initial count. otherwise, it clears the r_tmv register. once the timer table is scanned, the microcontroller updates the tm_cnt value in the risc timer table parameter ram and stops working on the timer tables until the next tick. if a set timer command is issued, the microcontroller makes the appropriate modifications to the timer table and parameter ram, but does not scan the timer table until the next tick of the internal timer. if you modify the risc timer table, execute the set timer command to synchronize the timers so that the microcontroller will operate properly. 16.2.6.10 using the timers to track microcontroller loading. the following sequence of steps is a method for using the 16 timers to determine if the microcontroller ever exceeds the 96% utilization level during a tick interval. removing the timers adds a 4% margin to the microcontrollers utilization level, but an aggressive user can use this technique to push the microcontroller performance to its limit. you must use the standard initialization sequence, but incorporate the following steps: 1. program the tick of the risc microcontroller timers to be 1,024 16 = 16,384. 2. disable microcontroller timer interrupts, as required. 3. using the set timer command, initialize all 16 risc microcontroller timers to have a timer period of 0x0000, which equals 65,536. 4. program one of the four general-purpose timers to increment once every tick. the general-purpose timer must be free-running and have a timeout of 65,536. 5. after a few hours of operation, compare the general-purpose timer to the current count of risc microcontroller timer 15 and if the difference between them exceeds two ticks, the microcontroller has, during some tick interval, exceeded the 96% utilization level. note: the general-purpose timers are up-counters, but the risc microcontroller timers are down-counters. you must take this under consideration when comparing timer counts.
communication processor module 16-26 mpc823e reference manual motorola dsp communication 16 processor module 16.3 digital signal processing many embedded control applications require dsp-style algorithm implementations, such as finite impulse response (fir) filters with or without adaptive equalization, data compression, and scrambling. these are written in software on the mpc823e and do not require your system to have a separate dsp processor, which would cost you more and consume more power. the communication processor module provides the additional power you need for those applications. the risc microcontrollers instruction set supports high-performance multiply and accumulate (mac) operation as well as special addressing modes that are essential to efficient dsp algorithm implementation. the risc microcontroller runs concurrently with the core and increases the cores bandwidth left for other system tasks. the system can take advantage of this increased core bandwidth by lowering the system clock frequency and voltage, which decreases the amount of power that is consumed. 16.3.1 features the following list summarizes the features of mpc823e dsp: ? 16 16-bit multiply and accumulate ? load/store with automatic post increment/decrement ? dsp routine library provides 11 basic building blocks for implementation of v.34bis and 56k 16.3.2 dsp operation there are three layers to dsp functionalityhardware, firmware, and software. you only need to construct the software layer to generate an application. figure 16-7. dsp functionality implementation cpm hardware cpm firmware cpu software generic dsp microcode routine library mac and address generator modules function descriptor chain in external stored in the internal rom in cpm risc microcontroller architecture memory defines the sequence and data flow of the dsp functions
communication processor module motorola mpc823e reference manual 16-27 dsp communication 16 processor module 16.3.2.1 hardware. the risc microcontrollers hardware contains special dsp processing units, such as a multiplier and accumulator that is capable of handling real or complex numbers, and an address generator that can access cyclic buffer structures in dual-port ram. 16.3.2.2 software. your software interfaces to the dsp via the function descriptor that is described in system memory. the function descriptor defines the sequence and data flow of your dsp task. 16.3.2.3 firmware. the risc microcontrollers firmware is a set of dsp functions that have been compiled to form a library of basic building blocks and each function within the library is implemented by a microcode routine stored in the internal rom. in addition, a software interface is defined that enables parameters to be passed between the core and communication processor module. several functions can be chained together to reduce software intervention and interrupt rates, assuming that all data structures reside in the dual-port ram. table 16-6 lists the dsp functions that are included in the library. 16.3.3 programming the dsp functions similar to the serial communication controller buffer descriptor, a function descriptor (fd) is used to specify the dsp function and pass the parameters. a table of such descriptors forms a circular queue with a programmable length. the descriptors are stored in external memory. there are two function descriptor tables (also referred to as chains)one for the transmitter and one for the receiver. the core prepares a chain of function descriptors in the system memory and a special host command notifies the risc microcontroller when to execute the chain. a maskable interrupt is generated once the chain is completed. as illustrated in figure 16-8, the pointer to the transmit (tx) chain must be written into the fdbase field of the dsp2 parameter ram and the pointer to the receive (rx) chain must be written into dsp1. table 16-6. dsp functions function opcode input coefficient output application fir1 00001 real real real decimation, rx interpolation fir2 00010 complex real complex tx filter, rx filter fir3 00011 complex complex real/complex ec computation, equalizer fir5 00011 complex complex real/complex fractionally spaced equalizer fir6 00110 real complex complex iir 00111 real real real biquad filter mod 01000 complex complex real/complex tx modulation demod 01001 real complex complex rx demodulation lms1 01010 ec update, equalizer update (t/2, t/3) lms2 01011 equalizer update (2t/3) wadd 01100 real real interpolation
communication processor module 16-28 mpc823e reference manual motorola dsp communication 16 processor module 16.3.3.1 data representation. the inputs, coefficients, and outputs are represented by 16-bit, fixed-point, 2s complement numbers. a real number is represented by a single 16-bit half-word, as illustrated in figure 16-8. its value is between -1 (0x8000) to +1 (0x7fff) and you must scale your data to fit this range. a complex number is represented by a pair of 16-bit half-wordsone word for the imaginary component and one for the real component as shown in figure 16-8. they must be scaled to fit in the -1 and +1 range. figure 16-8. dsp function descriptor operation bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field s real fraction bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field s imaginary fraction bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field s real fraction system memory dual-port memory receive fd chain transmit fd chain input, output, and coefficient buffers rx chain base tx chain base dsp1 dsp2
communication processor module motorola mpc823e reference manual 16-29 dsp communication 16 processor module 16.3.3.2 modulo addressing. the input and output buffers are circular within a certain programmable size that must be a multiple of 2 k . the base address of the circular buffer must be aligned on its natural size boundary. for example, if your input buffer size is 128 bytes, your base address must be aligned on a 128-byte boundary. in other words, the lower boundary (base address) of a circular buffer containing modulus (m) bytes must have zeros in the k lsbs of the base address, where 2 k 3 m, and therefore must be a multiple of 2 k . the upper boundary is the lower boundary, plus the size minus one (base address + m-1). once m is chosen, a sequential series of memory blocks (each of length 2 k ) is created where these circular buffer can be located. if m < 2 k , there is a 2 k -m space between the sequential m-sized circular buffers and m must be a multiple of four. see figure 16-9 for details. 16.3.3.2.1 dsp function descriptors. each function descriptor is composed of eight 16-bit half-words. the first half-word contains the function opcode as well as status and control bits and the other half-words contain the functions parameter packet. each function has its own parameter packet. sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1 and 4C10reserved these bits are reserved and must be set to 0. figure 16-9. circular buffer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i reserved opcode offset + 2 parameter 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? offset + e parameter 7 upper boundary lower boundary m = modulus address pointer circular buffer
communication processor module 16-30 mpc823e reference manual motorola dsp communication 16 processor module wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the communication processor module processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table is programmable and determined only by the w bit and the overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. opcodefunction operation code this field specifies the function that must be executed. some of these bits are reserved so they can be expanded by tapping into ram and executing a routine. see table 16-6 for more information. 16.3.3.2.2 dsp parameter ram memory map. each section in the dual-port ram is associated with each dsp chain and can be used for parameter storage or as a scratchpad. the fdbase index pointer defines the place in system memory for the function descriptor chain to start. it must be 16-byte aligned. also, the fdbase index pointer must be initialized before the init_dsp command is issued. see table 16-7 for dsp parameter ram memory map details.
communication processor module motorola mpc823e reference manual 16-31 dsp communication 16 processor module fdbasefunction descriptor table base address this index pointer defines the location in system memory where the function descriptor starts. however, you must initialize it. fd_ptrfunction descriptor pointer this pointer points to the current function descriptor address. it is only used by the risc microcontroller, so you do not need to modify it in any way. dstatecurrent state this bit defines the internal state of the risc microcontroller. it is only used by the risc microcontroller, so you do not need to modify it in any way. dstatuscurrent function descriptor status this bit defines the current status of the current function descriptor. it is only used by the risc microcontroller, so you do not need to modify it in any way. table 16-7. dsp parameter ram memory map address name width description dsp base + 0x00 fdbase word function descriptor table base address dsp base + 0x04 fd_ptr word function descriptor pointer dsp base + 0x08 dstate word dsp state dsp base + 0x0c to 0x0f res word reserved dsp base + 0x10 dstatus half-word current function descriptor status dsp base + 0x12 i half-word current function descriptor number of iterations dsp base + 0x14 tap half-word current function descriptor number of taps dsp base + 0x16 cbase half-word current function descriptor cbase pointer dsp base + 0x18 half-word current function descriptor sample buffer size-1 dsp base + 0x1a xptr half-word current function descriptor pointer to sample pointer dsp base + 0x1c half-word current function descriptor output buffer size-1 dsp base + 0x1e yptr half-word current function descriptor pointer to output buffer pointer dsp base + 0x20 m half-word current function descriptor sample buffer size-1 dsp base + 0x22 half-word current function descriptor sample buffer pointer dsp base + 0x24 n half-word current function descriptor output buffer size-1 dsp base + 0x26 half-word current function descriptor output buffer pointer dsp base + 0x28 k half-word current function descriptor coefficient buffer size-1 dsp base + 2a half-word current function descriptor coefficient buffer pointer note: you are only responsible for initializing the items in bold. dsp base = (immr & 0xffff0000) + 0x3ec0 (dsp1) and 0x3fc0 (dsp2).
communication processor module 16-32 mpc823e reference manual motorola dsp communication 16 processor module icurrent function descriptor number of iterations this bit is only used by the risc microcontroller, so you do not need to modify it in any way. tapcurrent function descriptor number of taps the bit is only used by the risc microcontroller, so you do not need to modify it in any way. cbasecurrent function descriptor cbase the bit defines the current function descriptor base address of the coefficients. it is only used by the risc microcontroller, so you do not need to modify it in any way. xptrcurrent function descriptor pointer to sample pointer the bit is only used by the risc microcontroller, so you do not need to modify it in any way. yptrcurrent function descriptor pointer to output buffer pointer the bit is only used by the risc microcontroller, so you do not need to modify it in any way. mcurrent function descriptor sample buffer size-1 the bit is only used by the risc microcontroller, so you do not need to modify it in any way. ncurrent function descriptor output buffer size-1 the bit is only used by the risc microcontroller, so you do not need to modify it in any way. kcurrent function descriptor coefficient buffer size-1 the bit is only used by the risc microcontroller, so you do not need to modify it in any way. 16.3.3.2.3 dsp commands. the following commands are issued to the cpm command register (cpcr) and their functionality is described in table 16-6. ? init dsp chain deactivates the corresponding chain. the function descriptor pointer is initialized to the starting address provided in the function descriptor table. ? start dsp chain activates the corresponding chain.
communication processor module motorola mpc823e reference manual 16-33 dsp communication 16 processor module 16.3.3.3 dsp event register. for dsp interrupts, the memory-mapped sdma status register (sdsr) is used to generate maskable interrupts to the core. an interrupt is set when the function finishes executing if the i bit is set in the function descriptor. there are two interrupt eventsdsp1 and dsp2that are each associated with a corresponding chain. a bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset at a time. sbersdma channel bus error (sdma function) when set, this bit indicates that an error caused the sdma channel to terminate during a read or write cycle. the sdma bus error address can be read from the sdma address register, as described in section 16.5.2.4 sdma address register . bits 1C5reserved these bits are reserved and must be set to 0. dsp2dsp chain 2 transmitter interrupt (dsp function) this bit is set when the chain 2 function finishes executing. however, the i bit must be set in the function descriptor. dsp1dsp chain 1 receiver interrupt (dsp function) this bit is set when the chain 1 function finishes executing. however, the i bit must be set in the function descriptor. sdsr bit 0 1 2 3 4 5 6 7 field sber reserved dsp2 dsp1 r/w r/w r/w r/w r/w reset 0000 addr (immr & 0xffff0000) + 0x908
communication processor module 16-34 mpc823e reference manual motorola dsp communication 16 processor module 16.3.3.4 dsp mask register. the 8-bit read/write sdma mask register (sdmr) is used to mask the dsp interrupts and has the same bit format as the sdsr. if a bit in the sdmr is a 1, the corresponding interrupt in the sdsr is enabled and if it is zero, the corresponding interrupt is masked. this register is cleared by reset. sbersdma channel bus error (sdma function) 0 = disable the interrupt. 1 = enable the interrupt. bits 1C5reserved these bits are reserved and must be set to 0. dsp1dsp chain 1 receiver interrupt (dsp function) 0 = disable the dsp chain 1 interrupt. 1 = enable the dsp chain 1 interrupt. dsp2dsp chain 2 transmitter interrupt (dsp function) 0 = disable the dsp chain 2 interrupt. 1 = enable the dsp chain 2 interrupt. sdmr bit 0 1 2 3 4 5 6 7 field sber reserved dsp2 dsp1 r/w r/w r/w r/w r/w reset 0000 addr (immr & 0xffff0000) + 0x90c
communication processor module motorola mpc823e reference manual 16-35 dsp communication 16 processor module 16.3.3.5 dsp implementation. there are basically two ways to implement a dsp taskrun c code on the core or use the communication processor module functions. figure 16-10 illustrates an example section of a v.32 modems transmit (tx) data pump flow. the tx filter is composed of three fir2 subfilters. to implement this dsp task with c code on the core, it takes 476 core instructions (371 for the filter and 105 for the modulation) to execute the code. repeating that 2,400 times a second consumes 1.14mips (476 x 2,400) of the core. to implement a task using the cpm functions, the software builds a static function descriptor structure composed of two chained functionsa fir2 and a mod. the core activates the risc microcontroller to execute those functions by sending a single write to the cpm command register. using an interrupt, the communication processor module then signals that the process has completed. the communication processor module executes the functions twice as efficiently as the core, which results in 0.55 cpm mips and very few core cycles. the tx filter is implemented by executing three subfilters each time a new sample is received. this is accomplished by invoking fir2 with a three-iteration count and autoincrement of the input sample pointer when the function is completed. fir2 writes the three results into the output buffer, which is also the modulation input buffer. modulation is accomplished by invoking mod with a three-iteration count. the input pointer is autoincremented with each iteration. figure 16-10. dsp implementation example modulation tx filter cos wt, sin wt 1 input / baud 3 outputs / baud 3 outputs / baud
communication processor module 16-36 mpc823e reference manual motorola dsp communication 16 processor module 16.3.3.5.1 dsp programming example (core only) void tx_filter () { s16 *coefr s16 *samplr, *sampli s16 *coefend; s32 filtoutr, filtouti; u8 subcount, sampleindex; extern s16 mult(s16 p1, s16 p2); /* in-line invocation */ coefr=txfiltcoef_str; coefend=txfiltcoef_end; samplr=&txfiltdly[real][txfiltptr]; sampli=&txfiltdly[imag][txfiltptr]; sampleindex=0; while (coefr communication processor module motorola mpc823e reference manual 16-37 dsp communication 16 processor module 16.3.3.5.2 dsp programming example (core and cpm). figure 16-11 illustrates the organization of the data buffer and function descriptor data in system memory and dual-port ram. the function descriptor resides in system memory and all input, ouput, and coefficient data must reside in dual-port ram. the transmit and modulation function descriptor chain can reside in either system memory or dual-port ram. figure 16-11. core and cpm implementation input pointer output pointer opcode = fir2 tx filter fd # of itterations # of taps coeff base in buffer size xyptr input buffer output buffer coeff table opcode = mod modulation fd # of itterations mod table size mptr in buffer size xyptr input pointer output buffer mod table mod table ptr system memory dual-port ram out buffer size out buffer size output pointer
communication processor module 16-38 mpc823e reference manual motorola dsp communication 16 processor module /* buffer descriptors */ typedef struct dsp_fd { unsigned short status; unsigned short parameter[7]; } dsp_fd; #define wrap 0x2000 /* wrap bit */ #define intr 0x1000 /* interrupt on completion */ /* define for function opcodes */ #define fir_2 0x0102 /* fir2 filter */ #define mod 0x0008 /* modulation function opcode */ /* initialize a static fd table for 2 functions */ dsp_fd filters[2]= { { fir_2,p11,p12, , p17} ,{(wrap | intr | mod),p21,p22, , p27} }; void main() { /* setup fd chain pointer */ dsp2_base. fdbase = filters; * /* issue command to cpm to start processing the fd chain */ issue_command( start_fd ); * * * } 16.3.4 dsp on-chip library functions the dsp library is an easy way to implement dsp functions. it consists of the following functions: ? fir1finite impulse response 1 ? fir2finite impulse response 2 ? fir3finite impulse response 3 ? fir5finite impulse response 5 ? fir6finite impulse response 6 ? iirinfinite impulse response ? modmodulation ? demoddemodulation ? lms1least mean squared 1 ? lms2least mean squared 2 ? waddweighted vector addition
communication processor module motorola mpc823e reference manual 16-39 dsp communication 16 processor module 16.3.4.1 fir1Creal c, real x, and real y. the fir1 function implements a basic fir filter with k real coefficients, real input samples, and real output. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. 16.3.4.1.1 coefficients and sample data buffers. the coefficients vector occupies k 16-bit half-words in memory and c(0) is stored in the first location. the sample input buffer is a cyclic buffer containing m+1 bytes. each sample is a 16-bit word and the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes. each output is a 16-bit half-word and the new output is stored in the address that follows the previous output. figure 16-12. fir1 implementation example coefficients input samples output c(0) * * c(1) * * c(2) x(n-k+1) * ** * y(n-k+1) c(k-1) x(n-2) * x(n-1) * x(n) y(n-2) y(n-1) y(n) 2k bytes m + 1 bytes n + 1 bytes figure 16-13. fir1 coefficients and sample data buffers t t t x(n) y(n) c(0) c(1) c(2) c(k-1) {real} {real} {real} yn () cp () xn p C () p0 = k1 C ? = ?
communication processor module 16-40 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.1.2 fir1 function descriptor. the fir1 function descriptor bit table is described below. the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1, 4, and 9C10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. iall auto-increment x for all iterations 0 = the x (input) data pointer is incremented (modulo m+1) by the number of samples specified in the index field after the last iteration. 1 = the x data pointer is incremented (modulo m+1) by the number of samples specified in the index field after each iteration. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i res iall index pc res opcode offset + 2 i offset + 4 k offset + 6 cbase offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module motorola mpc823e reference manual 16-41 dsp communication 16 processor module index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. pc preset coefficients pointer 0 = the coefficients pointer is not preset after each iteration. 1 = the coefficients pointer is preset after each iteration to the cbase pointer. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field. 16.3.4.1.3 fir1 parameter packet. the fir1 parameter packet is composed of seven 16-bit half-words and described in the following table. 16.3.4.1.4 application example. the fir1 is used in decimation and rx interpolation. for example, the following function descriptor structure can be used to implement a 2 to 1 decimation. table 16-8. fir1 parameter packet address name description half-word 1 i number of iterations half-word 2 k number of taps-1. the number of taps must be a multiple of four half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (4 samples) half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size is 4 (2 outputs) half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i 0 1 10 1 0 0 00001 offset + 2 i=3 (three iterations)
communication processor module 16-42 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.2 fir2Creal c, complex x, and complex y. the fir2 function implements a basic fir filter with k real coefficients, complex input samples, and complex output. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. 16.3.4.2.1 coefficients and sample data buffers. the coefficients vector occupies k 16-bit half-words in memory and c(0) is stored in the first location. the sample input buffer is a cyclic buffer that contains m+1 bytes and each input sample is two 16-bit half-words (real and imaginary components). the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer containing n+1 bytes. each output is two 16-bit half-words (real and imaginary components). the new output is stored in the address that follows the previous output. figure 16-14. fir2 implementation example t t t ? x(n) y(n) c(0) c(1) c(2) c(k-1) {complex} {complex} {real} yn () cp () xn p C () p0 = k1 C ? =
communication processor module motorola mpc823e reference manual 16-43 dsp communication 16 processor module 16.3.4.2.2 fir2 function descriptor. the fir2 function descriptor bit table is described below. the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. coefficients input samples output c(0) * * c(1) * * c(2) imag {x(n-k+1)} * real {x(n-k+1)} imag{y(n-k+1)} * real{y(n-k+1)} c(k-1) imag {x(n-2)} * real{x(n-2)} * imag{x(n-1)} imag{y(n-2)} real{x(n-1)} real{y(n-2)} imag{x(n)} imag{y(n-1)} real{x(n)} real{y(n-1)} imag{y(n)} real{y(n)} 2k bytes m + 1 bytes n + 1 bytes figure 16-15. fir2 coefficients and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i res iall index pc res opcode offset + 2 i offset + 4 k offset + 6 cbase offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-44 mpc823e reference manual motorola dsp communication 16 processor module bits 1, 4, 9, and 10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. iall auto-increment x for all iterations 0 = the x (input) data pointer is incremented (modulo m+1) by the number of samples specified in the index field after the last iteration. 1 = the x data pointer is incremented (modulo m+1) by the number of samples specified in the index field after each iteration. index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. pc preset coefficients pointer 0 = the coefficients pointer is not preset after each iteration. 1 = the coefficients pointer is preset after each iteration to cbase pointer. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field.
communication processor module motorola mpc823e reference manual 16-45 dsp communication 16 processor module 16.3.4.2.3 fir2 parameter packet. the fir2 parameter packet is composed of seven 16-bit half-words and described in the table below. 16.3.4.2.4 application example. the fir2 function is used in the tx and rx filters. for example, the following function descriptor structure can be used to implement the tx filter. table 16-9. fir2 parameter packet address name description half-word 1 i number of iterations. half-word 2 k number of taps-1. half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (4 samples) half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size is 8 (2 outputs) half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i 0 0 01 0 0 0 00010 offset + 2 i=3 (three iterations)
communication processor module 16-46 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.3 fir3Ccomplex c, complex x, and real/complex y. the fir3 function implements a basic fir filter with k complex coefficients, complex input samples, and real or complex output. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. figure 16-16. fir2 implementation example t t t ? x(n) y(n) c(0) c(1) c(2) c(k-1) {complex} {real or complex} {complex} or y n () cp () xn p C () p0 = k1 C ? = yn () real c p () xn p C () p0 = k1 C ? ?t ?? y ?? =
communication processor module motorola mpc823e reference manual 16-47 dsp communication 16 processor module 16.3.4.3.1 coefficients and sample data buffers. the coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and c(0) is stored in the first location. the sample input buffer is a cyclic buffer containing m+1 bytes and each input sample is two 16-bit half-words (real and imaginary components). the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes and each output is two 16-bit half-words (real and imaginary components). the new output is stored in the address that follows the previous output. 16.3.4.3.2 fir3 function descriptor. the fir3 function descriptor bit table is described below. coefficients input samples real output (x=0) complex output (x=1) imag{c(0)} * * * real{c(0)} * * * imag{c(1)} imag {x(n-k+1)} * imag{y(n-k+1)} real{c(1)} real {x(n-k+1)} * real{y(n-k+1)} * * real {y(n-k+1)} * * imag {x(n-2)} * * imag{c(k-1)} real{x(n-2)} * imag{y(n-2)} real{c(k-1)} imag{x(n-1)} real {y(n-2)} real{y(n-2)} real{x(n-1)} real {y(n-1)} imag{y(n-1)} imag{x(n)} real {y(n)} real{y(n-1)} real{x(n)} imag{y(n)} real{y(n)} 2k bytes m + 1 bytes n + 1 bytes n + 1 bytes figure 16-17. fir3 coefficients and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i z iall index pc res opcode offset + 2 i offset + 4 k offset + 6 cbase offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-48 mpc823e reference manual motorola dsp communication 16 processor module the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1, 9, and 10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. z complex output 0 = only the real component of the result is written to the output buffer. 1 = the real and imaginary parts of the result are written to the output buffer. iall auto-increment x for all iterations 0 = the x (input) data pointer is incremented (modulo m+1) by the number of samples specified in the index field after the last iteration. 1 = the x data pointer is incremented (modulo m+1) by the number of samples specified in the index field after each iteration. index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. pc preset coefficients pointer 0 = the coefficients pointer is not preset after each iteration. 1 = the coefficients pointer is preset after each iteration to the cbase pointer. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field.
communication processor module motorola mpc823e reference manual 16-49 dsp communication 16 processor module 16.3.4.3.3 fir3 parameter packet. the fir3 parameter packet is composed of seven 16-bit half-words and described in the table below. 16.3.4.3.4 application example. the fir3 with the real output is used in echo cancellation and the one with the complex output is used in the equalizer. table 16-10. fir3 parameter packet address name description half-word 1 i number of iterations half-word 2 k number of taps-1 half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (2 samples). half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size for x=1 is 8 (2 outputs). the minimum output buffer size for x=0 is 4 (2 outputs). half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i 0 0 01 0 0 0 00011 offset + 2 i=3 (three iterations)
communication processor module 16-50 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.4 fir5Ccomplex c, complex x, and complex y. the fir5 function implements a basic fir filter with k complex coefficients, complex input samples, and complex output. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. the fir5 only uses other input data samples to implement a fractionally spaced equalizer. 16.3.4.4.1 coefficients and sample data buffers. the coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and c(0) is stored in the first location. the sample input buffer is a cyclic buffer containing m+1 bytes. each input sample is two 16-bit half-words (real and imaginary components) and the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes and the new output is stored in the address that follows the previous output. figure 16-18. fir5 implementation example t t t ? x(n) y(n) c(0) c(1) c(2) c(k-1) {complex} {complex} {complex} yn () cp () xn p C () p0 = k1 C ? =
communication processor module motorola mpc823e reference manual 16-51 dsp communication 16 processor module 16.3.4.4.2 fir5 function descriptor. the fir5 function descriptor bit table is described below. the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. coefficients input samples real output (x=0) complex output (x=1) imag{c(0)} * * * real{c(0)} * * * imag{c(1)} imag {x(n-k+1)} * imag{y(n-k+1)} real{c(1)} real {x(n-k+1)} * real{y(n-k+1)} * * y(n-k+1) * * imag {x(n-2)} * * imag{c(k-1)} real{x(n-2)} * imag{y(n-2)} real{c(k-1)} imag{x(n-1)} y(n-2) real{y(n-2)} real{x(n-1)} y(n-1) imag{y(n-1)} imag{x(n)} y(n) real{y(n-1)} real{x(n)} imag{y(n)} real{y(n)} 2k bytes m + 1 bytes n + 1 bytes n + 1 bytes figure 16-19. fir5 coefficients and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i z iall index pc res opcode offset + 2 i offset + 4 k offset + 6 cbase offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-52 mpc823e reference manual motorola dsp communication 16 processor module bits 1, 9, and 10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. z complex output 0 = only the real component of the result is written to the output buffer. 1 = the real and the imaginary parts of the result is written to the output buffer. iall auto-increment x for all iterations 0 = the x (input) data pointer is incremented (modulo m+1) by the number of samples specified in the index field after the last iteration. 1 = the x data pointer is incremented (modulo m+1) by the number of samples specified in the index field after each iteration. index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. pc preset coefficients pointer 0 = the coefficients pointer is not preset after each iteration. 1 = the coefficients pointer is preset after each iteration to the cbase pointer. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field.
communication processor module motorola mpc823e reference manual 16-53 dsp communication 16 processor module 16.3.4.4.3 fir5 parameter packet. the fir5 parameter packet is composed of seven 16-bit half-words and described in the table below. 16.3.4.4.4 application example. the fir5 function is used in the fractionally spaced equalizer. the following example demonstrates how the function descriptor structure can be used to implement a fractionally spaced equalizer. table 16-11. fir5 parameter packet address name description half-word 1 i number of iterations half-word 2 k number of taps-1. half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (2 samples). half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size for x=1 is 8 (2 outputs). the minimum output buffer size for x=0 is 4 (2 outputs). half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i 1 0 11 0 0 0 00101 offset + 2 i=1 (one iteration)
communication processor module 16-54 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.5 fir6Ccomplex c, real x, and complex y. the fir6 function implements a basic fir filter with k complex coefficients, real input samples, and complex output. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. 16.3.4.5.1 coefficients and sample data buffers. the coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and c(0) is stored in the first location. the sample input buffer is a cyclic buffer containing m+1 bytes and each sample is a 16-bit half-word. the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes and the new output is stored in the address that follows the previous output. figure 16-20. fir6 implementation example t t t ? x(n) y(n) c(0) c(1) c(2) c(k-1) {real} {complex} {complex} yn () cp () xn p C () p0 = k1 C ? =
communication processor module motorola mpc823e reference manual 16-55 dsp communication 16 processor module 16.3.4.5.2 fir6 function descriptor. the fir6 function descriptor bit table is described below. the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. coefficients input samples output imag{c(0)} * * real{c(0)} * * imag{c(1)} x(n-k+1) * real{c(1)} * imag{y(n-k+1)} * * real{y(n-k+1)} * x(n-2) * imag{c(k-1)} x(n-1) * real{c(k-1)} x(n) imag{y(n-2)} real{y(n-2)} imag{y(n-1)} real{y(n-1)} imag{y(n)} real{y(n)} 2k bytes m + 1 bytes n + 1 bytes figure 16-21. fir6 coefficients and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i res iall index pc res opcode offset + 2 i offset + 4 k offset + 6 cbase offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-56 mpc823e reference manual motorola dsp communication 16 processor module bits 1, 4, 9, and 10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. iall auto increment x for all iterations 0 = the x (input) data pointer is incremented (modulo m+1) by the number of samples specified in the index field after the last iteration. 1 = the x data pointer is incremented (modulo m+1) by the number of samples specified in the index field after each iteration. index auto increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. pc preset coefficients pointer 0 = the coefficients pointer is not preset after each iteration. 1 = the coefficients pointer is preset after each iteration to the cbase pointer. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field.
communication processor module motorola mpc823e reference manual 16-57 dsp communication 16 processor module 16.3.4.5.3 fir6 parameter packet. the fir6 parameter packet is composed of seven 16-bit half-words and described in the table below. 16.3.4.6 iirCreal c, real x, real y. the iir function implements a basic biquad iir filter with six real coefficients, real input samples, and real outputs. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. several stages of the biquad filter can be cascaded by specifying an iteration count greater than one and concatenating the filter coefficients into one vector. 16.3.4.6.1 coefficients and sample data buffers. the coefficients vector occupies six 16-bit half-words in memory and c(0) is stored in the first location. c(1) is only used in the last stage of a cascaded iir filter. the sample input buffer is a cyclic buffer that contains m+1 bytes. each sample is a 16-bit half-word and the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes and the new output is stored in the address that follows the previous one. table 16-12. fir6 parameter packet address name description half-word 1 i number of iterations-1 (0 = one iteration) half-word 2 k number of taps-1. the number of taps must be a multiple of 2. half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 4(2 samples). half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size is 8 (2 outputs). half-word 7 res reserved figure 16-22. iir implementation example c(4) c(2) c(1) t t ? x(n) y(n) c(0) c(5) {real} {real} {real} ? c(3) ? ?
communication processor module 16-58 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.6.2 iir function descriptor. the iir function descriptor bit table is described below. the first half-word is composed of the following bits: sstop 0 = do not stop after executiing this function descriptor. 1 = stop after executing this function descriptor. bits 1, 4C5, and 8C10reserved these bits are reserved and must be set to 0. coefficients input samples output c(0) * * c(1) * * c(2) x(n-k+1) * c(3) * * c(4) * y(n-k+1) c(5) x(n-2) * x(n-1) * x(n) y(n-2) y(n-1) y(n) 2k bytes m + 1 bytes n + 1 bytes figure 16-23. iir coefficients and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i res index res opcode offset + 2 i offset + 4 tptr offset + 6 cbase offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module motorola mpc823e reference manual 16-59 dsp communication 16 processor module wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field. 16.3.4.6.3 iir parameter packet. the iir parameter packet is composed of seven 16-bit half-words and described in the table below. 16.3.4.6.4 application example. among other things, the iir is used in timing recovery and an interpolating filter. table 16-13. iir parameter packet address name description half-word 1 i number of iterations (= cascaded stages) half-word 2 tptr pointer to temp delay line(s) pointer half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 4 (2 samples). half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size is 4 (2 outputs). half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i 0 0 index 0 0 0 00111 offset + 2 i=1 (one iteration)
communication processor module 16-60 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.7 modCreal sin, real cos, complex x, and real/complex y. the mod function implements a basic modulator function with a modulation table composed of {cos w nt, sin w nt} pairs, complex input samples, and real outputs. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. 16.3.4.7.1 modulation table and sample data buffers. the modulation table is composed of 16-bit cosine and sine pairs that occupy k+1 bytes in memory. the sample input buffer is a cyclic buffer containing m+1 bytes. each sample is a pair of 16-bit half-words (real and imaginary components) and the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contain n+1 bytes and the new output is stored in the address that follows the previous output. the output buffer can be real or complex, depending on the x bit in the function descriptor. figure 16-24. mod implementation example modulation table input samples output (real) output (complex) sin q 1 *** cos q 1 *** sin q 2 imag {x(n-k+1)} * * cos q 2 real {x(n-k+1)} real{y(n-k+1)} imag{y(n-k+1)} * * * real{y(n-k+1)} * imag {x(n-2)} * * sin q n real{x(n-2)} real{y(n-2)} * cos q n imag{x(n-1)} real{y(n-1) imag{y(n-2)} real{x(n-1)} real{y(n)} real{y(n-2)} imag{x(n)} imag{y(n-1)} real{x(n)} real{y(n-1)} imag{y(n)} real{y(n)} k + 1 bytes m + 1 bytes n + 1 bytes n + 1 bytes figure 16-25. mod table and sample data buffers cos w nt, sin w nt {real} x(n) y(n) {complex} {real or complex} real y n () {} real x n () {} w nt cos imag xn () {} w nt sin e = imag yn () {} real x n () {} w nt sin imag xn () {} w nt cos + =
communication processor module motorola mpc823e reference manual 16-61 dsp communication 16 processor module 16.3.4.7.2 mod function descriptor. the mod function descriptor bit table is described below. the first word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1 and 5C10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. z complex output 0 = only the real component of the result is written to the output buffer. 1 = the real and imaginary parts of the result is written to the output buffer. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this table. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i z res opcode offset + 2 i offset + 4 k offset + 6 mptr offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-62 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.7.3 mod parameter packet. the mod parameter packet is composed of seven 16-bit half-words and is described in the table below. 16.3.4.7.4 application example. the mod is used in the modulator. the following example demonstrates how the function descriptor structure can be used to implement the mod functions. 16.3.4.8 demodCreal sin; real cos, real x, and complex y. the demod function implements a basic demodulator function with a modulation table composed of (cos w nt, sin w nt) pairs, real input samples, and complex outputs. the input data is in a circular buffer with size m+1 and the output data is in a circular buffer with size n+1. the agc parameter controls the demodulator gain. table 16-14. mod parameter packet address name description half-word 1 i number of iterations half-word 2 k modulation table size-1. the minimum modulation table size is 8 (2 sin/cos pairs). half-word 3 mptr pointer to modulation table pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (2 samples). half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size for x=1 is 8 (2 outputs). the minimum output buffer size for x=0 is 4 (2 samples). half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 0 11 12 13 14 15 offset + 0 s0wi 0000000 01000 offset + 2 i=3 (three iterations) figure 16-26. demod implementation example cos w nt, sin w nt, agc {real} x(n) y(n) {real} {complex} real y n () {} 1 agc + () x n () w nt cos = imag yn () {} 1 agc + () x n () w nt sin C () =
communication processor module motorola mpc823e reference manual 16-63 dsp communication 16 processor module 16.3.4.8.1 modulation table, sample data buffers, and agc constant. the modulation table is composed of 16-bit cosine and sine pairs that occupy k +1 bytes in memory. the samples input buffer is a cyclic buffer containing m+1 bytes. each sample is a 16-bit half-word and the new sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes and the new output is stored in the address that follows the previous output. the agc constant is in the range -1 agc 1. 16.3.4.8.2 demod function descriptor. the demod function descriptor bit table is described below. modulation table input samples output (complex) sin q 1 ** cos q 1 ** sin q 2 ** cos q 2 * imag{y(n-k+1)} * x(n-k+1) real{y(n-k+1)} ** * sin q n ** cos q n x(n-2) imag{y(n-2)} x(n-1) real{y(n-2)} x(n) imag{y(n-1)} real{y(n-1)} imag{y(n)} real{y(n)} k + 1 bytes m + 1 bytes n + 1 bytes figure 16-27. demod modulation table and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i res opcode offset + 2 i offset + 4 k offset + 6 dptr offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-64 mpc823e reference manual motorola dsp communication 16 processor module the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1, 4C10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field. 16.3.4.8.3 demod parameter packet. the demod parameter packet is composed of seven 16-bit half-words and is described in the table below. table 16-15. demod parameter packet address name description half-word 1 i number of iterations half-word 2 k modulation table size-1. the minimum modulation table size is 8 (2 sin/cos pairs). half-word 3 dptr pointer to modulation table pointer and agc constant half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (2 samples). half-word 5 xyptr pointer to a structure composed of the input sample data pointer and the output buffer pointer half-word 6 n output buffer size-1. the minimum output buffer size is 8 (2 outputs). half-word 7 res reserved
communication processor module motorola mpc823e reference manual 16-65 dsp communication 16 processor module 16.3.4.8.4 application example. the demod is used in the modulator. the following example demonstrates how the function descriptor structure can be used to implement the mod function. 16.3.4.9 lms1Ccomplex coefficients, complex samples, and real/complex scalar . the lms1 function implements a basic fir filter coefficients update. the coefficients and input samples are complex numbers, but the scalar is a real or complex number. 16.3.4.9.1 coefficients and sample data buffers. the coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and c(0) is stored in the first location. the samples input buffer is a cyclic buffer that contain m+1 bytes. each sample is a pair of 16-bit half-words (real and imaginary components) and the new sample is stored in the address that follows the previous sample. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s0wi 0000000 01001 offset + 2 i=3 (three iterations) figure 16-28. lms1 implementation example coefficients input samples imag{c(0)} * real{c(0)} * imag{c(1)} * real{c(1)} imag{x(n-k+1)} * real{x(n-k+1)} ** imag{c(k-1)} * real{c(k-1)} imag{x(n-2)} real{x(n-2)} imag{x(n-1)} real{x(n-1)} imag{x(n)} real{x(n)} 2k bytes m + 1 bytes figure 16-29. lms1 coefficients and sample data buffers c n1 + i c n i ex ni C + =
communication processor module 16-66 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.9.2 lms1 function descriptor. the lms1 function descriptor bit table is described below. the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and the overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. z complex scalar 0 = the scalar (e) is a real number. 1 = the scalar (e) is a complex number. index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i z res index res opcode offset + 2 reserved offset + 4 k offset + 6 cbase offset + 8 m offset + a xyptr offset + c eptr offset + e reserved
communication processor module motorola mpc823e reference manual 16-67 dsp communication 16 processor module 16.3.4.9.3 lms1 parameter packet. the lms1 parameter packet is composed of seven 16-bit half-words and is described in the table below. 16.3.4.9.4 application example. the lms1 is used in the echo cancellation update. 16.3.4.10 lms2Ccomplex coefficients, complex samples, and real/complex scalar. the lms2 function implements a basic fir filter coefficients update and the sample pointer is incremented by two, which is required for fractionally spaced equalizer updates. the coefficients and input samples are complex numbers, but the scalar is a real or complex number. table 16-16. lms1 parameter packet address name description half-word 1 res reserved half-word 2 k number of taps-1. half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (2 samples). half-word 5 xyptr pointer to new sample data pointer half-word 6 eptr pointer to scalar half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i z 0 index 0 0 0 01010 offset + 2 i=1 (one iteration) figure 16-30. lms2 implementation example c n1 + i c n i ex ni C + =
communication processor module 16-68 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.10.1 coefficients and sample data buffers. the coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and c(0) is stored in the first location. the sample input buffer is a cyclic buffer containing m+1 bytes. each sample is a pair of 16-bit half-words (real and imaginary components) and the new sample is stored in the address that follows the previous sample. 16.3.4.10.2 lms2 function descriptor. the lms2 function descriptor bit table is described below. coefficients input samples imag{c(0)} * real{c(0)} * imag{c(1)} * real{c(1)} imag{x(n-k+1)} * real{x(n-k+1)} ** imag{c(k-1)} * real{c(k-1)} imag{x(n-2)} real{x(n-2)} imag{x(n-1)} real{x(n-1)} imag{x(n)} real{x(n)} 2k bytes m + 1 bytes figure 16-31. lms2 coefficients and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i z res index res opcode offset + 2 reserved offset + 4 k offset + 6 cbase offset + 8 m offset + a xptr offset + c eptr offset + e reserved
communication processor module motorola mpc823e reference manual 16-69 dsp communication 16 processor module the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1, 5, and 8C10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. z complex scalar 0 = the scalar (e) is a real number. 1 = the scalar (e) is a complex number. index auto-increment index 00 = the x (input) pointer is not incremented. 01 = the x (input) pointer is incremented by one sample. 10 = the x (input) pointer is incremented by two samples. 11 = the x (input) pointer is incremented by three samples. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field.
communication processor module 16-70 mpc823e reference manual motorola dsp communication 16 processor module 16.3.4.10.3 lms2 parameter packet. the lms2 parameter packet is composed of seven 16-bit half-words and is described in the table below. 16.3.4.10.4 application example. the lms2 function is used in the fractionally spaced equalizer coefficient update. 16.3.4.11 waddCreal x and real y. the wadd function receives two real vectors and two real coefficients ( a and b) as inputs. the function generates an output vector that is the linear combination between the two input vectors, according to a and b . it is a special case when b = 1 - a and (0 a 1) generates a linear interpolation between the two input vectors. table 16-17. lms2 parameter packet address name description half-word 1 res reserved half-word 2 k number of taps-1. half-word 3 cbase filter coefficients vector base address pointer half-word 4 m samples buffer size-1. the minimum sample buffer size is 8 (2 samples). half-word 5 xptr pointer to new sample data pointer half-word 6 eptr pointer to scalar half-word 7 res reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s 0 w i z 0 index 0 0 0 01011 offset + 2 i=1 (one iteration) figure 16-32. wadd implementation example yn () a x 1 n () b x 2 n () + =
communication processor module motorola mpc823e reference manual 16-71 dsp communication 16 processor module 16.3.4.11.1 coefficients and sample data buffers. each input vector is stored in a cyclic buffer containing m+1 bytes. each sample is a 16-bit half-word and the newest sample is stored in the address that follows the previous sample. the output buffer is a cyclic buffer that contains n+1 bytes. each output is a 16-bit half-word and the newest output is stored in the address that follows the previous one. 16.3.4.11.2 wadd function descriptor. the wadd function descriptor bit table is described below. x 1 input samples x 2 input samples output ** * x 1 (n-k+1) * * *x 2 (n-k+1) * ** * x 1 (n-2) * y(n-k+1) x 1 (n-1) x 2 (n-2) * x 1 (n) x 2 (n-1) * x 2 (n) y(n-2) y(n-1) y(n) 2k bytes m + 1 bytes n + 1 length buffer figure 16-33. wadd modulation table and sample data buffers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 s res w i res opcode offset + 2 i offset + 4 a offset + 6 b offset + 8 m offset + a xyptr offset + c n offset + e reserved
communication processor module 16-72 mpc823e reference manual motorola dsp communication 16 processor module the first half-word is composed of the following bits: sstop 0 = do not stop after executing this function descriptor. 1 = stop after executing this function descriptor. bits 1 and 4C10reserved these bits are reserved and must be set to 0. wwrap (final function descriptor in table) 0 = this is not the last function descriptor in the function descriptor table. 1 = this is the last function descriptor in the function descriptor table. after this buffer has been used, the cpm processes the first function descriptor that the fdbase index pointer points to in the table. the number of function descriptors in this table are programmable and determined only by the w bit and overall space constraints of the memory. iinterrupt 0 = no interrupt is generated after this function is processed. 1 = a maskable interrupt is generated after this function is processed. opcodefunction operation code this field specifies the function to be executed. table 16-6 contains the value for this field. 16.3.4.11.3 wadd parameter packet. the wadd parameter packet is composed of seven 16-bit half-words and is described in the table below. table 16-18. wadd parameter packet address name description half-word 1 i number of iterations half-word 2 a x 1 weight coefficient half-word 3 b x 2 weight coefficient half-word 4 m samples buffer size-1 half-word 5 xyptr pointer to a structure composed of x 1 input sample data pointer, output buffer pointer, and the x 2 input sample data pointer. half-word 6 eptr output buffer size-1 half-word 7 res reserved
communication processor module motorola mpc823e reference manual 16-73 dsp communication 16 processor module 16.3.4.11.4 application example. by specifying different values, several functions can be implemented as shown in the table below. 16.3.4.12 the dsp execution times. a functions execution time is a linear function of the number of taps and iterations specified for that function. it includes overhead for context-switch, function descriptor handling, and initialization. table 16-20 lists the execution time for each of the dsp functions. table 16-19. wadd functions a b function 0 a 3 11- a linear interpolation a 0 y(n) = a x (n) scalar multiply 1 -1 y(n) = x 1 (n) - x 2 (n) vector subtract table 16-20. dsp functions execution times function execution time fir1 53 + 20 * ( i - 1) + 1.25 * i * (k+1) fir2 47 + 17 * ( i -1) + 3 * i * (k+1) fir3 44 + 14 * ( i - 1) + 4 * i * (k+1) fir5 44 + 14 * ( i - 1) + 5 * i * (k+1) fir6 50 + 20 * ( i - 1) + 3 * i * (k+1) iir 44 + 11 * i mod 44 + 7 * i demod 47 + 14 * i lms1 42 + 7 * (k+1) lms2 42 + 7 * (k+1) wadd 46 + 7 * i notes: 1. add 1 clock for wrap, 5 clocks for stop, and 4 clocks for interrupt. 2. i = number of iterations. 3. k+1 = number of taps.
communication processor module 16-74 mpc823e reference manual motorola timers communication 16 processor module 16.4 timers the communication processor module includes four identical 16-bit general-purpose timers that can be cascaded into two 32-bit timers. each general-purpose timer consists of a timer mode register, a timer capture register, a timer counter, a timer reference register, a timer event register, and a timer global configuration register. the timer mode register contains the prescaler value that you program. the timer block diagram is illustrated in figure 16-34. 16.4.1 features the following list summarizes the main features of the timers: ? maximum period of 10.7 seconds (at 25mhz) ? minimum 40ns resolution (at 25mhz) ? programmable sources for the clock input ? input capture capability ? output compare with programmable mode for the output pin ? four timers can be internally or externally cascaded to form two 32-bit timers. timer 1 exclusive-ored with spkr input from pcmcia to generate spkrout ? free run and restart modes figure 16-34. timer block diagram timer clock generator capture detection event register mode register mode bits prescaler timer counter capture register reference register divider clock ter1 tmr1 tcn1 trr1 tcr1 tin1 tout1 timer1 timer2 global configuration register tgcr tin2 tout2 general system clock cpm local bus tin3 tin4 timer3 timer4 tgate1
communication processor module motorola mpc823e reference manual 16-75 communication 16 processor module timers 16.4.2 timer operation the clock input to the prescaler can be selected from three sources: ? the general system clock ? the general system clock divided by 16 ? the corresponding tinx pin the general system clock is generated in the clock synthesizer and defaults to the system frequency (25 or 50mhz). however, the general system clock has the option to be divided before it leaves the clock synthesizer. this mode, called normal low, is used to save power. whatever the resulting frequency of the general system clock, you can either choose that frequency or the frequency divided by 16 as the input to the prescaler of each timer. on the other hand, you may prefer that the tinx pin be the clock source because it is internally synchronized to the internal clock. the clock input source is selected by the iclk field of the corresponding timer mode register. the prescaler is programmed to divide the clock input by values between 1 and 256 and the output of the prescaler is used as an input to the 16-bit counter. the best resolution of the timer is one clock cycle (40ns at 25mhz). the maximum period is 268,435,456 cycles, which is 10.7 seconds at 25mhz. both values assume that the general system clock is the full 25mhz. each timer can be configured to count until a reference is reached and then either begin a new time count immediately or continue running. the frr bit of the corresponding timer mode register selects each mode. when the reference value is reached, the corresponding bit in the timer event register is set and an interrupt is issued if the ori bit in the timer mode register is set. timers 1 and 2 can output a signal on the timer output pin (tout 1 and tou t2 ) when the reference value is reached or selected by the om bit of the corresponding timer mode 1 or 2 register. this signal can be an active-low pulse or a toggle of the current output. timer 1 is exclusive-or'ed with the spkr input signal to generate spkrout. this allows the system to output simple frequencies for alerts. to prevent this timer from affecting spkrout, choose one of the other timers or set this timer to a pulse mode. in addition, each timer has a 16-bit timer capture register that is used to latch the value of the counter when a defined transition of the tin1, tin2, tin3, or tin4 pin is sensed by the corresponding input capture edge detector. the type of transition triggering the capture is selected by the ce field in the corresponding timer mode register. when a capture or reference event occurs, the corresponding bit in the timer event register is set and a maskable interrupt request is issued to the cpm interrupt controller. timers 1 and 2 can be gated or restarted using the tgate1 signal (timers 3 and 4 cannot be gated). normal gate mode enables the count on the falling edge of the tgate1 pin and disables the count on the rising edge of the tgate1 pin. this mode allows the timer to count conditionally, depending on the state of the tgate1 pin. timers
communication processor module 16-76 mpc823e reference manual motorola timers communication 16 processor module restart gate mode performs the same function as normal mode, except it also resets the counter on the falling edge of the tgate1 pin. this mode can be used in the following applications: ? pulse measurementthe restart gate mode can measure a low pulse on the tgate1 pin. the rising edge of the tgate1 pin completes the measurement and if tgate1 is externally connected to tinx, it causes the timer to capture the count value and generate a rising-edge interrupt. ? bus monitoring the restart gate mode can detect a signal that is abnormally stuck low. the bus signal must be connected to the tgate1 pin. the timer count is reset on the falling edge of the bus signal and if the bus signal does not go high again within the number of user-defined clocks, an interrupt can be generated. the gate function is enabled in the timer mode register and the gate operating mode is selected in the timer global configuration register. 16.4.2.1 cascaded mode. in this mode, the 16-bit timers can be internally cascaded into a 32-bit counter. since the decision to cascade timers is made independently, you have the option of selecting four 16-bit timers or two 32-bit timers. the timer global configuration register is used to set the timers to cascaded mode, as shown in figure 16-35. if the cas2 bit is set in the timer global configuration register, the two timers function as a 32-bit timer with a 32-bit timer reference register, timer capture register, and timer counter. in this case, timers 1 and 3 are ignored and timers 2 and 4 must be used to define the mode. the capture is controlled by the tin2 pin and the interrupts are generated by the timer event 2 register. when operating in cascaded mode, the cascaded timer reference register, timer capture register, and timer counter must always be referenced with 32-bit bus cycles. note: tgate1 is internally synchronized to the timebase clock (tmbclk). if it meets the asynchronous input setup time, then (when working with the internal clock) the counter begins counting after one system clock. figure 16-35. timer cascaded mode block diagram timer3 timer4 capture clock trr, tcr, tcn connected to data bus trr, tcr, tcn connected to data bus pins 31-16. pins 15-0. timer1 timer2 clock capture trr, tcr, tcn connected to data bus trr, tcr, tcn connected to data bus pins 31-16. pins 15-0.
communication processor module motorola mpc823e reference manual 16-77 communication 16 processor module timers 16.4.2.2 timer global configuration register. the 16-bit, memory-mapped, read/write timer global configuration register (tgcr) contains configuration parameters that are used by both timers. it allows simultaneous starting and stopping of any number of timers as long as one bus cycle is used to access tgcr. cas4cascade timers 0 = normal operation. 1 = timers 3 and 4 are cascaded to form a 32-bit timer. frz4Cfrz1freeze 0 = the corresponding timer ignores the frz pin. 1 = stops the corresponding timer if the frz pin is asserted by the core during breakpoint. stp4Cstp1 stop timer 0 = normal operation. 1 = reduce the timers power consumption. this bit stops all clocks to the timer, except the clock from the u-bus interface, which allows you to read and write the timer registers. the clocks to the timer remain inactive until you clear this bit or a hardware reset occurs. rst4Crst1reset timer 0 = reset the corresponding timer. a software reset is identical to an external reset. 1 = enable the corresponding timer if the stpx bit is cleared. bit 4reserved this bit is reserved and must be set to 0. cas2cascade timers 0 = normal operation. 1 = timers 1 and 2 are cascaded to form a 32-bit timer. tgcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cas4 frz4 stp4 rst4 res frz3 stp3 rst3 cas2 frz2 stp2 rst2 gm1 frz1 stp1 rst1 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x980
communication processor module 16-78 mpc823e reference manual motorola timers communication 16 processor module gm1gate mode for pin 1 this bit is only valid if the gate function is enabled in timer 1 or 2. 0 = restart gate mode. a falling tgate1 pin enables and restarts the count and a rising edge of tgate1 disables the count. 1 = normal gate mode. this mode is the same as 0, except the falling edge of the tgate1 pin does not restart the count value in the timer counter. 16.4.2.3 timer mode registers. the 16-bit, memory-mapped, read/write timer mode registers (tmr1Ctmr4) are identical and cleared by reset. to avoid erratic behavior, the tgcr must be initialized before the tmrx register. the only exception is that the rst bit in the tgcr can be modified at any time. psprescaler value the prescaler is programmed to divide the clock input by a value between 1 and 256. a 00000000 value divides the clock by 1 and 11111111 divides it by 256. cecapture edge and enable interrupt 00 = disable interrupt on capture event; capture function is disabled. 01 = capture on rising tinx edge only and enable interrupt on capture event. 10 = capture on falling tinx edge only and enable interrupt on capture event. 11 = capture on any tinx edge and enable interrupt on capture event. omoutput mode (only valid for tmr1 and tmr2) 0 = active-low pulse on tout1 or tout2 for one timer input clock cycle as defined by the iclk bits. thus, toutx may be low for one general system clock period, one general system clock/16 period, or one tinx pin clock cycle period. changes to toutx occur on the falling edge of the system clock. 1 = toggle the toutx pin. changes to toutx occur on the falling edge of the system clock. orioutput reference interrupt enable 0 = disable interrupt for reference that is reached. this does not affect an interrupt on the capture function. 1 = enable interrupt when the reference value is reached. tmr1Ctmr4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ps ce om ori frr iclk ge reset 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x990 (tmr1), 0x992 (tmr2), 0x9a0 (tmr3), 0x9a2 (tmr4)
communication processor module motorola mpc823e reference manual 16-79 communication 16 processor module timers frrfree run/restart 0 = free run. the timer count continues to increment after the reference value is reached. 1 = restart. the timer count is reset immediately after the reference value is reached. iclkinput clock source for the timer 00 = internally cascaded input. for tmr1, the timer 1 input is the output of timer 2. for tmr3, the timer 3 input is the output of timer 4. for tmr2 and tmr4, this selection means no input clock is provided to the timer. 01 = internal general system clock. 10 = internal general system clock divided by 16. 11 = corresponding tinx pin (falling edge). gegate enable 0 = the tgate1 signal is ignored. 1 = the tgate1 signal is used to control the timer. 16.4.2.4 timer reference registers. each of the 16-bit, memory-mapped, read/write timer reference registers (trr1Ctrr4) contain the timeouts reference value. referencereference to tcnx this reference value is reached when the tcnx register increments to equal the trrx register. trr1Ctrr4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reference reset 1 r/w r/w addr (immr & 0xffff0000) + 0x994 (trr1), 0x996 (trr2), 0x9a4 (trr3), 0x9a6 (trr4)
communication processor module 16-80 mpc823e reference manual motorola timers communication 16 processor module 16.4.2.5 timer capture registers. each of the 16-bit, memory-mapped, read-only timer capture registers (tcr1Ctcr4) are used to latch the value of the counter at the falling edge of every tinx signal. the ce field in the tmrx register defines whether the counter starts at the rising or falling edge of the tinx signal. capture count this field contains the value of the timer counter register at the falling edge of the tinx signal. 16.4.2.6 timer counter registers. each of the 16-bit, memory-mapped, read/write timer counter (tcn1 and tcn4) registers are up-counters. in timer capture mode, the tinx signal defines when the counter begins. a read to tcnx yields the current value of the timer, but does not affect the counting operation. a write to tcnx sets the register to that value, which causes the corresponding prescaler in the ps field of the tmrx register to be reset. countcounter value this represents the value of the counter. tcr1Ctcr4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field capture count reset 0 r/w r addr (immr & 0xffff0000) + 0x998 (tcr1), 0x99a (tcr2), 0x9a8 (tcr3), 0x9aa (tcr4) tcn1Ctcn4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field count reset r/w r/w addr (immr & 0xffff0000) + 0x99c (tcn1), 0x99e (tcn2), 0x9ac (tcn3), 0x9ae (tcn4) note: = undefined. note: the tcnx register may not be updated correctly if a write is made to it while the timer is not running. you must always use the trrx register to define the preferred counter value.
communication processor module motorola mpc823e reference manual 16-81 communication 16 processor module timers 16.4.2.7 timer event registers. each of the 16-bit, memory-mapped timer event registers (ter1Cter4) are used to report events recognized by the timers. when an output reference event is recognized, the timer sets the ref bit, regardless of the corresponding ori bit in the tmrx register. the capture event is only set if it is enabled by the ce field in the tmrx register. these registers can be read at any time and are cleared at reset. a bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset at a time. however, both bits must be reset before the timer can negate the interrupt to the cpm interrupt controller. bits 0C13reserved these bits are reserved and must be set to 0. refoutput reference event this bit signifies that the counter has reached the value in the trrx register. the ori bit in the tmrx register is used to enable the interrupt request caused by this event. capcapture event this bit signifies that the counter value has been latched into the tcrx register. the ce field in the tmrx register is used to enable generation of this event. 16.4.3 initializing the timers the following is an example of timer 2s initialization sequence that is required to generate an interrupt every 10 microseconds, assuming a 25mhz general system clock. an interrupt must be generated after each 250 system clock. 1. write 0x0000 to the tgcr. this puts timer 2 into a reset state. cascaded mode is not used here. 2. write 0x001a to the tmr2. this enables the timers prescaler to divide by 1 and sets the clock source to general system clock. it also enables an interrupt to occur when the reference value is reached and restarts the timer to continuously generate 10ms interrupts. 3. write 0x0000 to the tcn2. this initializes the timer 2 count to zero (default state of this register). 4. write 0x00fa to the trr2. this initializes the timer 2 reference value to 250 (decimal). ter1Cter4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved ref cap reset 000 addr (immr & 0xffff0000) + 0x9b0 (ter1), 0x9b2 (ter2), 0x9b4 (ter3), 0x9b6 (ter4)
communication processor module 16-82 mpc823e reference manual motorola sdma communication 16 processor module 5. write 0xffff to the ter2. this clears the ter2 of any bits that might have been set. 6. write 0x00040000 to the cimr. this enables a timer 2 interrupt in the cpm interrupt controller and initializes the cicr. 7. write 0x0010 to the tgcr. this enables timer 2 to begin counting. to implement the same function with a 32-bit timer using timers 1 and 2, follow these steps: 1. write 0x0080 to the tgcr. this cascades timers 1 and 2 and puts them in a reset state. 2. write 0x001a to the tmr2. this enables the timer 2 prescaler to divide by 1 and the clock source to the general system clock. it also enables an interrupt when the reference value is reached and restarts the timer to continuously generate 10ms interrupts. 3. write 0x0000 to the tmr1. this enables timer 1 to use the output of timer 2 as its input (default of tmr1). 4. write 0x0000 to the tcn1 and 0x0000 to the tcn2. this initializes the count of the combined timers 1 and 2 to zero (default of tmr1) by using one 32-bit data move to tcn1. 5. write 0x0000 to the trr1 and 0x00fa to the trr2. this initializes the reference value of the combined timers 1 and 2 to 250 by using one 32-bit data move to trr1. 6. write 0xffff to the ter2. this clears the ter2 of any bits that might have been set. 7. write 0x00040000 to the cimr. this enables the timer 2 interrupt in the cpm interrupt controller and initializes the cicr. 8. write 0x0091 to the tgcr. this enables timers 1 and 2 to begin counting, but leaves them in cascaded mode. 16.5 the sdma channels the mpc823e has two physical serial dma (sdma) channels. one is controlled by the risc microcontroller and the other is controlled by the lcd controller. the risc microcontroller implements 12 virtual sdma channels and each one is associated with a serial channel transmitter or receiver. four channels are associated with the full-duplex serial communication controllers and the other eight are used for the serial peripheral interface, i 2 c controller, and serial management controllers. each channel is permanently assigned to service either the receive or transmit operation of a serial communication controller, serial management controller, serial peripheral interface, or i 2 c controller. data from these controllers can be routed to the external ram (path 1) or the internal dual-port ram (path 2) with the u-bus. figure 16-36 illustrates the paths of the data flow. on a path 1 access, the u-bus and external system bus must be acquired by the sdma channel. on a path 2 access, only the u-bus needs to be acquired and the access is not seen on the external system bus, unless the mpc823e is configured into the show cycles mode of the system interface unit. thus, transfers on the u-bus occur at the same time that other operations occur on the external system bus.
communication processor module motorola mpc823e reference manual 16-83 sdma communication 16 processor module each sdma channel can be programmed to output one of eight function codes that identify the channel currently accessing memory. the sdma channel can be assigned a big-endian (motorola) or little-endian format for accessing buffer data. these features are programmed in the receive and transmit function code registers that are associated with the serial communication controllers, serial management controllers, serial peripheral interface, and i 2 c controller. if a bus error occurs when the sdma conducts a risc-related access, the communication processor module generates a unique interrupt in the risc status register. the interrupt service routine reads the sdma address register to determine the address that the bus error occurred on. the channel that caused the bus error can be found by reading the receive and transmit internal data pointers from the specific protocol parameters area in the parameter ram of the serial channels. if an sdma bus error occurs on a risc-related cycle, all cpm activity ceases and the entire communication processor module must be reset in the cpm command register (cpcr). figure 16-36. sdma data paths external ram external rom internal u-bus system spi usb scc2 smc1 smc2 i 2 c risc microcontroller sdma dual-port ram 2 1 interface unit scc3
communication processor module 16-84 mpc823e reference manual motorola sdma communication 16 processor module 16.5.1 sdma bus arbitration and transfers the instruction cache, data cache, system interface unit, and sdma can become internal bus masters whose relative priority can be determined by examining their arbitration ids. however, you can only adjust sdma arbitration. all other arbitration ids are fixed. all 12 sdma channels share the same id that you are responsible for programming. any sdma channel can arbitrate for the bus against the other existing internal or external masters. once an sdma channel obtains the system bus, it remains the bus master for one transaction (a byte, half-word, word, or burst) before relinquishing the bus. this feature, in combination with the zero clock arbitration overhead provided by the u-bus is beneficial to bus efficiency and low bus latency. with character-oriented protocols, the sdma writes characters to memory without waiting for multiple characters to be received first and it always reads words. this is consistent with the need to provide low-latency operation on character-oriented protocols that are used at slower rates. the read or write operation may take multiple bus cycles if the memory provides a less than 32-bit port size. for instance, a 32-bit word read from a 16-bit memory takes two sdma bus cycles. the entire operand (4-word burst, 32 bits on reads, and 8, 16, or 32 bits on writes) will be transferred in back-to-back bus cycles before the sdma relinquishes the bus. the sdma can steal cycles with no arbitration overhead when the mpc823e is bus master. figure 16-37. sdma bus arbitration clk ts ta other cycle sdma cycle other cycle sdma internally requests the bus
communication processor module motorola mpc823e reference manual 16-85 sdma communication 16 processor module 16.5.2 the sdma registers the sdma channels share a configuration register, address register, and status register. they are all controlled by the configuration of the serial communication controllers, serial management controllers, serial peripheral interface, and i 2 c controller. 16.5.2.1 sdma configuration register. the 32-bit sdma configuration register (sdcr) is used to configure all 16 sdma channels. it is always read/write in supervisor mode, even though writing to the sdcr is not recommended unless the communication processor module is disabled. the control provided by this register has interactions with the dma controllers in the lcd and video controller modules of the mpc823e. refer to section 18.3.6 dma control and section 18.3.1 fifo control for more information regarding those modules. bits 0C16reserved these bits are reserved and must be set to 0. frzfreeze this field determines the action to be taken when the frz signal is asserted. the sdma negates the br signal and keeps it that way until frz is negated or a reset occurs. 00 = the sdma channels ignore the frz signal. 01 = reserved. 10 = the sdma channels freeze on the next bus cycle. 11 = reserved. sdcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r addr (immr & 0xffff0000) + 0x030 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field res frz reserved lam reserved laid raid reset 00 0 0000 r/w r r r r/w r r r addr (immr & 0xffff0000) + 0x030
communication processor module 16-86 mpc823e reference manual motorola sdma communication 16 processor module lamlcd/video aggressive mode the use of aggressive mode (as determined by the lam, raid and laid fields) is not recommended for use above waiting on response. if used above waiting on response unexpected behavior will result. this behavior is caused by edge conflicts in the internal logic for this mode of operation. 0 = disable lcd aggressive mode. priority depends on the laid field. 1 = enable lcd aggressive mode. the laid and raid fields must be equal to 00. bits 19C24 and 26C27reserved these bits are reserved and must be set to 0. laidlcd controller arbitration id this field determines the lcd and video controller arbitration id. its value must be programmed to 00 for typical applications. 00 = the lcd controller uses u-bus arbitration priority 6 (highest). 01 = the lcd controller uses u-bus arbitration priority 5. 10 = the lcd controller uses u-bus arbitration priority 2. 11 = the lcd controller uses u-bus arbitration priority 1 (lowest). raidrisc controller arbitration id this field establishes the priority level of bus arbitration among modules that can become bus master. the instruction cache, data cache, system interface unit, and sdmas all compete for bus mastership. the sdma channel arbitration id is determined by the raid field. arbitration ids for all other bus masters are internally fixed. this value must be programmed to 01 for typical applications. 00 = the sdma uses u-bus arbitration priority 6 (highest). 01 = the sdma uses u-bus arbitration priority 5. 10 = the sdma uses u-bus arbitration priority 2. 11 = the sdma uses u-bus arbitration priority 1 (lowest). note: this bit affects all dma transfers, not just the lcd/video controller.
communication processor module motorola mpc823e reference manual 16-87 sdma communication 16 processor module 16.5.2.2 sdma status register. shared by all 12 sdma channels, the 8-bit memory-mapped sdma status register (sdsr) is used to report events recognized by the sdma controller. when an event is recognized, the sdma sets the corresponding bit in the sdsr. a bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset at a time. this register is cleared by reset and can be read at any time. sbersdma channel bus error (sdma function) this bit indicates that an error caused the sdma channel to be terminated during a read or write cycle. the sdma bus error address can be read from the sdma address register. bits 1C5reserved these bits are reserved and must be set to 0. dsp2dsp chain 2 transmitter interrupt (dsp function) this bit is set when the chain 2 function finishes executing. however, the i bit must be set in the function descriptor, as described in section 16.3.3.3 dsp event register . dsp1dsp chain 1 receiver interrupt (dsp function) this bit is set when the chain 1 function finishes executing. however, the i bit must be set in the function descriptor, as described in section 16.3.3.3 dsp event register . sdsr bit 0 1 2 3 4 5 6 7 field sber reserved dsp2 dsp1 reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x908
communication processor module 16-88 mpc823e reference manual motorola sdma communication 16 processor module 16.5.2.3 sdma mask register. the 8-bit read/write sdma mask register (sdmr) has the same bit format as the sdma status register. if a bit in the sdma mask register is a 1, the corresponding interrupt in the event register is enabled. if the bit is zero, the corresponding interrupt is masked. sbersdma channel bus error mask (sdma function) 0 = disable the sdma channel bus error interrupt. 1 = enable the sdma channel bus error interrupt. bits 1C5reserved these bits are reserved and must be set to 0. dsp2dsp chain 2 transmitter interrupt mask (dsp function) 0 = disable the dsp chain 2 transmitter interrupt, as described in section 16.3.3.3 dsp event register . 1 = enable the dsp chain 2 transmitter interrupt. dsp1dsp chain 1 receiver interrupt mask (dsp function) 0 = disable the dsp chain 1 receiver interrupt, as described in section 16.3.3.3 dsp event register . 1 = enable the dsp chain 1 receiver interrupt. sdmr bit 0 1 2 3 4 5 6 7 field sber reserved dsp2 dsp1 reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x90c
communication processor module motorola mpc823e reference manual 16-89 idma communication 16 processor module 16.5.2.4 sdma address register. the 32-bit read-only sdma address register (sdar) contains the system address that is accessed during an sdma bus error. it is undefined at reset. sbeasdma bus error address this field contains the system address accessed when the sdma encounters a bus error. 16.6 emulating idma using the idma-dedicated sdma channel, which is not part of the 12 channels, the risc microcontroller can be configured to provide a general-purpose dma functionality. two general-purpose independent dma (idma) channels are supported. in this special emulation mode, you can specify any memory-to-memory or peripheral-to-memory transfers to be implemented in the same way as dedicated dma hardware. the general-purpose idma controllers operate in different data transfer modes that you are responsible for programming. they can transfer data between any combination of memory and i/o. in addition, data can be transferred in byte, half-word, word, or burst quantities and the source and destination addresses can be odd or even. the most efficient packing algorithms are used in idma transfers. the single address mode performs the best because it allows data to be transferred between memory and the peripheral within a single bus cycle. the chip-select and wait-state generation logic on the mpc823e can be used with idma. idma supports three buffer handling modessingle buffer, autobuffer, and buffer chaining. the single buffer mode allows a single buffer peripheral to memory data transfer with single address (flyby) burst transfers. the autobuffer mode allows blocks of data to be repeatedly moved from one location to another without you having to intervene. the buffer chaining mode allows a chain of blocks to be moved sequentially. you specify how to move the data using buffer descriptors similar to those used by a serial communication controller. these buffer descriptions reside in the dual-port ram. sdar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field sbea reset r/w r addr (immr & 0xffff0000) + 0x904 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field sbea reset r/w r addr (immr & 0xffff0000) + 0x906 note: = undefined.
communication processor module 16-90 mpc823e referencemanual motorola idma communication 16 processor module 16.6.1 features the following is a list of the mpc823e idmas main features: ? two independent, fully programmable dma channels ? dual address or single address transfers with 32-bit address and data capability ? 32-bit byte transfer counters ? 32-bit address pointers that can increment or remain constant ? efficient operand packing and unpacking for dual address transfers ? all bus-termination modes are supported ? provides dma handshake for cycle steal and burst transfers ? buffer handling modes (auto buffer and buffer chaining) 16.6.2 idma interface signals the mpc823e idma has two dedicated control signals per channeldma request and dma acknowledge. idma accepts dma requests from the dreq1 and dreq2 signals and acknowledges the request with the sdack1 and sdack2 signals. the peripheral used with these signals can either be a source or destination of the idma transfers. the dreqx signals are also used for memory-to-memory request generation and, in this case, must be connected to the timer that controls the transfer. 16.6.2.1 dreq x and sdack x . these are the handshake signals between the mpc823e and the peripheral that needs to be serviced. when the peripheral asks for idma service, it asserts dreqx and the mpc823e begins the idma process. while the service is in progress, sdackx is asserted during accesses to the device. dreqx can be configured to be either edge- or level-sensitive by programming the drxm field in the rccr. the drqp field in the rccr control idma channel priority in relation to the serial channels. to enable the dreqx signals, the corresponding dreqx bit in the pcso register must be set. when the dreqx signals are configured as edge-sensitive requests, the edge on which a request is generated is controlled by the corresponding edmx bit in the pcint register. for more information about the port c registers, see section 16.14.9 port c registers . 16.6.3 idma operation every idma operation involves the following series of eventsidma channel initialization, data transfer, and block termination. in the initialization phase, the core loads the idma-specific parameter ram with control information, initializes the idma buffer descriptors, and starts the channel. in the transfer phase, idma accepts requests for operand transfers and provides addressing and bus control for the transfers. the termination phase occurs when the operation is complete and idma interrupts the core if interrupts are enabled. to initialize a block transfer operation, you must initialize the idma registers. the idma buffer descriptors must be initialized with information describing the data block, device type, and other special control options. refer to section 16.6.3.2 idma parameter ram memory map and section 16.6.3.6 idma commands for more details.
communication processor module motorola mpc823e reference manual 16-91 idma communication 16 processor module follow these steps to perform an idma transfer: 1. define the source (peripheral) address to be burst aligned. 2. define the destination address to be burst aligned. 3. program the idma mode register (dcmr) to 0x0000. 16.6.3.1 autobuffer and buffer chaining. the host cpu must initialize the idma buffer descriptor ring with the appropriate buffer handling mode, source address, destination address, and block length. the data associated with each idma channel for autobuffer and buffer chaining modes is stored in buffers and each buffer is referenced by a buffer descriptor that uses a ring structure located in the dual-port ram. figure 16-38. idma buffer descriptor ring idma bd base bd 0 bd 1 bd 2 bd n source device or data buffer 0 source device or data buffer 1 source device or data buffer 2 source device or data buffer n destination device or data buffer 0 destination device or data buffer 1 destination device or data buffer 2 destination device or data buffer n address (ibase) ? ? ?
communication processor module 16-92 mpc823e referencemanual motorola idma communication 16 processor module 16.6.3.2 idma parameter ram memory map. the mpc823e uses the idma parameters listed in the table below to configure the idma channel for autobuffer or buffer chaining mode. ? ibasethis index pointer defines the starting point in the dual-port ram for the set of idma buffer descriptors. it is an offset from the beginning of the dual-port ram. you must initialize this entry before enabling the idma channel and if you overlap the buffer descriptor tables of two enabled serial channels or idma channels, erratic behavior will occur. ibase must contain a value that is divisible by 16. table 16-21. idma parameter ram memory map address name width description idma base + 00 ibase half-word idma buffer descriptor base address index pointer idma base + 02 dcmr half-word idma channel mode register idma base + 04 sapr word source internal address pointer idma base + 08 dapr word destination internal address pointer idma base + 0c ibptr half-word buffer descriptor pointer idma_base +0e write_sp half-word idma base + 10 s_byte_c word internal source byte count idma base + 14 d_byte_c word internal destination byte count idma base + 18 s_state word internal state idma base + 1c itemp four-word temporary data storage idma base + 2c sr_mem word data storage for peripheral write idma base + 30 read_sp half-word idma base + 32 half-word difference between source and destination residue idma base + 34 half-word temporary storage address pointer idma base + 36 half-word sr_mem byte count idma base + 38 d_state word internal state note: you are only responsible for initializing the items in bold. idma base = (immr & 0xffff0000) + 0x3cc0 (idma1) or 0x3dc0 (idma2). all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register.
communication processor module motorola mpc823e reference manual 16-93 idma communication 16 processor module ? dcmrthis register controls the operation mode of the idma channel. bits 0C10reserved these bits are reserved and must be set to 0. sizeperipheral port size 00 = word length. 01 = half-word length. 10 = byte length. 11 = reserved. typesource/destination type (can be peripheral or memory) 00 = read and write from memory. 01 = read from peripheral and write to memory. 10 = read from memory and write to peripheral. 11 = reserved. scsingle cycle 0 = dual-cycle mode. 1 = single-cycle mode. the following bits are only used by the risc microcontroller: ? saprthis address pointer points to the next source data byte that idma transfers. ? daprthis address pointer points to the next destination byte that idma writes. when the buffer descriptor is first processed, the communication processor module initializes these pointers to the programmed values in the buffer descriptor. ? ibptrthis pointer points to the next buffer descriptor that the idma transfers data to when it is in idle state or points to the current buffer descriptor during transfer processing. after a reset or when the end of an idma buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the ibase register. ? write_spthis parameter must not be modified. ? s_byte_cthis parameter must not be modified. ? d_byte_cthis parameter must not be modified. dcmr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved size type sc reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x3cc2 (idma1) and 0x3dc2 (idma2)
communication processor module 16-94 mpc823e referencemanual motorola idma communication 16 processor module ? s_statethis parameter must not be modified. ? itempthis parameter must not be modified. ? sr_memthis parameter must not be modified. ? read_spthis parameter must not be modified. ? d_statethis parameter must not be modified. the source address pointer points to the next source data byte that the idma transfers. the destination address pointer points to the next destination byte that the idma writes. when the buffer descriptor is first being processed, the communication processor module initializes these pointers to the programmed values. the remaining parameters are to only be used by the microcontroller. the memory port size is transparent to the idma, regardless of the actual port size. the system interface unit emulates 32-bit port size. 16.6.3.3 idma status registers. the 8-bit, memory-mapped idma1 and 2 status registers (idsrx) are used to report events recognized by the idma controller. when an event is recognized, idma sets its corresponding bit in this register. a bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset at a time. bits 0C4reserved these bits are reserved and must be set to 0. adafter service buffer descriptor done this status bit is set after servicing a buffer descriptor that has the i bit set. doneidma transfer done this bit indicates when the idma channel terminates a transfer. it is set after servicing a buffer descriptor that has the l status bit set. obout of buffers this bit indicates that the idma channel has no valid buffer descriptors. idsr1 and idsr2 bit 0 1 2 3 4 5 6 7 field reserved ad done ob reset 0 000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x910 (idsr1), 0x918 (idsr2)
communication processor module motorola mpc823e reference manual 16-95 idma communication 16 processor module 16.6.3.4 idma mask registers. the 8-bit read/write idma1 or 2 mask registers (idmrx) have the same bit format as the idsrx. if a bit in the idmrx is 1, the corresponding interrupt in the status register is enabled. if an idmrx bit is zero, the corresponding interrupt in the status register is masked. bits 0C4reserved these bits are reserved and must be set to 0. adafter service buffer descriptor done this status bit is set after servicing a buffer descriptor that has the i bit set. doneidma transfer done this bit indicates when the idma channel terminates a transfer. it is set after servicing a buffer descriptor that has the l status bit set. obout of buffers this bit indicates that the idma channel has no valid buffer descriptors. idmr1 and idmr2 bit 0 1 2 3 4 5 6 7 field reserved ad done ob reset 0 000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x914 (idmr1), 0x91c (idmr2)
communication processor module 16-96 mpc823e referencemanual motorola idma communication 16 processor module 16.6.3.5 idma buffer descriptors. the special idma buffer descriptors present the source addresses, destination addresses, and byte counts to the risc microcontroller. the risc microcontroller reads the buffer descriptors, programs the sdma channel, and notifies the core about the completion of a buffer transfer using the idma buffer descriptors. this process is similar to that of the serial channels, except that the buffer descriptor is larger because it contains additional information. you must prepare the following bits before a transfer can occur. they are set by the risc microcontroller after the buffer has been transferred. vvalid 0 = the data buffers associated with this buffer descriptor are not currently ready for transfer. you are free to manipulate this buffer descriptor or its associated data buffer. when it is not in autobuffer mode, the risc microcontroller clears this bit after the buffer has been transferred (or after an error condition is encountered). 1 = you have prepared the data buffers for transfer. notice that only one data buffer must be prepared if the source/destination is a peripheral device. it can only be the source data buffer when the destination is a device or the destination data buffer when the source is a device. you can not write any fields of this buffer descriptor once this bit is set. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 v res wi l res cm reserved offset + 2 dfcr sfcr offset + 4 data length offset + 6 offset + 8 source data buffer pointer offset + a offset + c destination data buffer pointer offset + e note: you are only responsible for initializing the items in bold. note: the only difference between autobuffer mode and buffer-chaining mode is that the v bit is not cleared by the risc microcontroller in autobuffer mode. autobuffer mode is enabled by the cm bit.
communication processor module motorola mpc823e reference manual 16-97 idma communication 16 processor module wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the table. 1 = this is the last buffer descriptor in the table. after the associated buffer has been used, the risc microcontroller transfers data from the first buffer descriptor that ibase register points to in the table. the number of buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = once this buffer is serviced by the risc microcontroller, the ad bit in the idsrx is set and can cause an interrupt. llast 0 = this is not the last buffer to be transferred in the buffer chaining mode. the i bit can be used to generate an interrupt when this buffer is serviced. 1 = this is the last buffer to be transferred in the buffer chaining mode. when the transfer count is exhausted, an interrupt is generated, regardless of state of the i bit. cmcontinuous mode 0 = buffer chaining mode. the risc microcontroller clears the v bit after this buffer descriptor is serviced. this mode is used to transfer large amounts of data into noncontiguous buffer areas. you can initialize buffer descriptors ahead of time, if you need to. the risc microcontroller automatically reloads the idma registers from the next buffer descriptor values when the transfer is terminated. 1 = autobuffer mode (continuous mode). the risc microcontroller does not clear the v bit after this buffer descriptor is serviced. this is the only difference between the behavior of autobuffer mode and buffer chaining mode. the autobuffer mode is used to transfer multiple groups of data to/from a buffer ring and does not require reprogramming. the risc microcontroller automatically reloads the idma registers from the next buffer descriptor values when the transfer is terminated. either a single buffer descriptor or multiple buffer descriptors can be used in this mode to create an infinite loop of repetitive data moves. note: the i bit can be used to generate an interrupt in this mode.
communication processor module 16-98 mpc823e referencemanual motorola idma communication 16 processor module sfcrsource function code register the 8-bit source function code register contains the value that you would like to appear on the at pins when the associated dma channel accesses the source memory. this register controls the byte-ordering convention used in transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set this field to select the required byte ordering of the data buffer. if this field is modified on-the-fly, it takes effect at the beginning of the next frame or at the beginning of the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation). it is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode can only be used with 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. atxaddress type 1C3 this field contains the function code value used during the sdma channel memory access. at0 is always driven to 1, so that this sdma channel access is identified as a dma-type access. sfcr bit 0 1 2 3 4 5 6 7 field reserved bo at1 at2 at3 addr offset + 3
communication processor module motorola mpc823e reference manual 16-99 idma communication 16 processor module dfcrdestination function code register the 8-bit destination function code register contains the value that you would like to appear on the at pins when the associated dma channel accesses the destination memory. this register also controls the byte-ordering convention used in transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set this field to select the data buffers required byte ordering. if these bits are modified on-the-fly, it takes effect at the beginning of the next frame or at the beginning of the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation). it is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode can only be used with 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. atxaddress type 1C3 this field contains the function code value used during sdma channel memory access. at0 is driven with a 1, so that this sdma channel access is identified as a dma-type access. data length this field contains the number of bytes that idma must transfer to or from this buffer descriptor data buffer. it must be programmed to a value greater than zero. dfcr bits 0 1 2 3 4 5 6 7 field reserved bo at1 at2 at3 addr offset + 2
communication processor module 16-100 mpc823e referencemanual motorola idma communication 16 processor module source buffer pointer this field contains the address of the associated source data buffer and can reside in internal or external memory. destination buffer pointer this field contains the address of the associated destination data buffer, which resides in internal or external memory. the terminal count code at = 0xf replaces the normal sfcr and dfcr code for the last idma cycle on the peripheral side. 16.6.3.6 idma commands. there are three idma commands: ? init_idma this command causes the risc microcontroller to reinstall its idma internal state to the condition it was in after a system reset. the idma buffer descriptor pointer is reinitialized to the top of the buffer descriptor ring. ? arm_idma this command causes the idma to open the next buffer descriptor in the table. it can be used to reduce the latency of servicing the first idma request. ? stop_idma this command causes the risc microcontroller to terminate current idma transfers. the done bit is set in the idsrx and the current buffer descriptor is closed. if the peripheral device is the source, the idma internal buffer is transferred to memory before termination. at the next request, the following buffer descriptor in the chain is processed. note: in single address mode when the source is a device, the source buffer pointer field is ignored. in dual address mode when the source is a device, this field must contain the device address. note: in single address mode when the destination is a device, the destination buffer pointer field is ignored. in dual address mode when the destination is a device, this field must contain the device address.
communication processor module motorola mpc823e reference manual 16-101 idma communication 16 processor module 16.6.3.7 starting idma. once the channel has been initialized with all parameters required for a transfer operation, idma is started by setting the dreqx bit in the port c special option (pcso) register. once dreqx has been set, the channel is active and accepts operand transfer requests through the channels corresponding dreqx pin. when the first valid external request is recognized, idma arbitrates for the bus and the dreqx pin input is ignored until the dreqx bit is set in the pcso register. idma1 is higher than idma2. the software can suspend channel transfer operation at any time by clearing the dreqx bit in the pcso register. in response, any operand transfer in progress will be completed and the bus will be released. no further bus cycles are started while the dreqx bit remains cleared. during this time, the core can access idma internal registers to determine the status of a channel or to alter operation. when the dreqx bit is set again, if a transfer request is pending, idma arbitrates for the bus and continues normal operation. interrupts from idma are sent to the interrupt controller. in the interrupt handler, the unmasked bits in the idsrx must be cleared (by writing them with a 1) to negate the interrupt request to the cpm interrupt controller. 16.6.3.8 requesting idma transfers. once idma has been started, transfers to idma can be requested. these transfers are initiated by externally generated requests from an external device using the dreqx pin in conjunction with the activation of the dreqx bit of the pcso register. 16.6.3.9 level-sensitive mode. for external devices that require very high data transfer rates, level-sensitive mode allows idma to use a maximum bandwidth to service the device. in this mode, the dreqx pin input to idma is level-sensitive and sampled at rising edges of the clock to determine when a valid request is asserted by the device. the device requests service by asserting the dreqx pin and leaving it asserted as long as it needs service. each time idma issues a bus cycle to either read or write the device, it outputs the sdackx signal. the device is either the source or destination of the transfers, as determined by the type field of the dcmr. sdackx is the acknowledgment of the original burst request given on the dreqx pin, which must be negated during the sdackx active period to guarantee that no further cycles are performed. burst mode in the context of the dreqx pin actually means back-to-back dma cycles. burst in the context of the bus means burst cycle. the dma always uses bursts at the memory width. 16.6.3.10 edge-sensitive mode. for external devices that generate a pulsed signal for each operand to be transferred, edge-sensitive mode must be used. in edge-sensitive mode, idma moves one operand for each falling edge of the dreqx pin input. dreqx is sampled at each rising edge of the clock to determine when a valid request is asserted by the device. when idma detects a falling edge on the dreqx pin, a request becomes pending and remains as such until it is serviced by idma. further falling edges on the dreqx pin are ignored until the request starts being serviced, which results in one operand being transferred. each time idma issues a bus cycle to read or write the device, it outputs the sdackx signal. the device is either the source or destination of the transfers, as determined by the type field of the dcmr. thus, sdackx is the acknowledgment of the original cycle steal request given on the dreqx pin.
communication processor module 16-102 mpc823e referencemanual motorola idma communication 16 processor module 16.6.3.11 idma operand transfers. once idma successfully arbitrates for the bus, it can begin making operand transfers. the source idma bus cycle has timing identical to an internal master read bus cycle. the destination idma bus cycles timing is controlled by the memory controller and is therefore identical to any other internal access. the two-channel idma controller supports dual-address transfers and single address transfers, but only channel 1 supports single-buffer (single-address burst fly-by) transfers. the dual-address operand transfer consists of a source operand read and a destination operand write. each single-address operand transfer consists of one external bus cycle that allows a read or write cycle to occur. a single-buffer mode transfer is exactly like the single-address operand transfer, except it is an external burst transfer. 16.6.3.11.1 transfer identification. the following are ways to externally determine if idma is executing a bus cycle: ? monitor the at signals or sdma channels to determine if they have the unique function code that identifies an idma transfer. ? monitor the sdackx signal, which shows accesses to the peripheral device. sdackx activates on either the source or destination bus cycles, depending on the type field of the dcmr. 16.6.3.11.2 dual-address mode. the two idma channels can be programmed to operate in a dual-address transfer mode in which the operand is read from the source address specified by the pointer and placed in internal storage. the operand read can take several bus cycles to complete because of differences in source and destination operand sizes. once it is read, the operand is then written to the address specified in the destination address pointer. this transfer may also be several bus cycles long. you can use a variety of peripheral, memory, and operand size combinations in a dual-address mode transfer. there are two types of dual-address mode cycles: ? dual-address source readinitially, the idma controller copies the source data buffer pointer buffer descriptor into the sapr field of the parameter ram. during this type of idma cycle, the sdbp is used to drive the address bus, the sfcr is used to drive the source address type, and the dcmr is used to drive the size control. data is read from the memory or peripheral and placed in the internal storage when the bus cycle is terminated. when the complete operand has been read, the sapr is incremented by 1, 2, 4, or 16, depending on the address and size information specified by the idma channel mode register (dcmr). ? dual-address destination writeinitially, the idma controller copies the destination data buffer pointer buffer descriptor into the dapr field of the parameter ram. during this type of idma cycle, the data in the internal storage is written to the device or memory selected by the at field in the dapr, the at field in the dfcr, and the size field in the dcmr. the same options exist for operand size and alignment in this cycle as they did in the dual address source read cycle. when the complete operand is written, the dapr is incremented by 1, 2, 4, or 16 according to the dcmr and the d_byte_c is decremented by the number of bytes transferred. if it is equal to zero and the transfer is completed with no errors, the done bit in the idsrx is set. refer to section 16.6.3.2 idma parameter ram memory map for more information.
communication processor module motorola mpc823e reference manual 16-103 idma communication 16 processor module regardless of the source size, destination size, source starting address, or destination starting address, idma uses the most efficient packing algorithm possible to perform the transfer in the lowest number of bus cycles. 16.6.3.11.3 single-address mode (fly-by transfers). each idma channel can be independently programmed to provide single-address transfers. the internal storage is not used by idma, since the transfer occurs directly from a device to memory. this mode is often referred to as fly-by mode because the internal storage is not used. the external request is used to start a transfer when the single-address mode is selected. the type field in the dcmr controls whether a source read or destination write cycle occurs on the data bus. if the type field is set to 01, the external handshake signals are used with the destination data buffer pointer and a single-address destination write occurs. if the type field is set to 10, the external handshake signals are used with the source data buffer pointer and a single-address source read occurs. there are two types of single-address mode cycles: ? single-address source readduring this type of idma cycle, the device or memory selected by the address in the sapr, the atx field in the sfcr, and the size field in the dcmr provides the data and control signals on the data bus. this bus cycle operates like a normal read bus cycle. the destination device is controlled by the dreqx and sdackx signals. asserting sdackx gives you write control to the destination device. for more details about idma handshake signals, refer to section 16.6.2 idma interface signals . for specific timing parameters, visit our website. figure 16-39. single-address, peripheral write, asynchronous ta t3 t1 t3 t1 t3 clkout t1 t3 t1 t3 t1 t3 address rd / wr ts data ta sdack x t0 t2 t0 dreq x
communication processor module 16-104 mpc823e referencemanual motorola idma communication 16 processor module ? single address destination writeduring this type of idma cycle, the source device is controlled by the idma handshake signals (dreqx and sdackx ). when the source device requests service from the idma channel, idma asserts sdackx to allow the source device to drive data onto the data bus. the data is written to the device or memory selected by the at field in the dapr, the destination at field in the dfcr, and the size field in the dcmr. the data bus is driven to three-state for this write cycle. for more details about idma handshake signals, refer to section 16.6.2 idma interface signals . for specific timing parameters, visit our website. figure 16-40. single-address, peripheral write, synchronous ta t3 t1 t3 t1 t3 clkout t1 t3 t1 t3 t1 t3 address rd / wr ts data ta sdack x t0 t2 t0 dreq x
communication processor module motorola mpc823e reference manual 16-105 idma communication 16 processor module 16.6.3.11.4 single-buffer burst fly-by mode. this mode is used to transfer a data block from a peripheral to system memory. when the buffer has been completely transferred, channel operation is terminated. both progressive (non-interlaced) and interlaced destination address generation modes are supported. this mode of operation is a subset of the buffer chaining mode with reduced latency and it is restricted to fly-by transfers. it is supported only on idma channel 1. progressive address generation mode is selected by setting the eie bit in the rccr, which is described in section 16.2.5 risc configuration and control registers . as a result, the organization of its parameter ram is different from the other modes. interlaced address generation mode supports charge-coupled devices (ccds), which use an interlaced readout scheme and are often used in digital cameras. the frame buffer in memory must be progressive to decrease the amount of processing the software has to perform. the interlace mode allows you to read an interlaced ccd into a progressive buffer. for example, for a 2-field ccd, the idma reads a line, skips a line, reads a line until the first field (the odd lines) is read. then the process repeats for the second field (even lines). there are, however, 4-field ccds, in which case you would read a line and then skip three. a field is a group of scan lines (odd or even) and a frame is composed of several fields. the refresh (of the display) or readout (of the ccd) is done by field sequencefield1, then field2, etc. figure 16-41. single-address, peripheral read, synchronous ta note: the arm idma command only works with idma modes that use buffer descriptors. t3 t1 t3 t1 t3 clkout t1 t3 t1 t3 t1 t3 address rd / wr ts data ta sdack x t0 t2 t0 dreq x
communication processor module 16-106 mpc823e referencemanual motorola idma communication 16 processor module interlaced mode can be set up using the following steps: 1. initialize the idma single buffer mode parameter ram. 2. in the rccr, set the eie bit to 1 and the dr1m bit according to the requested mode. see section 16.2.5 risc configuration and control registers for more information. 3. if edge-sensitive mode is selected, program the edm15 bit of the pcint register to the requested mode (falling edge/any edge). 4. in the pcso register, set the dreq1 bit to 1. see section 16.14.9.4 port c special options register for more information. when configured to single buffer mode, the idma parameter ram is overlayed with the specific parameters in table 16-22. table 16-22. single-buffer mode parameter ram map address name width destination address generation mode progressive interlaced dma base + 00 bapr* word buffer address pointer current buffer address pointer dma base + 04 bcr* word byte count register current bytes per line dma base + 08 dcmr* word dma channel mode register dma channel mode register dma base + 0c fbar * word not assigned field base address register dma base + 10 res half-word reserved reserved dma base + 12 nfld * half-word not assigned number of fields register dma base + 14 lcr half-word not assigned lines per field count register dma base + 16 l_cnt * half-word not assigned current line count dma base + 18 bplr half-word not assigned bytes per line register dma base + 1a rbr half-word not assigned raw bytes register dma base + 1c to dma base + 3f res word reserved reserved note: you are only responsible for initializing the items in bold. * modified by the idma controller during operation and must be reinitialized before starting a new idma transaction. dma base = (immr & 0xffff0000) + 0x3cc0 (idma1). all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register.
communication processor module motorola mpc823e reference manual 16-107 idma communication 16 processor module you must initialize the parameter ram values before the channel is enabled. however, they must only be modified when there is no dma activity. ? buffer address pointerthe buffer address pointer (bapr) contains 32 address bits of the destination buffer address used by the idma. the bapr must be programmed to burst-aligned address. in progressive mode, the bapr is incremented by 16 bytes after each transfer and it is incremented by 16 for each burst. in interlaced mode the bapr is incremented by 16 for each burst while it is within a line and then it is incremented by the raw bytes register to point to the next line. ? byte count registerthe 32-bit byte count register (bcr) specifies the number of bytes to be transferred by the idma. the bcr is decremented by 16 bytes after each transfer and must be programmed as a multiple of 16. in progressive mode, the idma channel will terminate the transfer of a block of data if this register reaches zero during operation. ? dma channel mode registerthe 32-bit dma channel mode register (dcmr) controls the channel operation mode. mb1must be 1 for dma operation, this bit must be set to 1. bits 1C2, 9 11, 16 31reserved these bits are reserved and must be set to 0. dcmr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field mb1 reserved bo at str reserved edge itlc bpr reset 000 000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x3cc8 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x3cca
communication processor module 16-108 mpc823e referencemanual motorola idma communication 16 processor module bobyte ordering you must set this field to select the required byte ordering of the data buffer. if this field is modified on-the-fly, it will take effect at the beginning of the next buffer descriptor. 00 = dec/intel convention is used for byte ordering (swapped operation). it is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed as compared to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least significant byte of the buffer double-word contains data to be transmitted earlier than the most significant byte of the same buffer double word. 1x = motorola byte ordering (normal operation). it is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most significant byte of the buffer word contains data to be transmitted earlier than the least significant byte of the same buffer word. ataddress type 1C3 this field contains the function code value used during this sdma channel memory access. at0 will be driven with a one to identify this sdma channel access as a dma-type access. strstart this bit enables the idma channel. you must set it after you program bapr and bcr. it is cleared by the channel upon completion of the transfer and the byte count in bcr is exhausted. 0 = dma channel is disabled. 1 = dma channel is enabled. edgeedge-sensitive dreq1 this bit controls whether the communication processor module will be interlocked to the external sdack1 signal before exiting the idma routine. this bit must be cleared if level-sensitive dreq1 is used. if the dr1m bit of the rccr is set to 1, this bit must be set to 0. 0 = level-sensitive mode. the communication processor module will wait until sdack1 is seen externally before executing the idma routine. 1 = edge-sensitive mode. the communication processor module may exit the idma routine before sdack1 is seen externally. itlcinterlaced mode this bit controls the destination address bit generation. 0 = progressive (non-interlaced) address generation. 1 = interlaced address generation.
communication processor module motorola mpc823e reference manual 16-109 idma communication 16 processor module bprbursts per request this field determines how many bursts will be transferred per request. 00 = one burst per request. 01 = two burst per request. 10 = reserved. 11 = four bursts per request. ? field base address registerthis 32-bit register specifies the field destination base address. fbar is incremented by the number of bytes per line after each field. it is used in interlaced mode only. ? number of fields per frame registerthis 16-bit register specifies the number of field per frame. it is used in interlaced mode only. nfld is decremented after each field. ? lines per field count register this 16-bit register specifies the number of lines per field. it is used in interlaced mode only. ? lines per field registerthis 16-bit register specifies the number of remaining lines to the end of the field. it is used in interlaced mode only, and must be initialized to the value of the lcr. l_cnt is decremented after each line. ? bytes per line registerthis 16-bit register specifies the number of bytes per line. the value must be divisible by 16 for one burst per request, by 32 for two bursts per request, or by 64 for four bursts per request. it is used in interlaced mode only. ? raw bytes registerthis 16-bit register specifies the number of bytes to skip from the end of one line to the beginning of the next line. it is used in interlaced mode only. 16.6.3.12 idma status registers. the 8-bit idma 1 and 2 status registers (idsrx) are used to report events recognized by the idma controller. when an event is recognized, the idma controller sets the corresponding bit in the idsrx. these memory-mapped registers can be read at any time. a bit is reset by writing a one (writing a zero has no effect). bits 0C5 and 7reserved these bits are reserved and must be set to 0. doneidma transfer done this bit indicates that the idma channel terminated a transfer. it will be set after the byte count in the bcr of the single-buffer mode parameter ram has reached zero. idsr1 and idsr2 bit 0 1 2 3 4 5 6 7 field reserved done reserved reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x910 (idsr1), 0x918 (idsr2)
communication processor module 16-110 mpc823e referencemanual motorola idma communication 16 processor module 16.6.3.13 idma mask registers. the 8-bit read/write idma1 and 2 mask registers (idmrx) have the same bit format as the idmax status registers. if a bit in the idmrx is a one, the corresponding interrupt in the idsrx will be enabled. if an idmrx bit is zero, the corresponding interrupt in the idsrx will be masked. bits 0C5 and 7reserved these bits are reserved and must be set to 0. doneidma transfer done this bit indicates when the idma channel terminates a transfer. it is set after servicing a buffer descriptor that has the l bit set. 16.6.3.14 single-buffer timing. a typical single-address burst timing when the idma is in single-buffer mode is illustrated in figure 16-42. the peripheral device asserts the dreq1 pin and waits for sdack1 to initiate a burst transfer to or from memory. the peripheral must negate the dreq1 pin before the last beat of the transfer. otherwise, idma will assume that another dma request is pending and will start another burst cycle right after the completion of the current transfer. idmr1 and idmr2 bit 0 1 2 3 4 5 6 7 field reserved done reserved reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x914 (idmr1), 0x91c (idmr2)
communication processor module motorola mpc823e reference manual 16-111 idma communication 16 processor module 16.6.3.15 download sequence. the microcode package is provided in s-records format. it occupies the first 512 bytes of the dual-port ram (on the ads address 0x2202000 to address 0x22021ff) and 256 bytes at the end of the first 4k (on the ads address 0x2202f00 to address 0x2202fff).use the following mpc8bug debugger commands to load the package: rms cpm rccr 0 load interlaced_dma.srx rms cpm rccr 9 figure 16-42. idma single-address burst read or write clkout gclk1 a[0:31] ts rd/ wr d[0:31] ta cs1 bs [0:3] row column 1 column 2 column 3 column 4 ( ras ) ( cas [0:3]) sdack 1 dreq 1 bdip
communication processor module 16-112 mpc823e reference manual motorola serial i/f communication 16 processor module 16.6.3.16 bus exceptions. when idma has the bus and is performing operand transfers, bus exceptions can occur. when a synchronous bus structure like those supported by the mpc823e is used, you can make provisions that allow a bus master to detect and respond to errors during a bus cycle. idma recognizes the same bus exceptions that the core recognizes at reset or when a transfer error occurs. ? reseton an external reset, idma immediately aborts channel operation, returns to the idle state, and clears the idsrx. if a bus cycle is in progress when reset is detected, the cycle is terminated, the control and address/data pins are three-stated, and bus ownership is released. ? transfer errorwhen a fatal error occurs during a bus cycle, a bus error exception is used to abort the cycle and systematically terminate that channel operation. the idma terminates the current bus cycle, signals an error in the sdsr, and signals an interrupt if the corresponding bit in the sdmr is set. idma waits for the risc microcontroller to reset before starting any new bus cycles. it must be noted that any data previously read from the source into the internal storage is lost. 16.7 the serial interface with time-slot assigner the serial interface connects the physical layer serial lines to the serial communication controllers (sccs) and two serial management controllers (smcs). in its simplest configuration, the serial interface allows these controllers to be connected to their own set of individual pins. the serial communication controller or serial management controller that connects to the external world in this way connects to a nonmultiplexed serial interface (nmsi). in an nmsi configuration, the serial interface provides a flexible clocking assignment for the serial communication controller or serial management controller from a bank of external clock pins and/or internal baud rate generators. however, the main feature of the serial interface is its time-slot assigner (tsa), which allows any combination of the serial communication or management controllers to multiplex their data together on one or two time-division multiplexed (tdma and tdmb) channels. common examples of tdms are the t1 lines in the u.s. or japan and the cept lines in europe. even if the time-slot assigner is not used in its intended capacity, it can still be used to generate complex waveforms on eight output pins (l1st[1:8]). for example, these pins can be programmed by the time-slot assigner to implement stepper motor control or variable duty cycle and period control on these pins. any programmed configuration can be changed on-the-fly. the serial interface block diagram is illustrated in figure 16-43. note: any device that is the source or destination of the operand under idma handshake control for single address transfers may need to monitor tea to detect a bus exception for the current bus cycle. tea terminates the cycle immediately and negates sdackx , which is used to control the transfer to or from the device.
communication processor module motorola mpc823e reference manual 16-113 serial i/f communication 16 processor module figure 16-43. serial interface block diagram time-slot assigner r clocks t clocks r clocks t clocks r sync t sync tdma/smc2/tdmb pins strobe pins u-bus route ram tx / rx ram control mode register tdma and tdmb tx/rx tx/rx command register status register clock route mux smc1 pins to smc1 nonmultiplexed serial interface (nmsi) mux scc3 pins to scc3 mux to smc2 usb usb pins usb clocks mux scc2 pins to scc2
communication processor module 16-114 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.1 features the top-level features of the serial interface are the time-slot assigner and nmsi. the time-slot assigner has the following main features: ? ability to connect to two independent tdma channel s ? independent, programmable transmit and receive routing paths ? independent transmit and receive frame syncs ? independent transmit and receive clocks ? selection of rising/falling clock edges for the frame sync and data bits ? supports 1 and 2 input clocks (1 or 2 clocks per data bit) ? selectable delay (0C3 bits) between frame sync and frame start ? eight programmable strobe outputs pins (lst[1:4] are used for receive (rx) ram while lst[5:8] are used for transmit (tx) ram) ? 1- or 8-bit resolution in routing, masking, and strobe selection ? supports frames up to 8,192 bits long ? internal routing and strobe selection can be dynamically programmed ? supports automatic echo and loopback mode for each tdm the nmsi has the following main features: ? serial communication controller 2 (scc2) and each serial management controller (smc) can be independently programmed to work with its own set of pins in a nonmultiplexed manner ? each serial communication controller can have its own set of modem control pins ? each serial management controller can have its own set of pins ? the serial communication controllers, universal serial bus, and each serial management controllers can derive clocks externally from a bank of four clock pins or a bank of four baud rate generators 16.7.2 configuring the time-slot assigner the time-slot assigner implements both internal route selection and time-division multiplexing for multiplexed serial channels. it supports the serial bus rate and format for most standard tdm buses, including the t1 and cept highways, pulse code modulation (pcm) highway, and isdn buses in both basic and primary rates. the two popular isdn basic rate busesinterchip digital link and general circuit interface (also known as iom-2) are supported.
communication processor module motorola mpc823e reference manual 16-115 serial i/f communication 16 processor module time-slot assigner programming is completely independent of the protocol used by the serial communication controller or serial management controller. for instance, the fact that serial communication controller can be programmed for the hdlc protocol has no impact on time-slot assigner programming. the purpose of the time-slot assigner is to route the data from the specified pins to the serial communication controller or serial management controller at the correct time, but it is the responsibility of the scc or smc to handle the received data. in its simplest mode, the time-slot assigner identifies the frame using one sync pulse and one clock signal that you provide. this can be enhanced to allow independent routing of the receive and transmit data on the tdma channel. additionally, the definition of a time-slot need not be limited to 8 bits or even to a single contiguous position within the frame. you can provide separate receive and transmit syncs as well as clocks. these various configurations are illustrated in figure 16-44. the time-slot assigner can support four, independent, half-duplex tdm sources, two in reception and two in transmission, using four sync inputs and four input clocks. in addition to channel programming, the time-slot assigner supports up to eight strobe outputs that may be asserted on a bit or byte basis. these strobes are completely independent from the channel routing used by sccs and the smcs. they are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state i/ o buffers in a multi-transmitter architecture. most time-slot assigner programming is accomplished in two 64 16-bit serial interface rams that are directly accessible by the host cpu in the internal register section of the mpc823e and are not associated with the dual-port ram. one serial interface ram is always used to program the transmit routing and the other is used to program the receive routing. with the serial interface rams, you can define the number of bits or bytes to be routed to the serial communication controller or serial management controller and decide when the external strobes are to be asserted and negated. the size of the serial interface ram that is available for time-slot programming depends on the configuration of the rdm field in the sigmr. if on-the-fly changes are allowed, the serial interface ram entries are reduced by one-half. however, the serial interface ram size is sufficient to allow extensive time-slot programming flexibility. the maximum frame length that can be supported in any configuration is 8,192 bits. the serial interface supports two testing modesecho and loopback. the echo mode provides a return signal from the physical interface by retransmitting the signal it has received. the physical interface echo mode differs from the individual scc echo mode in that it can operate on the entire tdm signal, rather than just on a particular scc channel. the loopback mode causes the physical interface to receive the same signal it is transmitting. the serial interface loopback mode conducts a more thorough check than the individual scc loopback does. it also checks the serial interface and the internal channel routes. the maximum external serial clock that may be an input to the time-slot assigner is gclk2 2.5. if a serial communication controller or serial management controller is operating with the nmsi, then the serial clock rate may be slightly faster at a value not to exceed gclk2 2.
communication processor module 16-116 mpc823e reference manual motorola serial i/f communication 16 processor module figure 16-44. various configurations with the tdm channel mpc82x slot 3 slot n tdm rx scc2 smc1 slot 3 slot n tdm tx scc2 smc1 simplest tdm example tsa tdm mpc82x slot 3 slot n tdm rx scc2 smc1 slot 1 slot 2 tdm tx scc2 smc1 more complex tdm example?nique routing tsa tdm mpc82x tdm rx scc2 smc1 tdm tx scc2 smc1 note: the two shaded areas of scc2 rx are received as one high-speed datastream by the scc2 and stored together in the same data buffers. 1 tdm sync 1 tdm clock tsa tdm scc2 scc2 mpc82x tdm rx scc2 smc1 tdm tx scc2 smc1 most complex tdm example?otally independent rx and tx tdm tx sync tdm tx clock tsa tdm scc2 tdm rx sync tdm rx clock 1 tdm clock 1 tdm sync 1 tdm sync 1 tdm clock even more complex tdm example?ultiple time-slots per channel with varying sizes of time-slots
communication processor module motorola mpc823e reference manual 16-117 serial i/f communication 16 processor module 16.7.3 enabling connections to the time-slot assigner each serial communication controller and serial management controller can be independently enabled to connect to the time-slot assigner. a serial communication controller is connected to the time-slot assigner by setting the scx bit in the sicr. the serial management controllers are connected to the time-slot assigner by setting the smcx field of the simode register. additionally, the tdma interface must be enabled before it can be connected to the time-slot assigner by setting the enx field in the sigmr. once there is a connection, the exact routing decisions are made in the serial interface ram. refer to figure 16-45 for more information. 16.7.4 serial interface ram operation the serial interface has two 64 32-bit static rams that are used to control the routing of the tdma channel to the serial communication and management controllers. these rams are uninitialized after power-on and, to avoid unwanted results, the host cpu must program them before enabling the multiplexed channels. the rams consist of 16-bit entries that define the routing control and each entry can control anywhere from 1 to 16 bits or 1 to 16 bytes. in addition to the routing, up to four strobe pins (all active high) can be asserted, depending on how the ram is programmed. you can configure the serial interface ram in the following formats to support the tdm channels: ? one multiplexed channel with static frames ? one multiplexed channel with dynamic frames ? two multiplexed channels with static frames ? two multiplexed channels with dynamic frames figure 16-45. enabling connections through the serial interface tdm pins time-slot assigner control logic en ena=1 to enable scc2 scc2 pins sc2=1 smc1 smc1 pins smc1=1 smc2 smc2=1 sc2=0 smc1=0 smc2=0 multiplexed interface nonmultiplexed interface serial interface ram scc3 scc3 pins sc3=0 sc3=1
communication processor module 16-118 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.4.1 one multiplexed channel with static frames. in this configuration, there are 64 entries in the serial interface ram for transmit data and strobe routing and 64 entries for receive data and strobe routing. this configuration must be chosen when the tdm routing does not need to be dynamically changed. figure 16-46. configuring the tdm with static frames 64 entries rx route framing signa l l1rclk x l1rsynca x serial interface ram entry 0 64 entries tx route 63 127 64 l1tclka x l1tsynca x ( 32 bits wide) one channel with independent rx and tx route rdm = 00
communication processor module motorola mpc823e reference manual 16-119 serial i/f communication 16 processor module 16.7.4.2 one multiplexed channel with dynamic frames. in this configuration, there is one multiplexed channel and it has 32 entries for transmit data and strobe routing and 32 entries for receive data and strobe routing. in each ram, one of the partitions is the current-route ram and the other is a shadow ram that allows you to change the serial routing. after programming the shadow ram, set the csrrx bit of the associated channel in the simcr to receive and the csrtx bit to transmit. when the next frame sync arrives, the serial interface automatically exchanges the current-route ram for the shadow ram. refer to section 16.7.4.6 serial interface ram dynamic changes for more details on how to dynamically change the channel route. you must only use this configuration when the routing on the time-division multiplex needs to be dynamically changed. figure 16-47. configuring the tdm with dynamic frames 32 entries rx route framing signals l1rclk x l1rsync x serial interface ram entry 0 32 entries tx route 31 95 64 l1tclk x l1tsync x 96 32 63 127 ( 32 bits wide) one channel with shadow ram for dynamic route change rdm = 01
communication processor module 16-120 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.4.3 two multiplexed channels with static frames. in this configuration, there are 32 entries in the serial interface ram for transmit data and strobe routing and 32 entries for receive data and strobe routing. this configuration is recommended when you use two tdms and thetdm routing does not need to be dynamically changed. figure 16-48. configuring two tdms with static frames 32 entries rxa route framing signals l1rclka l1rsynca serial interface ram entries 32 entries txa route 63 191 128 l1tclka l1tsynca (32 bits wide) two channels with independent rx and tx route rdm =10 32 entries rxb route framing signals l1rclkb l1rsyncb 64 32 entries txb route 127 255 192 l1tclkb l1tsyncb 0
communication processor module motorola mpc823e reference manual 16-121 serial i/f communication 16 processor module 16.7.4.4 two multiplexed channels with dynamic frames. in this configuration, there are two multiplexed channels. each channel has 16 entries for transmit data and strobe routing and 16 entries for receive data and strobe routing. in each ram, one of the partitions is the current-route ram and the other is a shadow ram that allows you to change the serial routing. after programming the shadow ram, set the csrrx bit of the associated channel in the serial interface command register to receive and the csrtx bit to transmit. when the next frame sync arrives, the serial interface automatically exchanges the current-route ram for the shadow ram. refer to section 16.7.4.6 serial interface ram dynamic changes for more details on how to dynamically change the channel route. this configuration when you are using two tdms and the routing needs to be dynamically changed. figure 16-49. configuring two tdms with dynamic frames 16 entries rxa route framing signals l1rclka l1rsynca serial interface ram entry 16 entries txa route 31 159 128 l1tclka l1tsynca 160 32 63 191 (32 bits wide) two channels with shadow ram for dynamic route change rdm = 11 16 entries rxb route framing signals l1rclk b l1rsync b 64 16 entries txb route 95 223 192 l1tclk b l1tsync b 224 96 127 255 0
communication processor module 16-122 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.4.5 programming the serial interface ram entries. the programming of each word within the ram determines the routing of the serial bits and assertion of strobe outputs. the ram programming codes are shown in the following table. looploopback 0 = normal mode. 1 = loopback mode for this time-slot. swtrswitch transmit and receive this bit is only valid in the receive route ram and is ignored in the transmit route ram. this bit affects the operation of both the l1rxdx and l1txdx pins. the swtr bit is only set in special situations in which you prefer to receive data from a transmit pin and transmit data on a receive pin. for instance, consider the situation in which devices a and b are connected to the same time-division multiplex, each with different time-slots. normally, there is no opportunity for stations a and b to communicate with each other directly over the time-division multiplex since they both receive the same tdm receive data and transmit on the same tdm transmit signal. serial interface ram entries bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field loop swtr ssel1 ssel2 ssel3 ssel4 res csel cnt byt lst reset 0000000 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xc00 to 0xdff bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved reset 11111111 11 1 111 11 r/w r/w addr (immr & 0xffff0000) + 0xc00 to 0xdff figure 16-50. using the swtr bit rx rx tx tx station a tdm transmit data tdm receive data station b
communication processor module motorola mpc823e reference manual 16-123 serial i/f communication 16 processor module the swtr option gives station b the opportunity to listen to transmissions from station a and transmit data to station a. to do this, station b would set the swtr bit in its receive route ram. for this entry, receive data is taken from the l1txdx pin and data is transmitted on the l1rxdx pin. if you only want to listen to station a transmissions and not transmit data on l1rxdx, then you must clear the csel field in the corresponding transmit route ram entry to prevent transmission on the l1rxdx pin. it is also possible for station b to transmit data to station a by setting the swtr bit of the entry in its receive route ram. data is transmitted on the l1rxdx pin rather than the l1txdx pin, according to the transmit route ram. this configuration could, however, cause collisions with other data on the l1rxdx pin unless care is taken to choose an available (quiet) time-slot. if you only want to transmit on l1rxdx and not receive data on l1txdx, then you must clear the csel field in the receive route ram to prevent reception of data on l1txdx. 0 = normal operation of the l1txdx and l1rxdx pins. 1 = data is transmitted on the l1rxdx pin and is received from the l1txdx pin for the duration of this entry. ssel1Cssel4strobe select 1C4 the four strobesl1st1, l1st2, l1st3, and l1st4can be assigned to the receive ram and asserted or negated with l1rclkx. l1st5, l1st6, l1st7, and l1st8 can be assigned to the transmit ram and asserted or negated with l1tclkx. each bit corresponds to the value the strobe must have during this bit/byte group. multiple strobes can be asserted simultaneously, if preferred. if a strobe is configured to be asserted in two consecutive serial interface ram entries, then it remains continuously asserted while the serial interface ram entries are being processed. if a strobe is asserted on the last entry in the table, the strobe is negated after the last entry finishes processing. bit 6reserved this bit is reserved and must be set to 0. note: if the transmit and receive sections of the tdm do not use a single clock source, the swtr feature can cause erratic results to occur. note: each strobe is changed with the corresponding ram clock and is only output if the corresponding parallel i/o is configured as a dedicated pin.
communication processor module 16-124 mpc823e reference manual motorola serial i/f communication 16 processor module cselchannel select 000 = the bit/byte group is not supported by the mpc823e. the transmit data pin is three-stated and the receive data pin is ignored. 001 = reserved. 010 = the bit/byte group is routed to scc2. 011 = the bit/byte group is routed to scc3. 100 = reserved. 101 = the bit/byte group is routed to smc1. 110 = the bit/byte group is routed to smc2. 111 = the bit/byte group is not supported by the mpc823e. this code is also used in the scit mode as the d channel grant. cntcount this value indicates the number of bits/bytes (according to the byt bit) that the routing and strobe select of this entry controls. if cnt = 0000, then 1 bit/byte is chosen and if cnt = 1111 16 bits/bytes are selected. bytbyte resolution 0 = bit resolution. the value of cnt indicates the number of bits in this group. 1 = byte resolution. the value of cnt indicates the number of bytes in this group. lstlast entry in the ram whenever the serial interface ram is used, this bit must be set in one of the transmit or receive entries of each group. even if all entries of a group are used, this bit must still be set in the last entry. 0 = this is not the last entry in this section of the route ram. 1 = this is the last entry in this ram. after this entry, the serial interface waits for the sync signal to start the next frame. note: if a second sync signal is received before the end of a frame (as defined by the last serial interface ram entry), an error occurs. the serial interface will terminate ram processing and cease transmitting or receiving data until a third sync signal is received.
communication processor module motorola mpc823e reference manual 16-125 serial i/f communication 16 processor module 16.7.4.6 serial interface ram dynamic changes. the serial interface ram has two operating modes: ? a time-division mulitplex channel with a static routing definition. the serial interface ram is divided into two partstransmit (tx) and receive (rx). ? a time-division mulitplex channel that allows dynamic changes. the serial interface ram is divided into four partstwo transmits (tx) and two receives (rx). ? two time-division mulitplex channels with a static routing definition. the serial interface ram is divided into four partstwo transmits (tx) and two receives (rx). ? two time-division mulitplex channels that allows dynamic changes. the serial interface ram is divided into eight partsfour transmits (tx) and four receives (rx). dynamic changes allow the routing definition of a tdm to be modified while the serial communication controllers and serial management controllers are connected to it. with fixed routing, a change has three requirements that must be met before the new routing takes effect: ? the serial communication controllers and serial management controllers connected to the time-slot assigner must be disabled. ? the serial interface routing must be modified. ? the serial communication controllers and serial management controllers connected to the time-slot assigner must be reenabled. dynamic changes divide portions of the serial interface ram into current-route and shadow ram. once the current-route ram is programmed, the time-slot assigner and serial interface channels are enabled and time-slot assigner operation begins. when you need to make a change in routing, you must program the shadow ram with the new route and set the csrrx bit in the serial interface command register to receive and the csrtx bit to transmit. as a result, the serial interface exchanges the shadow ram and the current-route ram as soon as the corresponding sync arrives and resets the appropriate csrxx bit to signify that the operation has completed. at this time, you can change the routing again. notice that the original current-route ram is now the shadow ram and vice versa. figure 16-51 illustrates an example of the shadow ram exchange process. if a tdm with dynamic changes is programmed, the initial current-route ram addresses in the serial interface ram are as follows: ? 0C31 rxa route ? 64C95 txa route the shadow rams are at addresses: ? 32C63 rxa route ? 96C127 txa route
communication processor module 16-126 mpc823e reference manual motorola serial i/f communication 16 processor module if two tdms with dynamic changes are programmed, the initial current-route ram addresses in the serial interface ram are as follows: ? 0C31 rxa route ? 64C95 rxb route ? 128C159 txa route ? 192C223 txb route the shadow rams are at addresses: ? 32C63 rxa route ? 96C127 rxb route ? 160C191 txa route ? 224C255 txb route you can read any ram at any time, but for proper serial interface operation you must not try to write the current-route ram. you can, however, read the serial interface status register (sistr) to find out which part of the ram is the current-route ram. besides knowing which ram is the current-route ram, you might need to know which entry the time-slot assigner is currently using within the current-route ram. this information is provided in the sirp register, which is described in detail in section 16.7.5.6 serial interface ram pointer register . you can also externally connect one of the eight strobes to an interrupt pin to generate an interrupt on a particular serial interface ram entry starting or ending execution by the time-slot assigner.
communication processor module motorola mpc823e reference manual 16-127 serial i/f communication 16 processor module figure 16-51. serial interface ram dynamic changes 16 rxa route the tsa uses the first part of framing signals: l1rclka l1rsynca 1) initial state the ram, and the shadow is 16 rxa shadow 0313263 csrra=0 program the 1) programming shadow ram for the new the serial enterface exchange the shadow and the rx and tx route and sets the second part of the ram. csr x n = 0 current-route rams 64 95 96 127 ram address: csrta=0 csrra=1 csrta=1 csrra=0 csrta=0 16 txa route framing signals: l1tclka l1tsynca 16 txa shadow ram address: csr x n. 16 rxa route framing signals: l1rclka l1rsynca 16 rxa shadow 0313263 64 95 96 127 ram address: 16 txa route framing signals: l1tclka l1tsynca 16 txa shadow ram address: and resets the csr x n. 16 rxa route framing signals: l1rclka l1rsynca 16 rxa shadow 0313263 64 95 96 127 ram address: 16 txa route framing signals: l1tclka l1tsynca 16 txa shadow ram address: exchanges between
communication processor module 16-128 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.5 serial interface programming model 16.7.5.1 serial interface global mode register. the 8-bit, memory-mapped, read/write serial interface global mode register (sigmr) defines the ram division modes. bits 0C3reserved these bits are reserved and must be set to 0. enbenable channel b 0 = channel b is disabled. the serial interface rams and tdm routing are in a state of reset, but all other serial interface functions still operate. 1 = the serial interface is enabled. enaenable channel a 0 = channel a is disabled. the serial interface rams and tdm routing are in a state of reset, but all other serial interface functions still operate. 1 = the serial interface is enabled. rdmram division mode this field defines the ram division mode and the number of multiplexed channels supported in the serial interface. 00 = the serial interface supports one tdm channel with 64 entries for receive routing and another 64 for transmit routing. 01 = the serial interface supports one tdm channel with 32 entries for receive routing and another 32 for transmit routing. there are an additional 32 shadow entries for the receive routing and 32 more for transmit routing that can be used to dynamically change the routing. 10 = the serial interface supports two tdm channels with 32 entries for receive routing and another 32 for transmit routing for each of the tdms. 11 = the serial interface supports two tdm channels with 16 entries for receive routing and another 16 for transmit routing for each channel. there are an additional 16 shadow entries for the receive routing and 16 more for transmit routing that can be used to dynamically change the channel routing. sigmr bit 0 1 2 3 4 5 6 7 field reserved enb ena rdm reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xae4
communication processor module motorola mpc823e reference manual 16-129 serial i/f communication 16 processor module 16.7.5.2 serial interface mode register. the 32-bit, memory-mapped, read/write serial interface mode register (simode) defines the serial interface operation modes and with serial interface ram allows you to support any or all of the isdn channels independently when in idl or gci mode. smc2smc2 connection 0 = nmsi mode. the clock source is determined by the smc2cs field and the data comes from a dedicated smtxd2 and smrxd2 pin in nmsi mode. 1 = smc2 is connected to the multiplexed serial interface (tdm channel). smc2cssmc2 clock source (nmsi mode) smc2 can take its clocks from one of the baud rate generators or one of four pins from the bank of clocks. however, the smc2 transmit and receive clocks must be the same when they are connected to nmsi mode. 000 = smc2 transmit and receive clocks are brg1. 001 = smc2 transmit and receive clocks are brg2. 010 = smc2 transmit and receive clocks are brg3. 011 = smc2 transmit and receive clocks are brg4. 100 = smc2 transmit and receive clocks are clk1. 101 = smc2 transmit and receive clocks are clk2. 110 = smc2 transmit and receive clocks are clk3. 111 = smc2 transmit and receive clocks are clk4. smc1smc1 connection 0 = nmsi mode. the clock source is determined by the smc1cs field and the data comes from a dedicated pin smtxd1 and smrxd1 in nmsi mode. 1 = smc1 is connected to the multiplexed serial interface (tdm channel). simode bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field smc2 smc2cs sdmb rfsdb dscb crtb stzb ceb feb gmb tfsdb reset 0 0 0 0 000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xae0 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field smc1 smc1cs sdma rfsda dsca crta stza cea fea gma tfsda reset 0 0 0 0 000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xae2
communication processor module 16-130 mpc823e reference manual motorola serial i/f communication 16 processor module smc1cssmc1 clock source (nmsi mode) smc1 can take its clocks from one of the baud rate generators or one of four pins from the bank of clocks. the smc1 transmit and receive clocks must be the same when it is connected to the nmsi. 000 = smc1 transmit and receive clocks are brg1. 001 = smc1 transmit and receive clocks are brg2. 010 = smc1 transmit and receive clocks are brg3. 011 = smc1 transmit and receive clocks are brg4. 100 = smc1 transmit and receive clocks are clk1. 101 = smc1 transmit and receive clocks are clk2. 110 = smc1 transmit and receive clocks are clk3. 111 = smc1 transmit and receive clocks are clk4. sdmxserial interface diagnostic mode for tdmx 00 = normal operation. 01 = automatic echo. in this mode, the channel transmitter automatically retransmits the data received from the tdm on a bit-by-bit basis. the receive section operates normally, but the transmit section can only retransmit received data. in this mode, the l1grx signal is ignored. 10 = internal loopback. in this mode, the tdm transmitter output is internally connected to the tdm receiver input (l1txdx is connected to l1rxdx). the receiver and transmitter operate normally. the data appears on the l1txdx pin. in this mode the l1rqa signal is asserted normally. the l1gra signal is ignored. 11 = loopback control. in this mode, the tdm transmitter output is internally connected to the tdm receiver input (l1txdx is connected to l1rxdx). the transmitter output (l1txdx) and the l1rqa pin is inactive. this mode is used to accomplish loopback testing of the entire tdm without affecting the external serial lines. rfsdxreceive frame sync delay for tdmx this field determines the number of clock delays between the receive sync and the first bit of the receive frame. even if the crtx bit is set, these bits do not control the delay for the transmit frame. 00 = no bit delay. the first bit of the frame is transmitted/received on the same clock as the sync. use for gci. 01 = 1-bit delay. use for idl. 10 = 2-bit delay. 11 = 3-bit delay. see the examples in figure 16-52 and figure 16-53 to find out how to use these bits. note: in modes 01,10, and 11, the receive and transmit clocks must be identical.
communication processor module motorola mpc823e reference manual 16-131 serial i/f communication 16 processor module dscxdouble speed clock for tdmx this bit controls how some time-division multiplex channels, such as gci, define the input clock to be two times faster than the data rate. 0 = the channel clock (l1rclkx and/or l1tclkx) is equal to the data clock. use for idl and most tdm formats. 1 = the channel clock rate is twice the data rate. use for gci. crtxcommon receive and transmit pins for tdmx this bit is useful when the transmit and receive sections of a given tdm use the same clock and sync signals. in this mode, the l1tclkx and l1tsyncx pins can be used as general-purpose i/o pins. 0 = separate pins. the receive section of this tdm uses l1rclkx and l1rsyncx pins for framing and the transmit section uses l1tclkx and l1tsyncx for framing. 1 = common pins. the receive and transmit sections of this tdm use l1rclkx as clock pin of the channel and l1rsyncx as the receive and transmit sync pin. use for idl and gci. stzxset l1txda to zero for tdmx 0 = normal operation. 1 = l1txdx is set to zero until serial clocks are available, which is useful for gci activation. cexclock edge for tdmx 0 = data is transmitted on the rising edge of the clock and received on the falling edge (use for idl and gci). 1 = data is transmitted on the falling edge of the clock and received on the rising edge. fexframe sync edge for tdmx this bit indicates when the l1rsyncx and l1tsyncx pulses are sampled with the falling or rising edge of the channel clock. 0 = falling edge. use for idl and gci. 1 = rising edge. gmxgrant mode for tdmx 0 = gci/scit mode. the gci/scit d channel grant mechanism for transmission is internally supported. the grant is one bit from the receive channel. this bit is marked by programming the channel select bits of the serial interface ram with 111 to assert an internal strobe on it. see section 16.7.7.2.2 scit mode . 1 = idl mode. a grant mechanism is supported if the corresponding grx bit in the serial interface clock route register is set. the grant is a sample of the l1gra pin while l1tsyncx is asserted. this grant mechanism implies the idl access controls for transmission on the d channel. refer to section 16.7.6.2 programming the idl interface for more information.
communication processor module 16-132 mpc823e reference manual motorola serial i/f communication 16 processor module tfsdxtransmit frame sync delay for tdmx this field determines the number of clock delays between the transmit sync and the first bit of the transmit frame. 00 = no bit delay. the first bit of the frame is transmitted/received on the same clock as the sync. 01 = 1-bit delay. 10 = 2-bit delay. 11 = 3-bit delay. figure 16-52. example of one clock delay from sync to data (rfsdx = 01) figure 16-53. example of no delay from sync to data (rfsdx = 00) l1clk x l1sync x data (fe=1) (ce=0) bit 0 one clock delay from sync latch to first bit of frame end of frame bit 0 bit 1 bit 2 bit 3 bit 4 l1clk x l1sync x data bit 0 bit 1 bit 2 bit 3 bit 0 bit 1 bit 2 bit 4 no delay from sync latch to first bit of frame (fe=1) (ce=0)
communication processor module motorola mpc823e reference manual 16-133 serial i/f communication 16 processor module figure 16-54. example of clock edge (ce) effect when dscx = 0 figure 16-55. example of clock edge (ce) effect when dscx = 1 ce=0 l1 x clk l1 x sync (fe=0) l1txd x (bit 0) l1st x (on bit 0) l1 x sync (fe=1) rx sampled here l1st x is driven from clock low in both the fe x settings t fsd x =1 ce=1 l1 x clk l1 x sync (fe x =0) l1txd x (bit 0) l1st x (on bit 0) l1 x sync (fe x =1) rx sampled here l1st x driven from clock high for both fe x settings
communication processor module 16-134 mpc823e reference manual motorola serial i/f communication 16 processor module figure 16-56. example of frame transmission reception when rfsdx or tfsdx = 0 and cd = 1 t fsd x =0 ce x =1 l1 x clk l1 x sync (fe x =0) l1txd x (bit 0) l1st x (on bit 0) rx sampled here l1 x sync (fe x =0) l1txd x (bit 0) l1st x (on bit 0) l1 x sync (fe x =1) l1txd x (bit 0) l1st x (on bit 0) rx sampled here l1 x sync (fe x =1) l1txd x (bit 0) l1st x (on bit 0) the l1st x is driven from sync. both data bit 0 and l1st x are driven from sync l1st x and data bit 0 data is driven from clock low. l1st x is driven from clock high is driven from clock low
communication processor module motorola mpc823e reference manual 16-135 serial i/f communication 16 processor module figure 16-57. example of cex = 0 and fex interaction, xfsd = 0 ce x =0 l1 x clk l1 x sync (fe x =1) l1txd x (bit 0) l1st x (on bit 0) t fsd x =0 l1 x sync (fe x =1) l1txd x (bit 0) l1st x (on bit 0) rx sampled here l1 x sync (fe x =0) l1txd x (bit 0) l1st x (on bit 0) l1 x sync (fe x =0) l1txd x (bit 0) l1st x (on bit 0) l1st x driven from clock low both the data and l1st x from sync both the data and l1st x from the clock l1st x driven from sync data driven from clock high when asserted during clock high when asserted during clock low
communication processor module 16-136 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.5.3 serial interface clock route register. the 32-bit, read/write, memory-mapped serial interface clock route (sicr) register is used to define the universal serial bus and serial communication controller clock sources that can be one of the four baud rate generators or an input from a bank of clock pins. bits 0C7reserved these bits are reserved and must be set to 0. gr3grant support of scc3 0 = scc3 transmitter does not support the grant mechanism. the grant is always asserted internally. 1 = scc3 transmitter supports the grant mechanism as determined by the gmx bit of the simode register. sc3scc3 connection 0 = scc3 is not connected to the multiplexed serial interface but is either connected directly to the nmsi3 pins or is not used. you can choose either the general-purpose i/o port pins or dedicated scc3 pins in the parallel i/o port registers. see section 16.14 the parallel i/o ports for more information. 1 = scc3 is connected to the multiplexed serial interface. the nmsi3 receive pins are available for other purposes. sicr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved gr3 sc3 r3cs t3cs reset 00000 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xaec bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gr2 sc2 r2cs t2cs res r1cs reserved reset 000 000 0 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xaee
communication processor module motorola mpc823e reference manual 16-137 serial i/f communication 16 processor module r3csreceive clock source for scc3 this field is ignored when the scc3 is connected to the time-slot assigner (sc3 = 1). 000 = scc3 receive clock is brg1. 001 = scc3 receive clock is brg2. 010 = scc3 receive clock is brg3. 011 = scc3 receive clock is brg4. 100 = scc3 receive clock is clk1. 101 = scc3 receive clock is clk2. 110 = scc3 receive clock is clk3. 111 = scc3 receive clock is clk4. t3cstransmit clock source for scc3 this field is ignored when scc3 is connected to the time-slot assigner (sc3 = 1). 000 = scc3 transmit clock is brg1. 001 = scc3 transmit clock is brg2. 010 = scc3 transmit clock is brg3. 011 = scc3 transmit clock is brg4. 100 = scc3 transmit clock is clk1. 101 = scc3 transmit clock is clk2. 110 = scc3 transmit clock is clk3. 111 = scc3 transmit clock is clk4. gr2grant support of scc2 0 = scc2 transmitter does not support the grant mechanism. the grant is always asserted internally. 1 = scc2 transmitter supports the grant mechanism as determined by the gmx bit of the simode register. sc2scc2 connection 0 = scc2 is not connected to the multiplexed serial interface but is either connected directly to the nmsi2 pins or is not used. you can choose either the general-purpose i/o port pins or dedicated scc2 pins in the parallel i/o port registers. see section 16.14 the parallel i/o ports for more information. 1 = scc2 is connected to the multiplexed serial interface. the nmsi2 receive pins are available for other purposes.
communication processor module 16-138 mpc823e reference manual motorola serial i/f communication 16 processor module r2csreceive clock source for scc2 this field is ignored when the scc2 is connected to the time-slot assigner (sc2 = 1). 000 = scc2 receive clock is brg1. 001 = scc2 receive clock is brg2. 010 = scc2 receive clock is brg3. 011 = scc2 receive clock is brg4. 100 = scc2 receive clock is clk1. 101 = scc2 receive clock is clk2 . 110 = scc2 receive clock is clk3 . 111 = scc2 receive clock is clk4 . t2cstransmit clock source for scc3 this field is ignored when scc3 is connected to the time-slot assigner (sc3 = 1). 000 = scc3 transmit clock is brg1. 001 = scc3 transmit clock is brg2. 010 = scc3 transmit clock is brg3. 011 = scc3 transmit clock is brg4. 100 = scc3 transmit clock is clk1. 101 = scc3 transmit clock is clk2. 110 = scc3 transmit clock is clk3. 111 = scc3 transmit clock is clk4. bits 24C25reserved these bits are reserved and must be set to 0. r1csclock source for the usb 000 = usb clock is brg1. 001 = usb clock is brg2. 010 = usb clock is brg3. 011 = usb clock is brg4. 100 = usb clock is clk1. 101 = usb clock is clk2. 110 = usb clock is clk3. 111 = usb clock is clk4. bits 29C31reserved these bits are reserved and must be set to 0.
communication processor module motorola mpc823e reference manual 16-139 serial i/f communication 16 processor module 16.7.5.4 serial interface command register. the 8-bit serial interface command register (sicmr) allows you to dynamically program the serial interface ram. the contents of this register are only valid in the ram division mode. for more information about dynamic programming, refer to section 16.7.4.6 serial interface ram dynamic changes . csrr x change shadow ram for tdma or b receiver when set, this bit causes the serial interface receiver to replace the current route with the shadow ram. you set this bit and the serial interface clears it. 0 = the receiver shadow ram is not valid. you can write into the shadow ram to program a new routing. 1 = the receiver shadow ram is valid. the serial interface exchanges between the rams and take the new receive routing from the receiver shadow ram. this bit is cleared as soon as the switch has completed. csrt x change shadow ram for tdma or b transmitter when set, this bit causes the serial interface transmitter to replace the current route with the shadow ram. you set this bit and the serial interface clears it. 0 = the transmitter shadow ram is not valid. you can write into the shadow ram to program a new routing. 1 = the transmitter shadow ram is valid. the serial interface exchanges between the rams and take the new transmitter routing from the receiver shadow ram. this bit is cleared as soon as the switch has completed. bits 2C7reserved these bits are reserved and must be set to 0. sicmr bit 0 1 2 3 4 5 6 7 field csrra csrta csrrb csrtb reserved reset 0000 0 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xae7
communication processor module 16-140 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.5.5 serial interface status register. the 8-bit serial interface status register (sistr) lets you know which part of the serial interface ram is the current-route ram. the value of this register is only valid when the corresponding bit in the sicmr is cleared. croracurrent route of tdma receiver this bit is valid in the ram division mode (rdm field in the sigmr = 01). 0 = the current-route receiver ram is in address 0C63 when the serial interface supports tdma. 1 = the current-route receiver ram is in address 64C127 when the serial interface supports tdma. crotacurrent route of tdma transmitter this bit is valid in the ram division mode (rdm field in the sigmr = 01). 0 = the current-route transmitter ram is in address 128C191 when the serial interface supports tdma. 1 = the current-route transmitter ram is in address 192C255 when the serial interface supports tdma. crorbcurrent route of tdmb receiver this bit is valid in the ram division mode (rdm field in the sigmr = 11). 0 = the current-route receiver ram is in address 64-95 when the serial interface supports tdmb. 1 = the current-route receiver ram is in address 96-127 when the serial interface supports tdmb. crotbcurrent route of tdmb transmitter this bit is valid in the ram division mode (rdm field in the sigmr = 11). 0 = the current-route transmitter ram is in address 192-223. 1 = the current-route transmitter ram is in address 224-255. bits 4C7reserved these bits are reserved and must be set to 0. sistr bit 0 1 2 3 4 5 6 7 field crora crota crorb crotb reserved reset 0000 0 r/w rrrr r addr (immr & 0xffff0000) + 0xae6
communication processor module motorola mpc823e reference manual 16-141 serial i/f communication 16 processor module 16.7.5.6 serial interface ram pointer register. the 32-bit, read-only serial interface ram pointer (sirp) register indicates the ram entry that is currently being serviced. it contains the real-time status location of the serial interface that is currently inside the tdm frame. although you may not need to access the sirp register, it does provide information that might be helpful for debugging and for synchronizing system activity with tdm activity. usually, reading the sistr is sufficient for most applications. you can determine which ram entry in the serial interface ram is currently in progress, but you cannot determine the status within that entry. for example, if the ram entry is programmed to select four contiguous time-slots from the tdm and the sirp register indicates the entry is currently active, you will not know which of the four time-slots is currently in progress. the sirp register does, however, change its status as soon as the next serial interface ram entry begins processing. the value of this register changes on serial clock transitions. before acting on the information found in this register, you must perform two reads and verify that they returned the same value. the pointers provided by this register indicate the serial interface ram entry word offset that is currently in progress. note: you can externally connect one of the eight strobes to an interrupt pin to generate an interrupt on a particular serial interface ram entry. sirp bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved vtb tbptr reserved vta taptr reset 00 0 00 0 r/w rr r rr r addr (immr & 0xffff0000) + 0xaf0 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved vrb rbptr reserved vra raptr reset 00 0 00 0 r/w rr r rr r addr (immr & 0xffff0000) + 0xaf2
communication processor module 16-142 mpc823e reference manual motorola serial i/f communication 16 processor module bits 0C1 and 8C9reserved these bits are reserved and must be set to 0. vta, vtb, vra, and vrbtime-slot valid bits for serial interface ram entries the vtx or vrx bit in each entry shows that the entry is valid, which is helpful when the corresponding pointer entry value is zero. additionally, the vtx or vrx bit saves you from having to read both the sirp and the sistr registers to obtain the information you need. the pointer values are based on the value of the rdm field in the sigmr. bits 16C17 and 24C25reserved these bits are reserved and must be set to 0. taptr, tbptrraptr, and rbptrserial interface ram time-slot pointers in all cases, the value of the txptr or rxptr fields increment by one for each entry that the serial interface processes. since each txptr and rxptr is 5 bits each, the values in each field can range from 0 to 31, corresponding to 32 different serial interface ram entries. the full pointer range may not necessarily be used. for instance, if the last bit is set in the fifth serial interface ram entry, then the pointer only reflects values from 0 to 4, but once the fifth entry is processed by the serial interface, the pointer is reset to 0. 16.7.5.6.1 sirp indication when rdm = 00. you cannot signify 64 entries with a single 5- bit pointer. two 5-bit pointers are used instead: one for the first 32 entries and one for the last 32 entries. if the corresponding vtx or vrx bit is set, then: ? rxptr contains the address of the currently active rx ram entry. when the serial interface services entries 1C32, raptr is incremented and rbptr is continuously cleared. when the serial interface services entries 33C64, raptr is continuously cleared and rbptr is incremented. ? txptr contains the address of the currently active tx ram entry. when the serial interface services entries 1C32, taptr is incremented and tbptr is continuously cleared. when the serial interface services entries 33C64, taptr is continuously cleared and tbptr is incremented.
communication processor module motorola mpc823e reference manual 16-143 serial i/f communication 16 processor module 16.7.5.6.2 sirp indication when rdm = 01. for the receiver, rxptr is used, depending on the portion of the serial interface rx ram that is currently active. for the transmitter, txptr is used, depending on the portion of the serial interface tx ram that is currently active. if the corresponding vtx or vrx bit is set, then: ? raptr contains the address of the currently active rx ram entry. the serial interface ram receive address block that is used is 0C63 and the crora bit is set to 0 in the sistr. ? rbptr contains the address of the currently active rx ram entry. the serial interface ram receive address block that is used is 64C127 and the crora bit is set to 1 in the sistr. ? taptr contains the address of the currently active tx ram entry. the serial interface ram transmit address block that is used is 128C191 and the crota bit is set to 0 in the sistr. ? tbptr contains the address of the currently active tx ram entry. the serial interface ram transmit address block that is used is 192C255 and the crota bit is set to 1 in the sistr. 16.7.5.6.3 sirp when rdm = 10. this is the simplest case, since each pointer is used continuously and only has one function. ? raptr contains the address of the currently active rxa entry. ? rbptr contains the address of the currently active rxb entry. ? taptr contains the address of the currently active txa entry. ? tbptr contains the address of the currently active txb entry. 16.7.5.6.4 sirp when rdm = 11. in this case, each pointer is used continuously, but points to different sections of the si ram, depending on whether the pointers value is in the first half (0C15) or the second half (16C31). ? raptr contains the address of the currently active rxb entry. if the pointer has a value from 0C15, the current-route ram is si ram address block 0C31 and the crorb bit is set to 0 in the sistr. if the pointer has a value from 16C31, the current-route ram is si ram address block 32C63 and crorb is set to 1 in the sistr. ? rbptr contains the address of the currently active rxb entry. if the pointer has a value from 0C15, the current-route ram is si ram address block 64C95 and the crorb bit is set to 0 in the sistr. if the pointer has a value from 16C31, the current-route ram is si ram address block 96C127 and crorb is set to 1 in the sistr. ? taptr contains the address of the currently active txa entry. if the pointer has a value from 0C15, the current-route ram is si ram address block 128C159 and the crota bit is set to 0 in the sistr. if the pointer has a value from 16C31, the current-route ram is si ram address block 160C191 and crota is set to 1 in the sistr.
communication processor module 16-144 mpc823e reference manual motorola serial i/f communication 16 processor module ? tbptr contains the address of the currently active txb entry. if the pointer has a value from 0C15, the current-route ram is si ram address block 192C223 and the crotb bit is set to 0 in the sistr. if the pointer has a value from 224C255, the current-route ram is si ram address block 160C191 and crotb is set to 1 in the sistr. 16.7.6 idl interface operation the full-duplex isdn interchip digital link (idl) interface is used to connect a physical layer device to the mpc823e. the basic and primary rate of the idl bus is supported by the mpc823e. in the basic rate of idl, data on three channels (b1, b2, and d) is transferred in a 20-bit frame, providing 160kbps full-duplex bandwidth. the mpc823e is an idl slave device that is clocked by the idl bus master (physical layer device) and has separate receive and transmit sections. the mpc823e supports one idl bus as illustrated in figure 16-58. mpc823e figure 16-58. idl bus application example s/t u s/t idl1 s/t interface isdn te nt u interface interface interface interface
communication processor module motorola mpc823e reference manual 16-145 serial i/f communication 16 processor module 16.7.6.1 idl interface implementation. the mpc823e can identify and support each idl channel or it can output strobe lines for interfacing with devices that do not support the idl bus. the idl signals for each transmit and receive channel are as follows: ? l1rclk x idl clock pin. input to the mpc823e. ? l1rsync x idl sync pin. input to the mpc823e. this signal indicates that the clock periods following the pulse designate the idl frame. ? l1rxd x idl receive data pin. input to the mpc823e. valid only for the bits that are supported by the idl and ignored for other signals that may be present. ? l1txd x idl transmit data pin. output from the mpc823e. valid only for the bits that are supported by the idl. otherwise, it is three-stated. ? l1rq x idl request permission to transmit on the d channel. output from the mpc823e on the l1rq x pin. ? l1graidl grant permission to transmit on the d channel. input to the mpc823e on the l1tsynca pin. the basic rate idl bus has three channels: ? b1 is a 64kbps bearer channel ? b2 is a 64kbps bearer channel ? d is a 16kbps signaling channel
communication processor module 16-146 mpc823e reference manual motorola serial i/f communication 16 processor module there are two definitions of the idl bus frame structure8 and 10 bits. the only difference between them is the channel order within the frame. figure 16-59. idl terminal adaptor four wire b1 + b2 + d b2 + d b1 mpc82x system bus (rom and ram ) mc145474 s / t transceiver pots mc145554 pcm codec / filter monocircuit idl (data) icl (control) scc tsa async spi
communication processor module motorola mpc823e reference manual 16-147 serial i/f communication 16 processor module figure 16-60. idl bus signals note: previous versions of motorola idl-defined bit functions, called auxiliary (a) and maintenance (m), were eliminated from the idl definition when it was concluded that the idl control channel would be out-of-band. they were defined as a subset of the motorola spi format called serial control port (scp). if you prefer to implement the a and m bit functions as originally defined, you can program the time-slot assigner to access these bits and route them transparently to a serial communication controller or serial management controller. to perform the out-of-band signaling required, use the mpc823e serial peripheral interface. l1 x clk l1 x sync l1rxd x note: l1rq x and l1gr x are not shown. b1 d1 b2 d2 l1 x clk l1 x sync l1rxd x b1 b2 10-bit idl 8-bit idl d1 d2 l1txd x l1txd x b1 d1 b2 d2 b1 b2 d1 d2 (clock is not to scale) (clock is not to scale)
communication processor module 16-148 mpc823e reference manual motorola serial i/f communication 16 processor module the mpc823e supports all channels of the idl bus in the basic rate. each bit in the idl frame can be routed to every serial communication controller and serial management controller or they can assert a strobe output that supports an external device. the mpc823e supports the request-grant method for contention detection on the d channel of the idl basic rate and when the mpc823e has data to transmit on the d channel, it asserts the l1rq x pin. the physical layer device monitors the physical layer bus for activity on the d channel and indicates that the channel is free by asserting the l1gra pin. the mpc823e samples the l1gra pin when the idl sync signal (l1rsync x ) is asserted. if l1gra is high (active), the mpc823e transmits the first zero of the opening flag in the first bit of the d channel. if a collision is detected on the d channel, the physical layer device negates l1gra. the mpc823e then stops its transmission and retransmits the frame when l1gra is reasserted. this procedure is handled automatically for the first two buffers of a frame. for the primary rate idl, the mpc823e supports up to four 8-bit channels in the frame, determined by the serial interface ram programming. additionally, the mpc823e can be used to assert strobes to support additional external idl channels. the idl interface supports the ccitt i.460 recommendation for data rate adaptation since it separately accesses each bit of the idl bus. the current-route ram specifies the bits that are supported by the idl interface and the serial controller. the receiver only receives the bits that are enabled by the receiver route ram. otherwise, the transmitter only transmits the bits that are enabled by the transmitter route ram and three-states the l1txd x pin. 16.7.6.2 programming the idl interface. you can program the channels used for the idl bus interface to the appropriate configuration. first, using the gm x bit, program the simode register to the idl grant mode for that channel. if the receive and transmit section are used for interfacing to the same idl bus, using the crt x bits you can internally connect the receive clock and sync signals to the serial interface ram transmit section. however, the ram section used for the idl channels must be programmed to the preferred routing. for more information, see section 16.7.5 serial interface programming model . you must now define the idl frame structure to be a 1-bit delay from frame sync to data, to falling edge sample sync, and the clock edge to transmit on the rising edge of the clock. program the l1txd x pin to be three-stated when inactive by using the parallel i/o open-drain register. to support the d channel, you must program the appropriate gm x bit in the simode register and program the ram entry to route data to that serial communication controller. the two definitions of idl8 and 10 bitsare only supported by modifying the serial interface ram programming. in both cases, the l1gra pin is sampled with the l1tsync x signal and transferred to the d channel serial communication controller as a grant indication. the same procedure is used to support an idl bus in the second channel.
communication processor module motorola mpc823e reference manual 16-149 serial i/f communication 16 processor module 16.7.6.2.1 idl interface programming example. using the example in section 16.7.6.1 idl interface implementation as a base model, the initialization sequence is as follows: 1. assuming smc1 is connected to the b1 channel, smc2 is connected to the b2 channel, and scc2 is connected to the d channel, program the serial interface ram. write all entries that are not used with 0x0001, set the lst bit, and disable the routing function. 2. the simode equals 0x80008145. only tdma is used. the two smcs are connected to the time-slot assigner. 3. the sicr equals 0x0000c000. scc2 is connected to the time-slot assigner. scc2 supports the grant mechanism since it is on the d channel. 4. in the paodr, bit 9 is set to 1. configure l1txda to be an open-drain output. 5. in the papar, bits 9, 8, and 7 are set to 1. configure l1txda, l1rxda, and l1rclka. 6. in the padir, bits 9 and 8 are set to 1. padir bit 7 = 0. configure l1txda, l1rxda, and l1rclka. 7. in the pcpar, bits 12, 5, and 11 are set to 1. configure l1rqa, l1tsynca, and l1rsynca. 8. in the pcdir, bit 12 is set to 0. l1rqa is an input. l1tsynca performs the l1gra function and is therefore an output, but it does not need to be configured with pcdir bit 5 is set to 0. l1rsynca is an input, but it does not need to be configured with a pcdir bit. 9. thesigmr equals 0x04. enable tdma (one static tdm). 10. the sicmr is not used. entry number ram word swtr ssel csel cnt byt lst description 1 0 0000 101 0000 1 0 8 bits smc2 (b1) 2 0 0000 010 0000 0 0 1 bit scc2 (d) 3 0 0000 000 0000 0 0 1 bit no support 4 0 0000 110 0000 1 0 8 bits smc2 (b2) 5 0 0000 010 0000 0 1 1 bit scc2 note: since idl requires the same routing for both receive and transmit, an exact duplicate of the above entries must be written to both the receive and transmit sections of the serial interface ram beginning at serial interface ram addresses 0 and 128, respectively.
communication processor module 16-150 mpc823e reference manual motorola serial i/f communication 16 processor module 11. sistr and sirp do not need to be read, but can be used for debugging information once the channels are enabled. 12. enable scc2 to hdlc operation (to handle the lapd protocol of the d channel). set scc2 and smc1 to transparent operation. 16.7.7 gci interface operation the normal mode of the general circuit interface (gci) and scit are fully supported by the mpc823e. it also supports the d channel access control in s/t interface terminals by using the command/indication (c/i) channel for that function. the gci bus consists of four linestwo data lines, a clock, and a frame synchronization line. usually, an 8khz frame structure defines the various channels within the 256kbps data rate. the mpc823e supports an independent gci bus and has independent receive and transmit sections. the interface can also be used in a multiplexed frame structure on which up to eight physical layer devices can multiplex their gci channels. in this mode, the data rate would be 2,048kbps. in the gci bus, the clock rate is twice the data rate. the serial interface divides the input clock by two to produce the data clock. the mpc823e also has data strobe lines that are used as an interface for devices that do not support the gci bus. the gci signals for each transmit and receive channel are as follows: ? l1rsync x used as a gci sync signal. input to the mpc823e. this signal indicates that the clock periods following the pulse designate the gci frame. ? l1rclk x used as a gci clock. input to the mpc823e. the l1rclk x signal is twice the data clock. ? l1rxd x used as a gci receive data. input to the mpc823e. ? l1txd x used as a gci transmit data. open-drain output. valid only for the bits that are supported by the idl. otherwise, it is three-stated. figure 16-61. gci bus signals b1 b2 monitor c/ i d1 d2 t e b1 b2 monitor c/ i d1 d2 t e l1 x sync l1rxd x l1 x clk l1txd x (clock is not to sc a (2x the data rate)
communication processor module motorola mpc823e reference manual 16-151 serial i/f communication 16 processor module in addition to the 144kbps isdn 2b+d channels, the gci provides five channels for maintenance and control functions: ? b1 is a 64kbps bearer channel ? b2 is a 64kbps bearer channel ? m is a 64kbps monitor (m) channel ? d is a 16kbps signaling channel ? c/i is a 48kbps c/i channel (includes tand e bits) the m channel is used to transfer data between layer 1 devices and the control unit (the core) and the c/i channel is used to control activation/deactivation procedures or to switch test loops by the control unit. the m and c/i channels of the gci bus must be routed to smc1 or smc2, which have modes to support the channel protocols. the mpc823e can support any channel of the gci bus in the primary rate by modifying the serial interface ram programming. the gci supports the ccitt i.460 recommendation as a method for data rate adaptation since it can access each bit of the gci separately. the current-route ram specifies which the bits that are supported by the interface and serial communication controller. the receiver only receives the bits that are enabled by the serial interface ram and the transmitter only transmits the bits that are enabled by the serial interface ram and does not drive l1txd x . otherwise, l1txd x is an open-drain output and must be externally pulled high. the mpc823e supports contention detection on the d channel of the scit bus. when the mpc823e has data to transmit on the d channel, it checks a scit bus bit that is marked with a special route code (usually, bit 4 of c/i channel 2). the physical layer device monitors the physical layer bus for activity on the d channel and indicates on this bit that the channel is free. if a collision is detected on the d channel, the physical layer device sets bit 4 of c/i channel 2 to logic high. the mpc823e then aborts its transmission and retransmits the frame when this bit is set again. this procedure is automatically handled for the first two buffers of a frame. 16.7.7.1 gci activation/deactivation procedure. in the deactivated state, the clock pulse is disabled and the data line is at a logic one. the layer 1 device activates the mpc823e by enabling the clock pulses and sending an indication to c/i channel 0. using a maskable interrupt, the mpc823e lets the core know that a valid indication has been received in the smc receive buffer descriptor. when the core activates the line, the data output of l1txda is programmed to zero by setting the stz x bit in the simode register. code 0 (command timing tim) is transmitted on c/i channel 0 to the layer 1 device until the stz x bit is reset. the physical layer device resumes the clock pulses and gives an indication in c/i channel 0. the core must reset the stz x bit to enable data output.
communication processor module 16-152 mpc823e reference manual motorola serial i/f communication 16 processor module 16.7.7.2 programming the gci interface. there are two modes of the gci interfacenormal and scit. 16.7.7.2.1 normal mode. you can program and configure the channels used for the gci bus interface. first, program the simode register to the gci/scit mode for that channel. this mode defines the sync pulse to gci sync for framing and data clock as one-half the input clock rate. you can program more than one channel to interface to the gci bus. also, if the receive and transmit section are used for interfacing the same gci bus, using the crt x bit you must internally connect the receive clock and sync signals to the serial interface ram transmit section. then you must define the gci frame routing and strobe select using the serial interface ram. when the receive and transmit sections use the same clock and sync signals, these sections must be programmed to the same configuration. also, the l1txd x pin in the i/o register must be programmed to be an open-drain output. to support the monitor and c/i channels in gci, those channels must be routed to one of the serial management controllers. to support the d channel when there is no possibility of collision, you must clear the gr x bit corresponding to the serial communication controller that supports the d channel in the simode register. 16.7.7.2.2 scit mode. to interface with the gci/scit bus, the simode register must be programmed to gci/scit mode. the serial interface ram is programmed to support a 96-bit frame length and the frame sync is programmed to the gci sync pulse. generally, the scit bus supports the d channel access collision mechanism. for this purpose, you must program the receive and transmit sections to use the same clock and sync signals with the crt x bit and program the gr x bit to transfer the d channel grant to the serial communication controller that supports this channel. the received bit must be marked by programming the channel select bits of the serial interface ram to 111 for an internal assertion of a strobe on this bit. this bit is sampled by the serial interface and transferred to the d channel serial communication controller as the grant. the bit is generally bit 4 of the c/i in channel 2 of gci, but any other bit can be selected using the serial interface ram.
communication processor module motorola mpc823e reference manual 16-153 serial i/f communication 16 processor module 16.7.7.3 gci interface programming example. assuming scc2 is connected to the d channel, smc2 to the b1 channel, and smc1 to the c/i channels, the initialization sequence is as follows: 1. program the serial interface ram. write all entries that are not used with 0x0001, set the lst bit, and disable the routing function. 2. simode = 0x0000c000. scc2 is connected to the time-slot assigner. scc2 supports the grant mechanism since it is on the d channel. 3. the sicr equals 0x000040c0. scc2 is connected to the time-slot assigner. 4. in the paodr, bit 9 is set to 1. configure l1txda to be an open-drain output. 5. in the papar, bits 9, 8, and 7 are set to 1. configure l1txda, l1rxda, and l1rclka. 6. in the padir, bits 9 and 8 are set to 1 and in the padir, bit 7 is set to 0. configure l1txda, l1rxda, and l1rclka. 7. in the pcpar, bit 4 is set to 1. configure l1rsynca. 8. the sigmr equals 0x04.enable tdma (one static tdm). 9. the sicmr is not used. entry number ram word swtr ssel csel cnt byt lst description 1 0 0000 110 0000 1 0 8 bits smc2 (b1) 2 0 0001 000 0000 1 0 ext device (b2) 3 0 0000 101 0000 1 0 8 bits smc1 (m) 4 0 0000 010 0001 0 0 2 bits scc2 (d) 5 0 0000 101 0101 0 0 6 bits smc1 (i+a+e) 6 0 0000 000 0110 1 0 skip 7 bytes 7 0 0000 000 0001 0 0 skip 2 bits 8 0 0000 111 0000 0 1 d grant bit note: since gci requires the same routing for both receive and transmit, an exact duplicate of the above entries must be written to both the receive and transmit sections of the serial interface ram beginning at addresses 0 and 128, respectively. note: if scit mode is not used, delete the last three entries of the serial interface ram and set the lst bit in the new last entry.
communication processor module 16-154 mpc823e reference manual motorola serial i/f communication 16 processor module 10. sistr and sirp do not need to be read, but can be used for debugging information once the channels are enabled. 11. enable scc2 for hdlc operation (to handle the lapd protocol of the d channel). set smc1 for scit operation. set smc2 for transparent operation. 16.7.8 nonmultiplexed serial interface configuration the serial interface supports a nonmultiplexed serial interface (nmsi) mode for the serial communication controllers and serial management controllers. the sicr decides whether to connect sccx to the nmsi and the simode register decides whether to connect a serial management controller to the nmsi. the serial communication controllers or serial management controllers can be connected to the nmsi, regardless of the other channels connected to a tdm channel. you must keep in mind, however, that nmsi pins can be multiplexed with other functions at the parallel i/o lines. therefore, if some combination of the tdm and nmsi channels is used, you must consult the mpc823e pinout in section 2 external signals to decide if (and where) you plan to connect a serial communication controller or serial management controller. the clocks that are provided to the universal serial bus, serial communication controllers, and serial management controllers are derived from six sourcesfour internal baud rate generators and four external clk pins. there are two main advantages to this bank-of-clocks approach. first, a universal serial bus, serial communication controller, or serial management controller is not forced to choose its clock from a predefined pin or baud rate generator, which adds flexibility to the pinout mapping strategy. second, if a group of smc receivers and transmitters need the same clock rate they can share the same pin, which leaves other pins available for other functions and minimizes the potential skew between multiple clock sources. the four baud rate generators also make their clocks available to external logic, regardless of whether they are being used by a serial communication controllers or serial management controller. the brgox pins are multiplexed with other functions, so all brgo x pins may not always be available. for more information, see the pinout in section 2 external signals . the bank-of-clocks mapping has one restrictionthe smc transmitter must have the same clock source as the receiver when connected to the nmsi pins. once the clock source is selected, the clock is given an internal name. for the serial communication controllers, the clocks are called rclk2 and tclk2 and for the serial management controllers, they are called smclk1 and smclk2. these internal names are used only in nmsi mode to specify the clock that is sent to the serial communication controller or serial management controller. these names do not correspond to any pins on the mpc823e. note: the internal rclk2 and tclk2 can be used as inputs to the dpll unit, which is inside the serial communication controllers. thus, the rclk2 and tclk2 clocks are not always required to reflect the actual bit rate on the line.
communication processor module motorola mpc823e reference manual 16-155 serial i/f communication 16 processor module the pins available to the universal serial bus, serial communication controllers, and serial management controllers in nmsi mode are illustrated in figure 16-62. the modem control pins for the usb in nmsi mode are as follows: ? usbrxd ? usbrxp ? usbtxp ? usbclk brg1Cbrg4, clk1Cclk4 ? usbrxn ? usbtxn ? usboe figure 16-62. bank of clocks smc1 smc2 scc2 rx scc2 tx brg1 brg2 clk2 smclk1 smclk2 rclk2 tclk2 brgo1 brgo2 bank of clocks selection logic usb and sccs controlled in the sicr smcs controlled in the simode register clk4 usbclk usb clock brg3 brg4 brgo3 scc3 rx scc3 tx rclk3 tclk3 clk1 clk3
communication processor module 16-156 mpc823e reference manual motorola serial i/f communication 16 processor module the modem control pins for the scc2 in nmsi mode are as follows: ? txd2 ? rxd2 ? tclk2 brg1Cbrg4, clk1C4 ? rclk2 brg1Cbrg4, clk1C4 ? rts2 ? cts2 ? cd2 the modem control pins for the scc3 in nmsi mode are as follows: ? txd3 ? rxd3 ? tclk3 brg1Cbrg4, clk1C4 ? rclk3 brg1Cbrg4, clk1C4 ? rts3 ? cts3 ? cd3 the modem control pins for the smc1 in nmsi mode are as follows: ? smtxd1 ? smrxd1 ? smclk1 brg1Cbrg4, clk1C4 ? smsyn1 (used only in the totally transparent protocol) the modem control pins for the smc2 in nmsi mode are as follows: ? smtxd2 ? smrxd2 ? smclk2 brg1Cbrg4, clk1C4 ? smsyn2 (used only in the totally transparent protocol) unused usb, scc or smc signals can be used for other functions or configured for parallel i/o.
communication processor module motorola mpc823e reference manual 16-157 brgs communication 16 processor module 16.8 the baud rate generators the communication processor module contains four independent, yet identical, baud rate generators (brgs) that can be used with the universal serial bus, serial communication controllers, and serial management controllers. the clocks produced in the baud rate generator are sent to the bank-of-clocks selection logic, where they can be routed to the universal serial bus, serial communication controllers, or serial management controllers. in addition, the output of the baud rate generator can be routed to a pin to be used externally. the following is a list of the baud rate generators main features: ? four independent and identical baud rate generators ? on-the-fly changes are allowed ? each baud rate generator can be routed to the universal serial bus, serial communication controllers, or serial management controllers. ? a 16 divider option allows low baud rates at high system frequencies ? each baud rate generator contains an autobaud support option ? three of the baud rate generator outputs can be routed to the brgox pin the baud rate generator block diagram is illustrated in figure 16-63. figure 16-63. baud rate generator block diagram extc field div 16 cd[0:11] mux prescaler divide by 1 or 16 12 bit counter clock brgclk clk2 pin autobaud control rx source atb bit baud rate generator brgo x to pin and/or bank of clocks tx source clk4 pin 1C4,096
communication processor module 16-158 mpc823e reference manual motorola brgs communication 16 processor module the clock input to the prescaler can be selected by the extc field in the baud rate generator configuration registers to originate in one of three sourcesbrgclk, clk2 or clk4. the brgclk is generated in the mpc823e clock synthesizer specifically for the four baud rate generators, serial peripheral interface, and i 2 c internal baud rate generator. you can also configure the clk2 or clk4 pins to be the clock source. an external pin allows flexible baud rate frequency generation, regardless of the system frequency. additionally, the clk2 or clk4 pins allow a single external frequency to become the input clock for multiple baud rate generators. the clock signals on the clk2 or clk4 pins are not synchronized internally prior to being used by the baud rate generator. next, the baud rate generator provides a divide-by-16 option before the clock reaches the prescaler. this option is chosen by the div16 bit. the clock is then divided into the prescaler by a maximum of 4,096. this input clock divide ratio can be programmed on-the-fly. however, on-the-fly baud rate generator changes must not occur within a shorter time than the period of two baud rate generator input clocks. the output of the prescaler is sent internally to the bank of clocks and can also be output externally on the brgox pins of either the port a or port b parallel i/o. one brgox pin is an output from the corresponding baud rate generator. if the baud rate generator divides the clock by an even value, the transitions of the brgox pin always occur on the falling edge of the input clock to the baud rate generator. if the baud rate generator is programmed to an odd value, the transitions alternate between the falling and rising edges of the input clock. additionally, the output of the baud rate generator can be sent to the autobaud control block. note: four baud rate generators are available for the sccs and smcs. however, brgo3 and brgo4 cannot be output externally.
communication processor module motorola mpc823e reference manual 16-159 brgs communication 16 processor module 16.8.1 autobaud operation using the autobaud process, a uart determines the baud rate of its received character stream by examining the pattern received and the timing information of that pattern. the mpc823e baud rate generators have a built-in autobaud control function that automatically measures the length of a start bit and modifies the baud rate accordingly. if the atb bit in the baud rate generator configuration registers is set, the autobaud control block starts searching for a low level on the rxdx signal, which it assumes is the beginning of a start bit and begins counting the start bit length. during this time, the brg output clock toggles for 16 brg clock cycles at the brg input clock rate and then stops with the brgox output clock in the low state. after the rxdx signal changes back to the high level, the autobaud control block rewrites the cd and div16 bits in the baud rate generator configuration registers to the divide ratio it found. due to a measurement error that occurs at high baud rates, this divide ratio written by the autobaud controller may not be the precise baud rate you prefer (56,600 could be the resulting baud rate, rather than 57,600). thus, an interrupt is provided in the scceCuart register (described in section 16.9.15.18 sccx uart event register ) to signify that the baud rate generator configuration registers were rewritten by the autobaud controller. when this interrupt is recognized, you must rewrite the baud rate generator configuration registers with the value you prefer. it is recommended that this be done as quickly as possible (even prior to the first character being fully received) to ensure that all characters are recognized correctly by the uart. once a full character is received, you can check the software to verify that the received character matches a predefined value (such as a or a). the software must then check for other characters (such as t or t) and program a serial communication controller to the preferred parity mode. you can change the parity mode in the psmrCscc uart register, which is described in section 16.9.3 protocol-specific mode register . note: the serial communication controller associated with the baud rate generator must be programmed to uart mode and have the tdcr and rdcr fields in the gsmr_l set to the 16 option for the autobaud function to operate correctly. input frequencies, such as 1.32mhz, 3.68mhz, 7.36 mhz, and 14.72mhz, must be used. for autobaud to operate successfully, the serial communication controller must be connected to a baud rate generator. for instance, scc2 must be clocked by brg2 to successfully perform the autobaud function. also, for a serial communication controller to correctly detect an autobaud lock and generate an interrupt, it must receive three full receive clocks from the baud rate generator before the autobaud process begins. to do this, set the atb bit to 0 in the baud rate generator configuration register and enable the brgx receive clock to the highest frequency. immediately prior to the start of the autobaud process (after device initialization), set the atb bit to 1.
communication processor module 16-160 mpc823e reference manual motorola brgs communication 16 processor module 16.8.2 baud rate generator configuration registers the 32-bit, memory-mapped baud rate generator configuration (brgc1C4) registers are used to configure the baud rate generators. at reset, the baud rate generators are disabled and the brgox output clock is high. these registers can be written at any time and you do not need to disable any internal or external devices connected to the brgox output clock. changes to the baud rate generators occur at the end of the next brg clock cycle (no spikes occur on the brgox output clock). bits 0C13reserved these bits are reserved and must be set to 0. rstreset baud rate generator this bit performs a software reset of the baud rate generator identical to that of an external reset. a reset disables the baud rate generator and sets the brgox output clock. this can only be seen externally if the brgox function is enabled to reach the corresponding port a or b parallel i/o pin. 0 = enable the baud rate generator. 1 = reset the baud rate generator (software reset). enenable baud rate generator count this bit is used to dynamically stop the baud rate generator from counting, which may be useful for low-power modes. 0 = stop all clocks to the baud rate generator. 1 = enable clocks to the baud rate generator. brgc1Cbrgc4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved rst en reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9f0 (brgc1), 0x9f4 (brgc2), 0x9f8 (brgc3), 0x9fc (brgc4) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field extc atb cd div16 reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9f2 (brgc1), 0x9f6 (brgc2), 0x9fa (brgc3), 0x9fe (brgc4)
communication processor module motorola mpc823e reference manual 16-161 brgs communication 16 processor module extcexternal clock source this field selects the baud rate generator input clock from the internal brgclk or one of three external pins. 00 = the baud rate generator input clock comes from the brgclk (internal clock generated by the clock synthesizer in the system interface unit). 01 = the baud rate generator input clock comes from the clk2 pin. 10 = the baud rate generator input clock comes from the clk4 pin. 11 = reserved. atbautobaud when set, this bit selects autobaud operation of the baud rate generator on the corresponding rxdx pin. 0 = normal operation of the baud rate generator. 1 = when rxdx goes low, the baud rate generator determines the length of the start bit and synchronizes the baud rate generator to the actual baud rate. cdclock divider this field and the prescaler determines the baud rate generator output clock rate. they are used to preset a 12-bit counter that is decremented at the prescaler output rate, but the counter is inaccessible to you. when the counter reaches zero, it is reloaded from the clock divider bits. thus, a value of 0xfff in cd0Ccd11 produces the minimum clock rate (divide by 4,096), and a value of 0x0000 produces the maximum clock rate (divide by 1). even when dividing by an odd number, the counter ensures a 50% duty-cycle by asserting the terminal count once on clock low and next on clock high. the terminal count signals counter expiration and toggles the clock. div16brg clock prescaler divide by 16 0 = divide by 1 for the clock divider input. 1 = divide-by-16 prescaler enabled for the clock divider output. note: the atb bit must remain clear (0) until the serial communication controller receives the three rx clocks. then you must set this bit to one to obtain the correct baud rate. once the baud rate is obtained and locked, it is indicated by setting the ab bit in the scce-uart register in section 16.9.15.18 sccx uart event register . this bit may only be set for brg2.
communication processor module 16-162 mpc823e reference manual motorola brgs communication 16 processor module 16.8.3 uart baud rate examples for synchronous communication using the internal baud rate generator, the brgox output clock must never be faster than the system frequency divided by 2. so, with a 25mhz system frequency, the maximum brgox output clock rate is 12.5mhz. you must program the uart to 16 oversampling when using a serial communication controller in uart mode. on the mpc823e, 8 and 32 options are also available. assuming 16 oversampling is chosen in the uart, a data rate of 25mhz 16 = 1.5625mb/sec is the maximum possible uart speed. putting this together, the following formula must be used to calculate the bit rate based on a particular baud rate generator configuration for a uart: async baud rate = (brgclk, clk2 or clk4) (clock divider + 1) (1 or 16 depending on the div16 bit) (8, 16, or 32 according to the rdcr and tdcr fields in the gsmr_l register). the following table lists typical bit rates of asynchronous communication. the internal clock rate is assumed to be 16 the baud rate. table 16-23. typical baud rates of asynchronous communication baud rates mpc823e system frequency (mhz) 20 25 24.5760 div16 div actual frequency div16 div actual frequency div16 div actual frequency 50 1 1561 50.02 1 1952 50 1 1919 50 75 1 1040 75.05 1 1301 75 1 1279 75 150 1 520 149.954 1 650 150 1 639 150 300 1 259 300.48 1 324 300.5 1 319 300 600 0 2082 600.09 0 2603 600 0 2559 600 1200 0 1040 1200.7 0 1301 1200 0 1279 1200 2400 0 520 2399.2 0 650 2400.1 0 639 2400 4800 0 259 4807.7 0 324 4807.69 0 319 4800 9600 0 129 9615.4 0 162 9585.9 0 159 9600 19200 0 64 19231 0 80 19290 0 79 19200 38400 0 32 37879 0 40 38109 0 39 38400 57600 0 21 56818 0 26 57870 0 26 56889 115200 0 10 113636 0 13 111607 0 12 118154 note: all values are decimal.
communication processor module motorola mpc823e reference manual 16-163 sccs communication 16 processor module for synchronous communication, the internal clock is identical to the baud rate output. to get the preferred rate, you can select the appropriate system clock according to the following equation: sync baud rate = (brgclk, clk2 or clk4) ? (clock divider + 1) ? (1 or 16 according to the div16 bit) to get a rate of 64kbps, the system clock can be 24.96mhz, div16 = 0, and the clock divider = 389. 16.9 the serial communication controllers the mpc823e has two serial communication controllers (scc2 and scc3) that can be configured independently to implement different protocols. they can be used to implement bridging functions, routers, gateways, and interface with a wide variety of standard wans, lans, and proprietary networks. the serial communication controllers have many physical interface options, such as interfacing to tdm buses, isdn buses, and standard modem interfaces. the serial communication controllers does not include the physical interface, but it is the logic that formats and manipulates the data obtained from the physical interface. that is why the serial interface is described in a different section. the protocol you choose is independent of your physical interface preference. the serial communication controllers are described in terms of the protocol that you choose to run. when a serial communication controller is programmed to implement a certain protocol or mode, a certain level of functionality is associated with that protocol. for most protocols, this corresponds to the different parts of the link layer. many functions of the serial communication controllers are common to each of the following protocols: ? uart controller ? hdlc controller ? hdlc bus controller ? appletalk/localtalk controller ? asynchronous hdlc controller ? irda controller (scc2 only) ? transparent controller ? ethernet controller although the selected protocol usually applies to the sccx transmitter and receiver, half of a serial communication controller can run in transparent mode, while the other half runs the standard protocol.
communication processor module 16-164 mpc823e reference manual motorola sccs communication 16 processor module each internal clock of a serial communication controller can be programmed with either an external or internal source. the internal clocks originate from one of four baud rate generators or one of four external clock pins. these clocks can be as fast as a 1:2 ratio of a 12.5mhz system clock. however, a serial communication controllers ability to support a sustained bitstream depends on the protocol, as well as other factors. associated with each serial communication controller is a digital phase-locked loop (dpll) for external clock recovery (nrz, nrzi, fm0, fm1, manchester, and differential manchester). the dpll can be configured to nrz operation to pass the clocks and data to or from a serial communication controller without modifying it. the risc microcontroller is responsible for selecting and controlling the various ports and controllers of the communication processor module. for information about the serial communication controller command set, see table 16-2. a serial communication controller can be connected to its own set of pins on the mpc823e. this configuration is called the nonmultiplexed serial interface (nmsi) and is described in section 16.7 the serial interface with time-slot assigner . in this configuration, a serial communication controller can support the standard modem interface signalsrtsx , ctsx , and cdx through the port b, port c and cpm interrupt controller pins. additional handshake signals can be supported with additional parallel i/o lines. the serial communication controller block diagram is illustrated in figure 16-64. figure 16-64. serial communication controller block diagram control registers dpll and clock shifter shifter delimiter clock generator delimiter decoder encoder recovery receive control unit transmit control unit receive data fifo transmit data fifo modem lines modem lines u-bus peripheral bus tclk rclk internal clocks rxdx txdx
communication processor module motorola mpc823e reference manual 16-165 sccs communication 16 processor module 16.9.1 features the following is a list of the serial communication controllers main features: ? implements the hdlc, hdlc bus, asynchronous hdlc, synchronous start/stop, asynchronous start/stop, appletalk, transparent, and ethernet protocols ? supports full 10mbps ethernet/ieee 802.3 ? a single hdlc or transparent channel can be supported at 8mbps (full duplex) ? maximum clocking rates of 12.5mhz at 25mhz ? dpll circuitry for clock recovery with nrz, nrzi, fm0, fm1, manchester, and differential manchester (also known as differential bi-phase-l) ? clocks can be derived from a baud rate generator, an external pin, or dpll; data clock can be as high as 3.125mhz with a 25mhz clock ? supports automatic control of the rtsx , ctsx , and cdx modem signals ? multibuffer data structure for receive and transmit (up to 512 buffer descriptors can be partitioned in any way) ? deep fifos ? transmit-on-demand feature decreases time-to-frame transmission ? low fifo latency option for transmit and receive in character-oriented and totally transparent protocols ? frame preamble options ? full-duplex operation ? fully transparent option for receiver/transmitter while another protocol executes on the transmitter/receiver ? echo and local loopback modes for testing
communication processor module 16-166 mpc823e reference manual motorola sccs communication 16 processor module 16.9.2 the general sccx mode registers the serial communication controllers contain two high and low read/write general sccx mode registers (gsmr_h and gsmr_l) that define all the options common to each serial communication controller, regardless of the protocol. these registers are cleared at reset and since they are 64 bits in length, they are accessed as gsmr_l and gsmr_h. gsmr_l contains the first (low-order) 32 bits of the gsmr and gsmr_h contains the last 32 bits. bits 0C14reserved these bits are reserved and must be set to 0. gdeglitch detect enable this bit determines whether a serial communication controller will search for glitches on the external receive and transmit serial clock lines provided. if this feature is enabled, the presence of a glitch is reported in the scce register for each particular protocol. whether or not the gde bit is set, a serial communication controllers always attempts to clean up the clocks that it uses internally, via a schmitt trigger on the input lines. 0 = no glitch detection is performed. this option must be chosen if the external serial clock exceeds the limits of the glitch detection logic (6.25mhz assuming a 25mhz system clock). this option must also be chosen if the sccx clock is provided by one of the internal baud rate generators. lastly, this option must be chosen if external clocks are used and if it is more important to minimize power consumption than to watch for glitches. 1 = glitch detection is performed with a maskable interrupt generated in the scce register. gsmr_h bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved gde reset 0 0 r/w r/w r/w addr (immr & 0xfff0000) + 0xa24 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tcrc revd trx ttx cdp ctsp cds ctss tfl rfw txsy synl rtsm rsyn reset 0 0000000000 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xfff0000) + 0xa26
communication processor module motorola mpc823e reference manual 16-167 sccs communication 16 processor module tcrctransparent crc (totally transparent mode only) this field selects the type of frame checking that is provided on the transparent channels of a serial communication controller (either the receiver, transmitter, or both, as defined by the ttx and trx bits). although this configuration selects a frame check type, the actual decision to send the frame check is made in the tx buffer descriptor. thus, it is not required to send a frame check in transparent mode. if a frame check is not used, you can simply ignore the frame check errors that are generated on the receiver. 00 = 16-bit ccitt crc (hdlc). (x16 + x12 + x5 + 1). 01 = crc16. (x16 + x15 + x2 + 1). 10 = 32-bit ccitt crc (ethernet, hdlc, and high-speed irda). (x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1). also called crc32. 11 = reserved. revdreverse data (transparent mode only) 0 = normal operation. 1 = when set, this bit causes the totally transparent channels on the serial communication controller (either the receiver, transmitter, or both) to reverse the bit order and transmit the msb of each octet first. trxtransparent receiver the serial communication controllers offer totally transparent operation. however, to increase flexibility, totally transparent operation is not configured with the mode field of the gsmr_l, but with the ttx and trx bits. this gives you the opportunity to implement unique applications, such as configuring an sccx transmitter for uart operation and configuring the receiver for totally transparent operation. this can be done by setting the mode field to uart, ttx to 0, and trx to 1. 0 = normal operation. 1 = the receiver operates in totally transparent mode, regardless of the protocol selected for the transmitter in the mode field of the gsmr_l. note: full-duplex transparent operation for a serial communication controller is obtained by setting the ttx and trx bits. the serial communication controllers cannot operate with ethernet on the transmitter or while transparent operation is on the receiver. in other words, if the mode field is set for ethernet, then ttx must equal trx or erratic operation will occur.
communication processor module 16-168 mpc823e reference manual motorola sccs communication 16 processor module ttxtransparent transmitter the serial communication controllers offer totally transparent operation. however, to increase flexibility, totally transparent operation is not configured with the mode field of the gsmr_l, but with the ttx and trx bits. this allows you to implement unique applications, such as configuring an sccx receiver for hdlc operation and configuring a transmitter for totally transparent operation. this can be done by setting the mode field to hdlc, ttx to 1 and trx to 0. 0 = normal operation. 1 = the transmitter operates in totally transparent mode, regardless of the protocol selected for the receiver in the mode field of the gsmr_l. cdpcarrier-detect pulse this bit must be set if a serial communication controller is used in the time-slot assigner. 0 = normal operation (envelope mode). the cdx signal must envelope the frame. negating cdx while receiving data causes a cdx lost error. 1 = pulse mode. once the cdx signal is asserted, synchronization has been achieved and further transitions of cdx have no effect on reception. ctspcts pulse 0 = normal operation (envelope mode). the ctsx signal must envelope the frame. negating ctsx while transmitting data causes a ctsx lost error. 1 = pulse mode. once the ctsx signal is asserted, synchronization has been achieved and further transitions of ctsx have no effect on transmission. cdscarrier-detect sampling 0 = the cdx signal is assumed to be asynchronous with the data. it is internally synchronized by a serial communication controller and then data is received. 1 = the cdx signal is assumed to be synchronous with the data, which speeds up operation. in this mode, cdx must transition while the receive clock is in the low state. as soon as cdx is low, data is received. this mode is especially useful when connecting an mpc823e in transparent mode because it allows the rtsx signal of one mpc823e to be directly connected to the cdx signal of another mpc823e. note: full-duplex transparent operation for a serial communication controller is obtained by setting the ttx and trx bits. the serial communication controllers cannot operate with ethernet on the receiver or while transparent operation is on the transmitter. in other words, if the mode field is set to ethernet, then ttx must equal trx or erratic operation will occur.
communication processor module motorola mpc823e reference manual 16-169 sccs communication 16 processor module ctsscts sampling 0 = the ctsx signal is assumed to be asynchronous with the data. it is internally synchronized by a serial communication controller and data is then transmitted after several serial clock delays. 1 = the ctsx signal is assumed to be synchronous with the data, which speeds up operation. in this mode, ctsx must transition while the transmit clock is in the low state. as soon as ctsx is low, data immediately begins transmission. this mode is especially useful when connecting an mpc823e in transparent mode since it allows the rtsx signal of one mpc823e to be directly connected to the ctsx signal of another mpc823e. tfltransmit fifo length 0 = normal operation. the transmit fifo is 32 bytes for each serial communication controller. 1 = the transmit fifo is 1 byte and can be used with character-oriented protocols to ensure a minimum fifo latency at the expense of performance. rfwreceive fifo width 0 = receive fifo is 32 bits wide for maximum performance. data is not normally written to receive buffers until at least 32 bits are received. this configuration is required for hdlc-type protocols and ethernet, but it is recommended for high-performance transparent modes. in this mode, the receive fifo is 32 bytes for each serial communication controller. 1 = low-latency operation. the receive fifo is 8 bits wide and the receive fifo is a quarter its normal size (8 bytes). this allows data to be written to the data buffer when a character is received, instead of waiting to receive 32 bits. this configuration must be chosen for character-oriented protocols, such as uart. it can also be used for low-performance, low-latency, transparent operation, if preferred. however, when it is used with hdlc, hdlc bus, appletalk, or ethernet modes, erratic behavior occurs. txsytransmitter synchronized to the receiver this bit is specifically intended for x.21 applications in which the transmitted data must begin an exact multiple of 8-bit periods after the received data arrives. 0 = no synchronization between receiver and transmitter (default). 1 = the transmit bitstream is synchronized to the receiver. additionally, if the rsyn bit is set to 1, then transmission in the totally transparent mode does not occur until the receiver has synchronized with the bitstream and the ctsx signal is asserted to a serial communication controller. assuming ctsx is already asserted, transmission begins eight clocks after the receiver starts receiving data.
communication processor module 16-170 mpc823e reference manual motorola sccs communication 16 processor module synlsync length (transparent mode only) this field determines the operation of the sccx receiver that is configured for totally transparent operation. 00 = the sync pattern in the dsr (described in section 16.9.4 data synchronization register ) is not used. an external sync signal is used instead. 01 = 4-bit sync. the receiver synchronizes on a 4-bit sync pattern stored in the dsr. this character and additional syncs can be programmed to be stripped using the sync character in the parameter ram. the transmitter transmits the entire contents of the dsr prior to each frame. 10 = 8-bit sync. the receiver synchronizes on an 8-bit sync pattern stored in the dsr. the transmitter transmits the entire contents of the dsr prior to each frame. 11 = 16-bit sync. the receiver synchronizes on a 16-bit sync pattern stored in the dsr. the transmitter transmits the dsr prior to each frame. rtsmrts mode this bit indicates the mode of the request-to-send modem signal. it can be changed on-the- fly. 0 = send idles between frames as defined by the protocol and the tend bit in the gsmr_l. rtsx is negated between frames (default). 1 = send flags/syncs between frames according to the protocol. rtsx is always asserted when a serial communication controller is enabled. rsynreceive synchronization timing (transparent mode only) 0 = normal operation. 1 = if the cds bit is set to 1, then the cdx signal must be asserted on the second bit of the receive frame, rather than the first. gsmr_l bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res edge tci tsnc rinv tinv tpl tpp tend tdcr reset 000000 0 000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xfff0000) + 0xa20 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field rdcr renc tenc diag enr ent mode reset 00 00000 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xfff0000) + 0xa22
communication processor module motorola mpc823e reference manual 16-171 sccs communication 16 processor module bit 0reserved this bit is reserved and must be set to 0. edgeclock edge this field determines the clock edge the dpll uses to adjust the received sample point after a jitter occurs in the received signal. these bits are ignored in the uart protocol or the x1 mode of the rdcr field. 00 = both the positive and negative edges are used for changing the sample point (default). 01 = positive edge. only the positive edge of the received signal is used for changing the sample point. 10 = negative edge. only the negative edge of the received signal is used for changing the sample point. 11 = no adjustment is made to the sample point. tcitransmit clock invert 0 = normal operation. 1 = before it is used, the internal transmit clock (tclk) is inverted by a serial communication controller. this allows a serial communication controller to clock data out one-half clock earlier on the rising edge of tclk rather than on the falling edge. in this mode, the serial communication controllers offer a minimum and maximum rising clock edge to data specification. data output by a serial communication controller after the rising edge of an external transmit clock can be latched by the external receiver one clock cycle later on the next rising edge of the same transmit clock. this option is recommended for ethernet, hdlc, or transparent operation when the clock rates are higher than 8mhz to improve data setup time for the external receiver. tsnctransmit sense this bit indicates the amount of time the internal sense signal stays active after the last transition on the rxdx pin, thus indicating that the line is free. for instance, tsnc can be used in the appletalk protocol to avoid a spurious ctsx -changed interrupt that would otherwise occur during the frame sync sequence preceding the opening flags. if the rdcr field is configured to 1 mode, the delay is the greater of the two numbers listed. if rdcr is configured to 8 , 16 , or 32 mode, the delay is the lesser of the two numbers listed. 00 = infinitecarrier sense is always active (default). 01 = 14- or 6.5-bit times as determined by the rdcr field. 10 = 4- or 1.5-bit times as determined by the rdcr field (normally for appletalk). 11 = 3- or 1-bit times as determined by the rdcr field.
communication processor module 16-172 mpc823e reference manual motorola sccs communication 16 processor module rinvdpll receive input invert data this bit must be zero in hdlc bus mode. 0 = do not invert. 1 = invert the data before sending it to the on-chip dpll for reception. this setting is used to produce fm1 from fm0 and nrzi space from nrzi mark. it can also be used in regular nrz mode to invert the datastream. tinvdpll transmit input invert data this bit must be zero in hdlc bus mode. 0 = do not invert. 1 = invert the data before sending it to the on-chip dpll for transmission. this setting is used to produce fm1 from fm0 and nrzi space from nrzi mark. it can also be used in regular nrz mode to invert the datastream. tpltransmit preamble length this field determines the length of the preamble configured by the tpp field. 000 = no preamble (default). 001 = 8 bits (1 byte). 010 = 16 bits (2 bytes). 011 = 32 bits (4 bytes). 100 = 48 bits (6 bytes). select this setting for ethernet operation. 101 = 64 bits (8 bytes). 110 = 128 bits (16 bytes). 111 = reserved. tpptransmit preamble pattern this field determines the possible bit pattern that must precede the beginning of each transmit frame. the preamble pattern is sent prior to the first flag/sync of the frame. tpp is ignored if a serial communication controller is programmed to uart mode. the length of the preamble is programmed in the tpl field and the preamble pattern is typically transmitted to a receiving station that uses a dpll for clock recovery. the receiving dpll uses the regular pattern of the preamble to help it lock onto the received signal in a short, predictable time period. 00 = all zeros. 01 = repetitive 10s. select this setting for ethernet operation. 10 = repetitive 01s. 11 = all ones. select this setting for localtalk operation. note: in t1 applications, setting the tinv and tend bits creates a continuously inverted hdlc datastream.
communication processor module motorola mpc823e reference manual 16-173 sccs communication 16 processor module tendtransmitter frame ending this bit is specifically intended for nmsi transmitter encoding of the dpll. this bit determines whether the txdx signal must idle in a high state or in an encoded ones state (high or low). it can, however, be used with other encodings besides nmsi. 0 = default operation. the txdx signal is only encoded when data is transmitted, including the preamble and opening and closing flags/syncs. when no data is available to transmit, the signal is driven high. 1 = the txdx signal is always encoded, even when idles are transmitted. tdcrtransmit divide clock rate this field determines the divider rate of the transmitter. if the dpll is not used, the 1x value must be chosen, except in asynchronous uart mode, which requires 8x, 16x, or 32x to be chosen. you must program tdcr to equal rdcr in most applications. if the dpll is used in the application, the selection of tdcr depends on the encoding. nrzi usually requires 1x , whereas fm0/fm1, manchester, and differential manchester allow 8x, 16x, or 32x. the 8x option allows highest speed, whereas the 32x option provides the greatest resolution. tdcr is usually equal to rdcr so that the same clock frequency source can control both the transmitter and receiver. 00 = 1x clock mode. only nrz or nrzi encodings are allowed. 01 = 8x clock mode. 10 = 16x clock mode. normally chosen for uart and appletalk. 11 = 32x clock mode. rdcrreceive dpll clock rate this field determines the divider rate of the receive dpll. if the dpll is not used, the 1x value must be chosen, except in asynchronous uart mode, which requires 8x, 16x, or 32x to be chosen. you must program this field to equal tdcr in most applications. if the dpll is used in the application, the selection of rdcr depends on the encoding. nrzi usually requires 1x, whereas fm0, fm1, manchester, and differential manchester allow 8x, 16x, or 32x. the 8x option allows highest speed, whereas the 32x option provides the greatest resolution. 00 = 1x clock mode. only nrz or nrzi decodings are allowed. 01 = 8x clock mode. 10 = 16x clock mode. normally chosen for uart and appletalk. 11 = 32x clock mode.
communication processor module 16-174 mpc823e reference manual motorola sccs communication 16 processor module rencreceiver decoding method 000 = nrz (default setting if dpll is not used). 001 = nrzi mark (also set rinv for nrzi space). 010 = fm0 (also set rinv for fm1). 011 = reserved. 100 = manchester. 101 = reserved. 110 = differential manchester (differential bi-phase-l). 111 = reserved. tenctransmitter encoding method 000 = nrz (default setting if dpll is not used). 001 = nrzi mark (also set tinv for nrzi space). 010 = fm0 (also set tinv for fm1). 011 = reserved. 100 = manchester. 101 = reserved. 110 = differential manchester (differential bi-phase-l). 111 = reserved. diagdiagnostic mode the data received enters the rxdx pin and the transmit data is shifted out through the txdx pin. the serial communication controllers use the modem signals to automatically enable or disable transmission and reception. these timings are shown in section 16.9.10 controlling sccx timing . in local loopback mode, the transmitter output is internally connected to the receiver input, while the receiver and the transmitter operate normally. the value on the rxdx pin is ignored. data can be programmed to appear on the txdx or the port a register can be programmed to make the txdx pin high. see section 16.14 the parallel i/o ports for more information. the rtsx pin can also be programmed to be disabled in the appropriate parallel i/o register. in the sdmx field of the simode register, the l1txdx and l1rqx signals can be programmed to be either asserted normally or to remain inactive. see section 16.7.5.2 serial interface mode register for more information. note: select nrz if the dpll is not used. you must program this bit to equal tenc in most applications. however, do not use this internal dpll for ethernet mode. note: select nrz if the dpll is not used. you must program this bit to equal renc in most applications. however, do not use this internal dpll for ethernet mode.
communication processor module motorola mpc823e reference manual 16-175 sccs communication 16 processor module when using local loopback mode, the clock source for the transmitter and receiver must be the same. thus, the same baud rate generator or external clkx pin can be used for both the transmitter and receiver. separate clkx pins can be used with the transmitter and receiver as long as the clkx pins are connected to the same external clock signal source. in automatic echo mode, the channel automatically retransmits the received data on a bit-by-bit basis using whatever receive clock is provided. the receiver operates normally and receives data if cdx is asserted. the transmitter simply transmits the received data. in this mode, the ctsx signal is ignored. the echo function can be implemented in the software by receiving buffers from a serial communication controller, linking them to transmit buffer descriptors, and then transmitting them back out of that serial communication controller. in loopback/echo mode, loopback and echo operation occur simultaneously. the cdx and ctsx pins are ignored. refer to the loopback bit description for clocking requirements. 00 = normal operation. the ctsx and cdx signals are under automatic control. 01 = local loopback mode. 10 = automatic echo mode. 11 = loopback and echo mode. enrenable receive this bit enables the receiver hardware state machine for a serial communication controller. when enr is cleared, the receiver is disabled and any data in the receive fifo is lost. if enr is cleared during reception, the receiver aborts the current character. enr may be set or cleared, regardless of whether the serial clocks are present. refer to section 16.9.14 disabling the sccs on-the-fly for a description of how to disable and reenable a serial communication controller. note: if you prefer external loopback, the diag field must be selected for normal operation and an external connection must be made between the txdx and rxdx pins. clocks can be generated internally using a baud rate generator or they can be generated externally. you can physically connect the appropriate control signals or the port c register can be used to cause the cdx and ctsx pins to be permanently asserted to a particular serial communication controller. note: the serial communication controller that controls reception provides other tools besides the enr bit. some of these tools include the enter hunt mode command, close rx bd command, and the e bit of the receive buffer descriptor.
communication processor module 16-176 mpc823e reference manual motorola sccs communication 16 processor module entenable transmit this bit enables the transmitter hardware state machine for a serial communication controller. when ent is cleared, the transmitter is disabled. if ent is cleared during transmission, the transmitter aborts the current character and the txdx pin returns to the idle state. data already in the transmit shift register is not transmitted. ent can be set or cleared, regardless of whether the serial clocks are present. refer to section 16.9.14 disabling the sccs on-the-fly for a description of how to properly disable and reenable a serial communication controller. modechannel protocol mode 0000 = hdlc. 0001 = reserved. 0010 = appletalk/localtalk. 0011 = ss7. reserved for ram microcode. 0100 = uart. 0101 = profibus. reserved for ram microcode. 0110 = async hdlc/irda. 0111 = v.14. reserved for ram microcode. 1000 = reserved. 1001 = ddcmp. reserved for ram microcode. 1010 = reserved. 1011 = reserved. 1100 = ethernet. 11xx = reserved. 16.9.3 protocol-specific mode register the functionality of each serial communication controller varies according to the protocol selected in the mode field of the gsmr_l. each serial communication controller has an additional 16-bit, memory-mapped, read/write protocol-specific mode register (psmr) that configures it for a particular mode. since every sccx protocol has specific requirements, the psmr bits are different for each protocol. note: the serial communication controller that controls transmission provides other tools besides the ent bit. these tools include the stop transmit command, graceful stop transmit command, restart transmit command, the freeze option in uart mode, ctsx flow control option in uart mode, and the r bit of the transmit buffer descriptor.
communication processor module motorola mpc823e reference manual 16-177 sccs communication 16 processor module 16.9.4 data synchronization register each serial communication controller has a 16-bit, memory-mapped, read/write data synchronization register (dsr) that specifies the pattern used in the frame synchronization procedure of the synchronous protocols. in the uart protocol, it is used to configure fractional stop bit transmission. in the transparent protocol, it must be programmed with the preferred sync pattern. in the ethernet protocol, it must be programmed with 0xd555. at reset, it defaults to 0x7e7e (two hdlc flags), so it does not need to be written for hdlc mode. when the dsr is used to send out syncs (such as in transparent mode), the contents of the dsr are always transmitted least-significant bit first. 16.9.5 transmit-on-demand register if no frame is currently being transmitted by a serial communication controller, the risc microcontroller periodically polls the r bit of the next transmit (tx) buffer descriptor to see if you have requested a new frame/buffer to be transmitted. this polling algorithm depends on the configuration of the serial communication controller, but it occurs every 8 to 32 serial transmit clocks. you can, however, request that the risc microcontroller begin processing the new frame/buffer immediately, without waiting until the normal polling time. to obtain immediate processing, set the tod bit in the transmit-on-demand register (todr) after you set the r bit in the tx buffer descriptor. this feature, which decreases the transmission latency of the transmit buffer/frame, is particularly useful for lan-type protocols in which maximum interframe gap times are limited by the protocol specification. since the transmit-on-demand feature gives high priority to the specified tx buffer descriptor, it can affect the servicing of the receive fifo. therefore, it is recommended that you only use the transmit-on-demand feature when a high-priority tx buffer descriptor has been prepared and if a sufficient amount of time has passed since a serial communication controller was transmitted. dsr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field syn2 syn1 reset 0111111001111110 r/w r/w r/w addr (immr & 0xfff0000) + 0xa2e
communication processor module 16-178 mpc823e reference manual motorola sccs communication 16 processor module the tod bit does not need to be set if a new tx buffer descriptor is added to the circular queue or if other tx buffer descriptors in that queue have not finished transmitting. once they are finished, however, the new tx buffer descriptors are processed. the first bit of the frame will typically be clocked out 5-6 bit times after the tod bit has been set to 1. todtransmit on demand 0 = normal operation. 1 = the risc microcontroller gives high priority to the current tx buffer descriptor and does not wait the normal polling time to check that the tx buffer descriptors r bit has been set. instead, it begins transmitting the frame. this bit is automatically cleared after one serial clock. bits 1C15reserved these bits are reserved and must be set to 0. 16.9.6 sccx buffer descriptor operation data associated with a serial communication controller channel transmitter and receiver is stored in buffers and each buffer is referenced by a buffer descriptor that can be located anywhere in internal memory. the mpc823e internal memory has enough space for 224 buffer descriptors (bds) to be shared between the universal serial bus, serial communication controllers, serial managment controllers, serial peripheral interface, and i 2 c controller. however, you must define how the buffer descriptors will be allocated to the serial channels transmitter or receiver. you can select 100 buffer descriptors for the sccx receiver or 20 buffer descriptors for the transmitter. the buffer descriptor table forms a circular queue with a programmable length. you can program the start address of each channel buffer descriptor table in the internal memory. in addition, you can allocate the parameter area of an unused channel to other used channels as buffer descriptor tables or actual buffers. see figure 16-65 for details. todr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field tod reserved reset 00 r/w r/w r/w addr 0xa2c note: the communication processor module sets all the status bits in these buffer descriptors, but you must clear them before submitting the buffer descriptor to the communication processor module. for example, the parity error bit is only set when a parity error occurs.
communication processor module motorola mpc823e reference manual 16-179 sccs communication 16 processor module the format of the buffer descriptors is the same for each serial communication controller mode of operation and for transmit and receive. the first word in each buffer descriptor contains a status and control word that determines the buffer descriptors table length. only this first field, which contains the status and control bits, differs for each protocol. the second word determines the data length referenced to this buffer descriptor and the last two words in the buffer descriptor contain a 32-bit address pointer that points to the actual buffer in memory. r/eready/empty ready (transmitter): 0 = the data buffer associated with this buffer descriptor is not ready to be transmitted. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered. 1 = the data buffer, which you must prepare for transmission, has not been transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. empty (receiver): 0 = the data buffer associated with this rx buffer descriptor has been filled with data or reception has been aborted because of an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor again as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or is currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. wwrap 0 = this is not the last buffer descriptor in the buffer descriptor ring. 1 = this is the last buffer descriptor in the buffer descriptor ring. after this buffer has been used, the communication processor module will transmit (receive) data from the first buffer descriptor that tbase (rbase) points to in the table. the number of tx buffer descriptors in the ring are programmable and determined only by the w bit and overall space constraints of the dual-port ram. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r/e w i status and control offset + 2 data length offset + 4 high-order data buffer pointer offset + 6 low-order data buffer pointer
communication processor module 16-180 mpc823e reference manual motorola sccs communication 16 processor module iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the specific rx or tx bit in the protocol event register is set when this buffer is serviced by the communication processor module. these bits can cause an interrupt when enabled by the mask register. for frame-oriented protocols, a message can reside in as many buffers as necessary. each buffer has a maximum length of (64kC1) bytes. the communication processor module does not assume that all buffers of a single frame are currently linked to the buffer descriptor table. it does assume, however, that the unlinked buffers are provided by the core in time to be transmitted or received. when this does not occur, an error condition is reported by the communication processor module. an underrun error is reported when data is transmitted and a busy error is reported when data is received. figure 16-65. sccx memory structure frame status data length data pointer sccx tx bd table dual- port ram external memory tx buffer descriptors rx buffer descriptors tx data buffer frame status data length data pointer rx data buffer sccx rx bd table pointer sccx tx bd table pointer sccx rx bd table
communication processor module motorola mpc823e reference manual 16-181 sccs communication 16 processor module all protocols can have their buffer descriptors point to data buffers that are located in the internal dual-port ram. however, because the internal ram is being used for buffer descriptors, it is customary for the data buffers to be located in external ram, especially if the data buffers are large. in most instances, the internal u-bus is used to transfer data to the data buffer. the communication processor module processes the tx buffer descriptors in a straightforward manner. once the transmit side of a serial communication controller is enabled, it starts with the first buffer descriptor in that sccx transmit table. once the communication processor module detects that the r bit is set in the tx buffer descriptor, it starts processing the buffer. the communication processor module detects that the buffer descriptor is ready when it polls the r bit or when you try to write to the todr. once the data from the buffer descriptor has been placed in the transmit fifo, the communication processor module moves on to the next buffer descriptor, again waiting for that buffer descriptor r bit to be set. thus, the communication processor module does no look-ahead buffer descriptor processing, nor does it skip over buffer descriptors that are not ready. when the communication processor module sees the w bit set in a buffer descriptor, it goes back to the beginning of the buffer descriptor table after processing of the buffer descriptor is complete. after using a buffer descriptor, the communication processor module normally sets the r bit to 0, thus, the communication processor module does not use a buffer descriptor twice until the buffer descriptor has been confirmed by the core. the one exception to this rule is that the mpc823e supports an option for repeated transmission called continuous mode, whereby the r bit stays set to 1. this is available in some protocols. the communication processor module uses the rx buffer descriptors in a similar fashion. once the receive side of a serial communication controller is enabled, it starts with the first buffer descriptor in that sccx receive buffer descriptor table. once data arrives from the serial line into a serial communication controller, the communication processor module performs certain required protocol processing on the data and moves the resultant data to the data buffer pointed to by the first buffer descriptor. use of a buffer descriptor is complete when there is no more room left in the buffer or when certain events occur, such as detection of an error or an end-of-frame. whatever the reason, the buffer is then closed and additional data is stored using the next buffer descriptor. whenever the communication processor module needs to begin using a buffer descriptor because new data is arriving, it checks the e bit of that buffer descriptor. if the current buffer descriptor is not empty, it reports a busy error. however, it does not move from the current buffer descriptor until it is empty. when the communication processor module discovers the w bit set in a buffer descriptor, it goes back to the beginning of the buffer descriptor table after processing is complete and after using a buffer descriptor, the communication processor module sets the e bit to 0 and never uses a buffer descriptor twice until it has been processed by the core. the one exception to this rule is that the mpc823e supports an option for repeated reception called continuous mode, whereby the e bit stays set to 1. this is available in some protocols.
communication processor module 16-182 mpc823e reference manual motorola sccs communication 16 processor module 16.9.7 sccx parameter ram memory map the serial communication controller parameter ram area begins at an offset from the sccx base area. the protocol-specific portions of the sccx parameter ram are discussed in the specific protocol descriptions and the part that is common to all serial communication controller protocols is shown in table 16-24. you must initialize certain parameter ram values before enabling the serial communication controllers. other values are initialized or written by the communication processor module. once initialized, most parameter ram values do not need to be accessed in your software because most of the activity is centered around the transmit and receive buffer descriptors, not the parameter ram. however, if you do access the parameter ram, the following regulations must be noted: ? the parameter ram can be read at any time. ? the parameter time values related to the sccx transmitter can only be written whenever the transmitter is disabled after a stop transmit command and before a restart transmit command or after the buffer/frame finishes transmitting as a result of the execution of a graceful stop transmit command and before a restart transmit command is executed. ? the parameter ram values related to the sccx receiver can only be written when the receiver is disabled. refer to section 16.9.14 disabling the sccs on-the-fly for more information.
communication processor module motorola mpc823e reference manual 16-183 sccs communication 16 processor module ? rbase and tbasethe dual-port ram starts receiving and transmitting data for the sccx buffer descriptors in the rbase and tbase entries. they allow more flexibility in partitioning the sccx buffer descriptors. by selecting rbase and tbase entries for a serial communication controller and by setting the w bit in the last buffer descriptor in each buffer descriptor list, you can select how many buffer descriptors to allocate for the transmit and receive side of a serial communication controller. however, you must initialize these entries before enabling the corresponding channel. table 16-24. sccx parameter ram memory map for all protocols address name width description sccx base + 00 rbase half-word rx buffer descriptor base address sccx base + 02 tbase half-word tx buffer descriptor base address sccx base + 04 rfcr byte rx function code sccx base + 05 tfcr byte tx function code sccx base + 06 mrblr half-word maximum receive buffer length sccx base + 08 rstate word rx internal state sccx base + 0c rptr word rx internal data pointer sccx base + 10 rbptr half-word rx buffer descriptor pointer sccx base + 12 rcnt half-word rx internal byte count sccx base + 14 rtmp word rx temp sccx base + 18 tstate word tx internal state sccx base + 1c tptr word tx internal data pointer sccx base + 20 tbptr half-word tx buffer descriptor pointer sccx base + 22 tcnt half-word tx internal byte count sccx base + 24 ttmp word tx temp sccx base + 28 rcrc word temp receive crc sccx base + 2c tcrc word temp transmit crc sccx base + 30 first word of protocol-specific area sccx base + xx last word of protocol-specific area note: you are only responsible for initializing the items in bold. sccx base = (immr & 0xffff0000) + 0x3d00 (scc2) and 0x3e00 (scc3). note: rbase and tbase must contain a value that is divisible by eight.
communication processor module 16-184 mpc823e reference manual motorola sccs communication 16 processor module ? rfcr and tfcrthere are two function code registers for the sccx channelone for receive data buffers and one for transmit data buffers. the function code entry contains the value that you want to appear on the at pins when the associated sdma channel accesses memory. it also controls the byte-ordering convention for transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set these bits to select the required byte ordering of the data buffer. if this field is modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type these bits contain the function code value used during the sdma channel memory access. at0 is driven with a 1 to identify this sdma channel access as a dma type. rfcr bit 0 1 2 3 4 5 6 7 field reserved bo at reset 000 r/w r/w r/w r/w addr sccx base + 0x00 tfcr bit 0 1 2 3 4 5 6 7 field reserved bo at1Cat3 reset 000 r/w r/w r/w r/w addr sccx base + 0x02
communication processor module motorola mpc823e reference manual 16-185 sccs communication 16 processor module bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set these bits to select the required byte ordering of the data buffer. if this field is modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type these bits contain the function code value used during this sdma channel memory access. at0 is driven with a 1 to identify this sdma channel access as a dma type. ? mrblreach serial communication controller has one maximum receive buffer length register to define the receive buffer length. mrblr defines the maximum number of bytes that the mpc823e writes to a receive buffer on a serial communication controller before it moves on to the next buffer. the mpc823e can write fewer bytes to the buffer than mrblr if a condition, such as an error or end-of-frame occurs, but it never writes more bytes than the mrblr value. it follows then, that buffers you supply must always be at least as long as the mrblr. the transmit buffers for a serial communication controller are not affected in any way by the value programmed into the mrblr. transmit buffers can be individually chosen to have varying lengths. the number of bytes to be transmitted is chosen by programming the data length field in the tx buffer descriptor.
communication processor module 16-186 mpc823e reference manual motorola sccs communication 16 processor module ? rbptrthe receiver buffer descriptor pointer for each sccx channel points to the next buffer descriptor the receiver transfers data to when it is in idle state or to the current buffer descriptor during frame processing. after a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the rbase register. although you will not usually need to write the rbptr in most applications, you can modify it when the receiver is disabled or when you are sure no receive buffer is currently being used. ? tbptrthe transmitter buffer descriptor pointer for each sccx channel points to the next buffer descriptor the transmitter transfers data from when it is in idle state or to the current buffer descriptor during frame transmission. after a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the tbase register. although you will not usually need to write tbptr in most applications, you can modify it when the receiver is disabled or when you are sure no receive buffer is currently being used. ? other general parametersyou do not need to access these parameters during normal operation. they are only listed because they provide helpful information for experienced users and for debugging purposes. additional parameters are listed in table 16-24. rptr and tptr are updated by the sdma channels to show the next address in the buffer to be accessed. tcnt is a down-count value that is initialized with the tx buffer descriptors data length and decremented with every byte read by the sdma channels. rcnt is a down-count value that is initialized with the mrblr value and decremented with every byte written by the sdma channels. rstate, tstate, rtmp, ttmp, and reserved areas must only be used by the risc microcontroller. note: mrblr is not intended to be dynamically changed while a serial communication controller is operating. however, if it is modified in a single bus cycle with one 16-bit move, then a dynamic change in the receive buffer length can be successfully achieved. this occurs when the communication processor module moves control to the next rx buffer descriptor in the table. thus, a change to mrblr does not have an immediate effect. to guarantee the exact rx buffer descriptor on which the change occurs, you must only change the mrblr while the sccx receiver is disabled. the value of mrblr must be greater than zero for all modes. for ethernet and hdlc mode, the mrblr must be evenly divisible by 4. in transparent mode, the mrblr must also be divisible by 4, unless the rfw bit of the gsmr_h is set to 8 bits. note: to extract data from a partially full receive buffer, issue the close rx bd command.
communication processor module motorola mpc823e reference manual 16-187 sccs communication 16 processor module 16.9.8 handling interrupts in the sccs interrupt handling for the sccx channel is configured on a global basis in the cpm interrupt pending register, cpm interrupt mask register, and cpm in-service register. in each of these registers, a bit is used to mask, enable, or report the presence of an interrupt from sccx. the interrupt priority between the serial communication controllers is programmable in the cpm interrupt configuration register. interrupts are handled by the scc event register in each protocol. a number of events can cause a serial communication controller to interrupt the processor and these events differ slightly depending on the protocol you have selected. these events are handled independently by the scc event and mask registers. events that can cause interrupts related to the ctsx and cdx modem lines are described in section 16.14.8 port c pin functionality . 16.9.8.1 interrupt handling in the scc event register. the 16-bit memory- mapped scc event (scce) register is used to report events recognized by a serial communication controller. when an event is recognized, the serial communication controller sets the corresponding bit in the scce, regardless of the corresponding mask bit. since each protocol has specific requirements, the protocol-specific mode register (psmr) is different for each implementation. 16.9.8.2 interrupt handling in the scc mask register. the 16-bit, read/write scc mask (sccm) register allows you to enable or disable interrupt generation using the communication processor module for specific events in each sccx channel. an interrupt is only generated if the sccx interrupts in this channel are enabled in the cpm interrupt mask register (cimr). if a bit in the sccm register is zero, the communication processor module does not proceed with its usual interrupt handling whenever that event occurs. anytime a bit in the sccm register is set, a 1 in the corresponding bit in the scce register sets the sccx bit in the cpm interrupt pending register (cipr), which is described in section 16.15 the cpm interrupt controller . the bit format of the sccm register is identical to that of the scce. since every sccx protocol has specific requirements, the sccm bits are different for each protocol. 16.9.8.3 interrupt handling in the scc status register. the 8-bit, read/ write scc status (sccs) register allows you to monitor real-time status conditions on the rxdx signal. it does not show the real-time status of the ctsx and cdx pins. their real- time status is available in the port c parallel i/o. since every sccx protocol has specific requirements, the sccs bits are different for each protocol.
communication processor module 16-188 mpc823e reference manual motorola sccs communication 16 processor module 16.9.9 initializing the serial communication controllers the serial communication controllers require that a number of registers and parameters be configured after power-on reset. to initialize scc2, regardless of the protocol you are using, follow these steps: 1. set the parallel i/o ports to configure and connect the i/o pins to the scc2. 2. initialize the raid field of the sdcr with the appropriate arbitration id. 3. set the port c registers to configure the ctsx and cdx pins to be in parallel i/o with interrupt capability or to be direct connections to the scc2 (if modem support is needed). 4. if the time-slot assigner is used, you must configure the serial interface. if the scc2 is in nmsi mode, the sicr must still be initialized. 5. set the gsmr_h and gsmr_l, but do not write the ent or enr bits yet. 6. set the psmr. 7. set the dsr. 8. initialize the required values for the scc2 in its parameter ram. 9. clear any current events in the scce register (optional). 10. set the sccm register to enable the interrupts in the scce register. 11. set the cicr to configure the scc2 interrupt priority. 12. clear any current interrupts in the cipr (optional). 13. set the cimr to enable interrupts to the cpm interrupt controller. 14. set the ent and enr bits in the gsmr_l. the buffer descriptors can have their r or e bits set at any time. notice that the cpcr does not need to be accessed after a power-on reset. a serial communication controller must be disabled and reenabled after any dynamic change in its parallel i/o ports or serial channel physical interface configuration. you can also use the rst bit in the cpcr (described in section 16.2.6.1 cpm command register ) for a comprehensive reset. follow these steps to handle an interrupt in the serial communication controllers: 1. once an interrupt occurs, read the scce register to locate the source of the interrupt. the scce bits to be handled in this interrupt handler are normally cleared at this time by writing ones to them. 2. process the tx buffer descriptors to reuse them if the tx or txe bit was set in the scce register. if the transmit speed is fast or the interrupt delay is long, more than one transmit buffer may have been sent by a serial communication controller. thus, it is important to check more than just one tx buffer descriptor during interrupt handling. one common practice is to process all tx buffer descriptors in the interrupt handler until one is found with its r bit set. 3. extract data from the rx buffer descriptor if the rx, rxb, or rxf bit is set in the scce register. if the receive speed is fast or the interrupt delay is long, more than one
communication processor module motorola mpc823e reference manual 16-189 sccs communication 16 processor module receive buffer may have been received by a serial communication controller. thus, it is important to check more than just one rx buffer descriptor during interrupt handling. one common practice is to process all rx buffer descriptors in the interrupt handler until one is found with its e bit set. 4. reset the status bit in the buffer descriptors control and status field that is associated with the interrupt. these bits do not reset after each i/o operation. 5. clear the sccx bit in the cisr. 6. execute the rfi instruction. 16.9.10 controlling sccx timing when the diag field of the gsmr_l is programmed for normal operation, the cdx and ctsx signals are automatically controlled by the serial communication controllers. the tci bit of the gsmr_l must also be programmed for normal operation. 16.9.10.1 synchronous protocols. in synchronous protocols, the rtsx pin is asserted when sccx data is loaded into the transmit fifo and a falling transmit clock occurs. at this point, the serial communication controller starts transmitting data once the appropriate conditions occur on the ctsx pin. in all cases, the first bit of data is the start of the opening flag, sync pattern, or preamble. figure 16-66 illustrates that the delay between the rtsx pin and data is 0 bit times, regardless of how the ctss bit is set in the gsmr_h. this operation assumes that the ctsx pin is already asserted to a serial communication controller or that the ctsx pin is reprogrammed to be a parallel i/o line, in which case, the ctsx signal to the serial communication controller is always asserted. the rtsx pin is negated one clock after the last bit in the frame. figure 16-66. rtsx output delays asserted for synchronous protocols txdx rtsx ctsx first bit of frame data (input) tclk (output) (output) note: a frame includes opening and closing flags and syncs, if present in the protocol. last bit of frame data
communication processor module 16-190 mpc823e reference manual motorola sccs communication 16 processor module if the ctsx pin is not already asserted when the rtsx pin is asserted, then the delays to the first bit of data depend on when ctsx is asserted. figure 16-67 illustrates that the delay between ctsx and the data can be approximately 0.5- to 1-bit time or 0-bit times, depending on how the ctss bit is set in the gsmr_h. figure 16-67. ctsx output delays asserted for synchronous protocols txdx rtsx ctsx first bit of frame data last bit of frame data (input) tclk (output) (output) note: ctss is set to 1 in the gsmr. ctsp is a "don't care". txdx rtsx ctsx first bit of frame data last bit of frame data (input) tclk (output) (output) note: ctss is set to 0 in the gsmr. ctsp is a "don't care". cts sampled low here
communication processor module motorola mpc823e reference manual 16-191 sccs communication 16 processor module if the ctsx pin is programmed to envelope the data, it must remain asserted during frame transmission or a ctsx lost error occurs. negation of the ctsx pin forces the rtsx pin high and the transmit data to an idle state. if the ctss bit in the gsmr_h is zero, the ctsx pin must be sampled by a serial communication controller before a ctsx lost is recognized. otherwise, the negation of ctsx immediately causes the ctsx lost condition. refer to figure 16-68 for details. figure 16-68. ctsx lost in synchronous protocols note: if the ctss bit in the gsmr_h is set, all ctsx transitions must occur while the transmit clock is low. txdx rtsx ctsx first bit of frame data (input) tclk (output) (output) note: ctss is set to 1 in the gsmr. ctsp is set to 0 or no cts lost can occur. txdx rtsx ctsx first bit of frame data (input) tclk (output) (output) ctsx sampled low here ctsx sampled high here rtsx forced high data forced high cts lost signaled in frame bd cts lost signaled in frame bd data forced high note: ctss is set to 1 in the gsmr. ctsp is set to 0 or no cts lost can occur. rtsx forced high
communication processor module 16-192 mpc823e reference manual motorola sccs communication 16 processor module reception delays are determined by the cdx pin as illustrated in figure 16-69. if the cds bit in the gsmr_h is zero, then the cdx pin is sampled on the rising receive clock edge prior to data being received. if the cds bit in the gsmr_h is 1, then the cdx pin transitions cause data to be immediately gated into the receiver. if the cdx pin is programmed to envelope the data, it must remain asserted during frame transmission or a cdx lost error occurs. negation of the cdx pin terminates reception. if the cds bit in the gsmr_h is zero, the cdx pin must be sampled by a serial communication controller before a cdx lost error is recognized. otherwise, the negation of cdx immediately causes the cdx lost condition to occur. figure 16-69. using cdx to control synchronous protocol reception note: if the cds bit in the gsmr_h is set, all cdx transitions must occur while the receive clock is low. first bit of data in frame last bit of frame data rxdx cdx first bit of frame data last bit of frame data rclk (input) cdx sampled low here (input) cdx sampled high here rclk rxdx (input) cdx (input) cdx assertion immediately gates reception cdx negation immediately halts reception notes: 1. cds is set to 1 in the gsmr and cdp is set to 0. 2. if cdx is negated prior to the last bit of the receive frame, cdx lost is signaled in the frame buffer descriptor. 3. if cdp is set to 1, cdx lost cannot occur and cdx negation has no effect on reception. notes: 1. cds is set to 0 in the gsmr and cdp is set to 0. 2. if cdx is negated prior to the last bit of the receive frame, cdx lost is signaled in the frame buffer descriptor. 3. if cdp is set to 1, cdx lost cannot occur and cdx negation has no effect on reception.
communication processor module motorola mpc823e reference manual 16-193 sccs communication 16 processor module 16.9.10.2 asynchronous protocols. in asynchronous protocols, the rtsx pin is asserted when sccx data is loaded into the transmit fifo and a falling transmit clock occurs. the cdx and ctsx pins can be used to control reception and transmission in the same manner as the synchronous protocols. the first bit of data transmission in an asynchronous protocol is the start bit of the first character. in addition, the uart protocol has an option for ctsx flow control as described in section 16.9.15 the sccs in uart mode . if ctsx is already asserted when rtsx is asserted, transmission begins in two additional bit times. however, if ctsx is not already asserted when rtsx is asserted and the ctss bit is set to 0 in the gsmr_h, then transmission begins in three additional bit times. if ctsx is not already asserted when rtsx is asserted and ctss is set to 1, then transmission begins in two additional bit times. 16.9.11 digital phase-locked loop operation each sccx channel includes a digital phase-locked loop (dpll) that is used to recover clock information from a received datastream. for applications that provide a direct clock source to the serial communication controllers, the dpll can be bypassed if it is programmed to do so in the gsmr_l. the dpll must not be used when a serial communication controller is programmed to ethernet and it is optional for other protocols. the dpll receiver block diagram is illustrated in figure 16-70 and the transmitter block diagram is illustrated in figure 16-71. the dpll can be driven by an external clock or one of the baud rate generator outputs and they must be approximately 8x, 16x , or 32x the data rate, depending on the encoding or decoding preferred. the dpll uses this clock, along with the datastream, to construct a data clock that can be used as the scc2 receive and/or transmit clock. in all modes, the dpll uses the input clock to determine the nominal bit time. at the beginning of operation, the dpll is in search mode, whereas the first transition resets the internal dpll counter and begins dpll operation. while the counter is counting, the dpll monitors the incoming datastream for transitions and when a transition is detected, the dpll makes a count adjustment to produce an output clock that tracks the incoming bits.
communication processor module 16-194 mpc823e reference manual motorola sccs communication 16 processor module figure 16-70. dpll receiver block diagram figure 16-71. dpll transmitter block diagram 0 1 s x1 mode rclk hsrclk 0 1 s x1 mode sccrdata carrier snc noise hunting renc rdcr dpll receiver edge tsnc rinv rxdx rxdx rinv renc nrzi hsrclk d q ck decoded data hsrclk 0 1 s x1 mode tclk hstclk hstclk txen hstclk txdx 0 1 s x1 mode 0 1 s tenc = nrzi scct data tinv tenc tdcr tend hstclk dpll transmitter d q ck dq ck encoded data
communication processor module motorola mpc823e reference manual 16-195 sccs communication 16 processor module the dpll has a carrier-sense signal that indicates when there are data transfers on the rxdx signal. using the tsnc field of the gsmr_l, this signal is asserted as soon as a transition is detected on rxdx and it is negated after a programmable number of clocks have been detected with no transitions. to prevent itself from locking on the wrong edges and to provide fast synchronization, the dpll must receive a preamble pattern before it receives the data. in some protocols, the preceding flags or syncs are used. however, some protocols require a special pattern, such as alternating ones and zeros. when a transmission occurs, a serial communication controller can generate preamble patterns as programmed in the tpp and tpl bits of the gsmr_l. in addition, the dpll can be used to invert the datastream of a reception or transmission. this feature is available in all encodings, including the standard nrz data format. also, when the transmitter is idle, the dpll can either force the txdx signal to a high voltage or continue encoding the data supplied to it. the dpll is used for uart encoding/decoding, which gives you the option of selecting the divide ratio in the uart decoding process (8x, 16x, or 32x). typically, 16x option is used. the maximum data rate that can be supported with the dpll is 3.125mhz when operating with a 25mhz system clock, assuming that the 8 option is chosen (25mhz ? 8 = 3.125mhz). thus, the frequency applied to the clkx pin or generated by an internal baud rate generator may be up to 25mhz on a 25mhz mpc823e, if the dpll 8x, 16x, or 32x options are used. table 16-25. preamble patterns for decoding methods decoding method preamble pattern maximum preamble length required nrzi mark all zeros 8-bit nrzi space all ones 8-bit fm0 all ones 8-bit fm1 all zeros 8-bit manchester repeating 10s 8-bit differential manchester all ones 8-bit note: the 1:2 ratio of gclk1 to the serial clock does not apply when the dpll is used to recover the clock in the 8x, 16x, or 32x modes. synchronization occurs internally after the receive clock is generated by the dpll. therefore, even the fastest dpll clock generation (the 8x option) easily meets the required 1:2 ratio clocking limit.
communication processor module 16-196 mpc823e reference manual motorola sccs communication 16 processor module 16.9.11.1 encoding and decoding data with a dpll. each serial communication controller contains a digital phase-locked loop unit that can be programmed to encode and decode sccx data as nrz, nrzi mark, nrzi space, fm0, fm1, manchester, and differential manchester. examples of the different encoding methods are illustrated in figure 16-72. if you do not want to use the dpll, you can choose nrz coding in the renc and tenc bits of the gsmr_l. the coding is defined as follows: ? nrza one is represented by a high level for the duration of the bit and a zero is represented by a low level. ? nrzi marka one is represented by no transition at all. a zero is represented by a transition at the beginning of the bit (the level present in the preceding bit is reversed). ? nrzi spacea one is represented by a transition at the beginning of the bit (the level present in the preceding bit is reversed). a zero is represented by no transition at all. ? fm0a one is represented by a transition only at the beginning of the bit. a zero is represented by a transition at the beginning of the bit and another transition at the center of the bit. ? fm1a one is represented by a transition at the beginning of the bit and another transition at the center of the bit. a zero is represented by a transition only at the beginning of the bit. figure 16-72. dpll encoding examples nrz nrzi mark fm0 fm1 manchester 011001 data differential nrzi space manchester
communication processor module motorola mpc823e reference manual 16-197 sccs communication 16 processor module ? manchestera one is represented by a high to low transition at the center of the bit. a zero is represented by a low to high transition at the center of the bit. in both cases there may be a transition at the beginning of the bit to set up the level required to make the correct center transition. ? differential manchestera one is represented by a transition at the center of the bit with the opposite direction from the transition at the center of the preceding bit. a zero is represented by a transition at the center of the bit with the same polarity from the transition at the center of the preceding bit. 16.9.12 clock glitches a clock glitch occurs when an input clock signal transitions between a one and zero state two times, in a time period small enough to violate the minimum high or low time specification of the input clock. they also occur when excessive noise is present on a slowly rising or falling signal. this can be a potential problem for many communication systems. not only can glitched clocks cause systems to experience errors, but they can also cause undetected errors. systems that supply an external clock to a serial channel are often susceptible to glitches caused by noise, connecting or disconnecting the physical cable from the application board, or excessive ringing on a clock line. the serial communication controllers have special circuits designed to detect glitches that occur within the system. glitches that could cause a serial communication controller to transition to the wrong state. this status information can be used to alert the system of a problem at the physical layer. the glitch detect circuit is not a specification test, so if you develop a circuit that does not meet the input clocking specifications for a serial communication controller, erroneous data can be received or transmitted that is not indicated by the glitch detection logic. conversely, if a glitch indication is signaled, it does not guarantee that erroneous data was received or transmitted. regardless of whether the dpll is used, the received clock is passed through a noise filter that eliminates any noise spikes that affect a single sample. this sampling is enabled using the gde bit of the gsmr_h. if a spike is detected, a maskable receive or transmit glitched clock interrupt is generated in the event register of the sccx channel. although you can either reset the sccx receiver or transmitter or continue operation, the statistics on clock glitches must be kept for later evaluation. the glitch status indication can also be used as a debugging aid during the early phases of prototype testing.
communication processor module 16-198 mpc823e reference manual motorola sccs communication 16 processor module 16.9.13 dpll and serial infrared encoder/decoder irda is a family of specifications intended to facilitate the interconnection of computers and peripherals using a directed half-duplex serial infrared physical communications medium. the infrared data association (irda) physical layer standard version 1.1 specifies three modes of operation, each one with a distinct modulation scheme and signaling rate. ? low speed mode2.4kb/s to 115.2kb/s ? middle speed mode0.576 mb/s or 1.152 mb/s ? high speed mode4 mb/s figure 16-73 illustrates how to implement a general infrared link with the mpc823e using an scc, irda encoder/decoder module, and external irda transducer module. the irda dpll is driven by one of the baud rate generator outputs or by an external clock called a high-speed receive/transmit clock (hsrclk/hstclk) that is used as a reference clock for the irda dpll. in low- and middle-speed modes, the hsrclk and hstclk frequency must be 16x the serial frequency. in high-speed mode, the ratio between the hsrclk/hstclk frequency and the serial frequency depends on the irda dpll mode, which is currently 12x the serial frequency. therefore, for high-speed mode irda operation from an external clock, a 48mhz frequency must be provided. it you are using a source for hsrclk and hstclk, the minimum system frequency must be 48mhz. see section 16.9.20.5 programming model for more information. mpc823e figure 16-73. serial irda link ir transmit encoder ir receive decoder encoder/ decoder module ir transducer module output driver&led detector & receiver ir out ir in sccx txdx rxdx
communication processor module motorola mpc823e reference manual 16-199 sccs communication 16 processor module 16.9.14 disabling the sccs on-the-fly if you are not using the serial communication controllers, you can disable them and reenable them later by following a sequence of steps to ensure that any buffers currently in use are properly closed and that new data is transferred to or from a new buffer. you must follow this sequence if you are changing a parameter that cannot be dynamically changed. parameters that are dynamic can be changed immediately. for instance, the internal baud rate generators allow on-the-fly changes, but the dpll-related bits in the gsmr_l do not. 16.9.14.1 disabling the entire sccx transmitter. the sccx transmitter can be fully disabled or enabled by following these steps: 1. issue the stop transmit command to the cpcr if a serial communication controller is currently transmitting data. it must stop smoothly. if a serial communication controller is not transmitting, then you do not need the stop transmit command. furthermore, if you overwrite the tbptr or execute the init tx parameters command, the stop transmit command is not required. 2. clear the ent bit in the gsmr_l to disable the sccx transmitter and put it in a reset state. 3. make modifications to the sccx transmit parameters or to the parameter ram. if you want to switch protocols or restore the sccx transmit parameters to their initial state, issue the init tx parameters command to the cpcr. 4. issue the restart transmit command to the cpcr. this command is required if the init tx parameters command was not issued in step 3. 5. set the ent bit in the gsmr_l. transmission begins using the tx buffer descriptor that the tbptr points to as soon as the r bit is set in the tx buffer descriptor. 16.9.14.2 disabling part of the sccx transmitter. to reinitialize the sccx transmitter to the state it was in after reset, follow this short sequence of steps: 1. clear the ent bit in the gsmr_l. 2. issue the init tx parameters command and make any additional modifications. 3. set the ent bit in the gsmr_l. note: modifying parameter ram does not require that you fully disable the serial communication controllers. refer to the parameter ram description for details about modifying the parameter ram values. if you prefer to disable the usb, sccs, smcs, spi, and i 2 c, use the cpcr (described in section 16.2.6.1 cpm command register ) to reset the entire communication processor module with a single command.
communication processor module 16-200 mpc823e reference manual motorola sccs communication 16 processor module 16.9.14.3 disabling the entire sccx receiver. the sccx receiver can be fully disabled or enabled by following these steps: 1. clear the enr bit in the gsmr_l to disable the sccx receiver and put it in a reset state. 2. make modifications to the sccx receive parameters or to the parameter ram. if you want to switch protocols or restore the sccx receive parameters to their initial state, issue the init rx parameters command. 3. issue the enter hunt mode command in the cpcr. this command is required if the init rx parameters command was not issued in step 2. 4. set the enr bit in the gsmr_l. reception begins using the rx buffer descriptor that the rbptr points to if the e bit is set in the tx buffer descriptor. 16.9.14.4 disabling part of the sccx receiver. to reinitialize the sccx receiver to the state it was in after reset, follow this short sequence of steps: 1. clear the enr bit in the gsmr_l. 2. issue the init rx parameters command in the cpcr and make any additional modifications. 3. set the enr bit in the gsmr_l. 16.9.14.5 switching protocols. sometimes you may want to switch the protocol that a serial communication controller is executing without resetting the board. you can use one command and the following sequence of steps: 1. clear the ent and enr bits in the gsmr_l. 2. issue the init tx and rx params command in the cpcr. this command initializes both the transmit and receive parameters. any additional modifications can be made in the gsmr_l. 3. set the ent and enr bits in the gsmr_l and the serial communication controller is enabled with the new protocol. tip: you can save power by clearing the ent and enr bits of the serial communication controllers.
communication processor module motorola mpc823e reference manual 16-201 sccs communication 16 processor module 16.9.15 the sccs in uart mode many applications need a simple method of sending low-speed data between pieces of equipment. the universal asynchronous receiver transmitter (uart) protocol is the de-facto standard for such communication. the term asynchronous is used because it is not necessary to send clocking information along with the data being sent. uart links are character-oriented. asynchronous links are used to connect terminals and other computer equipment together. even in applications where synchronous communication is required, the uart is often used for a local debugging port to run board debugger software. the character format of the uart protocol is illustrated in figure 16-74. since the transmitter and receiver operate asynchronously, there is no need to connect the transmit and receive clocks. instead, the receiver oversamples the incoming datastream (usually by a factor of 16) and uses some of these samples to determine the bit value. traditionally, the middle three samples of the 16 samples are used. two uarts can communicate using a system like this if parameters, such as the parity scheme and character length, are the same for both the transmitter and receiver. when data is not transmitted in the uart protocol, a continuous stream of ones (called the idle condition) is transmitted. since the start bit is always a zero, the receiver can detect when real data is once again present on the line. uart specifies an all-zeros character called a break, which is used to abort a character transfer sequence. many different protocols have been defined using asynchronous characters, but the most popular of these is the rs-232 standard, which specifies baud rates, handshaking protocols, and mechanical/electrical details. another popular standard using the same character format is rs-485, which defines a balanced line system allowing longer cables than rs-232 links. synchronous protocols are sometimes defined to run over asynchronous links. other protocols like profibus extend the uart protocol to include lan-oriented features such as token passing. figure 16-74. uart character format uart txdx uart tclk 8x, 16x, or 32x start bit 5, 6, 7, or 8 data bits with the least-significant bit first addr bit par bit optional 9/16 to 2 stop bits (clock not to scale)
communication processor module 16-202 mpc823e reference manual motorola sccs communication 16 processor module all the standards provide handshaking signals, but some systems require just three physical linestransmit data, receive data, and ground. many proprietary standards have been built around the asynchronous character frame and some even implement a multidrop configuration. in multidrop systems, more than two stations can be present on a network, each one with a specific address. frames made up of many characters can be broadcast with the first character acting as a destination address. to accommodate this standard, the uart frame is extended one bit to distinguish between an address character and the normal data characters. additionally, a synchronous form of the uart protocol exists where start and stop bits are still present, but because a clock is provided with each bit the oversampling technique is not required. this mode is called isochronous operation or synchronous uart. by appropriately setting the gsmr_l, the sccx channel can be configured to function in uart mode, which provides standard serial i/o using asynchronous character-oriented (start-stop) protocols with rs-232 c-type lines. the sccx in uart mode, also called the sccx uart controller, can be used to communicate with any existing rs-232 type of device and to provide a port for serial communication to other microprocessors and terminals (either locally or via modems). it includes facilities for communication using standard asynchronous bit rates and protocols. the sccx in uart mode supports a multidrop mode for master/slave operation with wake-up capability on both the idle signal and address bit. this mode also supports a synchronous mode of operation in which a clock must be provided with each bit that is received. it transmits data from memory (either internal or external) to the txdx signal and receives data from the rxdx signal into memory. in synchronous uart mode, the clock must also be supplied and it can be generated internally or externally. modem lines are supported via the port b and c pins. the sccx in uart mode consists of separate transmit and receive sections whose operations are asynchronous with the core. 16.9.15.1 features the following list summarizes the main features of the sccx in uart mode: ? flexible message-oriented data structure ? implements synchronous and asynchronous uart ? multidrop operation ? receiver wake-up on idle line or address mode ? eight control character comparisons ? two address comparisons ? maintenance of four 16-bit error counters ? received break character length indication ? programmable data length (5C8 bits) ? programmable 1 to 2 stop bits in transmission ? capable of reception without a stop bit ? programmable fractional stop bit length
communication processor module motorola mpc823e reference manual 16-203 sccs communication 16 processor module ? even, odd, force, or no parity generation ? even, odd, force, or no parity check ? frame error, noise error, break, and idle detection ? transmit preamble and break sequences ? freeze transmission option with low-latency stop 16.9.15.2 normal asynchronous mode. in normal asynchronous mode, the receive shift register receives the incoming data on the rxdx pin. the control bits in the psmrCscc uart register define the length and format of the uart character and each bit is received in the following order: 1. start bit 2. 5C8 data bits (lsb first) 3. address/data bit (optional) 4. parity bit (optional) 5. stop bits the receiver uses a clock 8x, 16x, or 32x faster than the baud rate and samples each bit of the incoming data three times around its center. the value of the bit is determined by the majority of those samples and if they do not all agree, a noise indication counter is incremented. when a complete byte has been clocked in, the contents of the shift register are transferred to a uart receive data buffer. if there is an error in this character, the appropriate error bits are set by the communication processor module. the sccx uart controller can receive fractional stop bits. the next characters start bit can begin any time after the three middle samples are taken. the uart transmit shift register transmits the outgoing data on the txdx pin. data is then synchronously clocked with the transmit clock, which may have either an internal or external source. the bit transmission order is lsb first, but only the data portion of the uart frame is actually stored in the data buffers. the start and stop bits are always generated and stripped by the sccx uart controller. the parity bit can also be generated in transmission and checked during reception and although it is not stored in the data buffer, its value can be inferred from the reporting mechanism of the data buffer. similarly, the optional address bit is not stored in the transmit or receive data buffer, but is implied from the buffer descriptor itself. parity is generated and checked for the address bit. the rfw bit of the gsmr_h must be set for an 8-bit receive fifo. 16.9.15.3 synchronous mode. in synchronous mode, the sccx uart controller uses a 1x data clock for timing. the receive shift register receives the incoming data on the rxdx pin synchronously to the clock. the length and format of the serial word in bits are defined by the control bits in the psmrCscc uart register in the same way they are defined in asynchronous mode. when a complete byte has been clocked in, the contents of the shift register are transferred to a uart receive data buffer. if there is an error in this character, then the appropriate error bits are set by the communication processor module.
communication processor module 16-204 mpc823e reference manual motorola sccs communication 16 processor module the uart transmit shift register transmits the outgoing data on the txdx pin. data is then clocked synchronously with the transmit clock, which can have an internal or external source. the rfw bit in the gsmr_h must be set for an 8-bit receive fifo. 16.9.15.4 sccx uart parameter ram memory map. when configured to operate in uart mode, the serial communication controllers overlay the structure used in table 16-24 with the uart-specific parameters described in table 16-26. table 16-26. sccx uart parameter ram memory map address name width description sccx base + 30 res word reserved sccx base + 34 res word reserved sccx base + 38 max_idl half-word maximum idle characters sccx base + 3a idlc half-word temporary idle counter sccx base + 3c brkcr half-word break count register (transmit) sccx base + 3e parec half-word receive parity error counter sccx base + 40 frmec half-word receive framing error counter sccx base + 42 nosec half-word receive noise counter sccx base + 44 brkec half-word receive break condition counter sccx base + 46 brkln half-word last received break length sccx base + 48 uaddr1 half-word uart address character 1 sccx base + 4a uaddr2 half-word uart address character 2 sccx base + 4c rtemp half-word temp storage sccx base + 4e toseq half-word transmit out-of-sequence character sccx base + 50 character1 half-word control character 1 sccx base + 52 character2 half-word control character 2 sccx base + 54 character3 half-word control character 3 sccx base + 56 character4 half-word control character 4 sccx base + 58 character5 half-word control character 5 sccx base + 5a character6 half-word control character 6 sccx base + 5c character7 half-word control character 7 sccx base + 5e character8 half-word control character 8 sccx base + 60 rccm half-word receive control character mask sccx base + 62 rccrp half-word receive control character register sccx base + 64 rlbc half-word receive last break character note: you are only responsible for initializing the items in bold. sccx base = (immr & 0xffff0000) + 0x3d00 (scc2) and 0x3e00 (scc3). all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register.
communication processor module motorola mpc823e reference manual 16-205 sccs communication 16 processor module ? max_idlonce a character is received, the sccx uart controller begins counting any idle characters that are received. if a max_idl number of idle characters is received before the next data character, an idle timeout occurs and the buffer is closed. this, in turn, can produce an interrupt request to the core to receive the data from the buffer. thus, max_idl provides a convenient way to demarcate frames in uart mode. to disable the max_idl feature, simply program it to 0x0000. an idle character is calculated the following number of bit times: 1 + data length (5, 6, 7, or 8) + 1 (if parity bit is used) + number of stop bits (1 or 2). for example, for 8 data bits, no parity, and 1 stop bit, the character length is 10 bits. ? idlcthe risc microcontroller uses this value to store the current idle counter value in the max_idl timeout process. idlc is a down-counter and you do not need to initialize or access it. ? brkcrthe sccx uart controller sends a break character sequence whenever a stop transmit command is issued to the cpcr. the number of break characters sent by the sccx uart controller is determined by the value in brkcr. for 8 data bits, no parity, 1 stop bit, and 1 start bit, each break character is 10 bits long and consists of all zeros. ? parec, frmec, nosec, and brkecyou must initialize these 16-bit (moduloC2 16 ) counters. when the following conditions occur, they are incremented by the risc microcontroller. o parec counts received parity errors. o frmec counts received characters with framing errors. o nosec counts received characters with noise errors. o brkec counts the number of break conditions that occur on the receivepin. notice that one break condition can last for hundreds of bit times, yet this counter is incremented only once during that period. ? brklnthis value is used to store the length of the last break character that is received and is as long as the break. for example, if the receive pin is low for 20 bit times, brkln shows the value 0x0010. brkln is accurate to within one character unit of bits. for 8 data bits, no parity, 1 stop bit, and 1 start bit, brkln is accurate to within 10 bits. ? uaddr1, uaddr2in multidrop mode, the sccx uart controller provides automatic address recognition for two addresses. in this case, you program the lower order bytes of uaddr1 and uaddr2 with the two preferred addresses. ? toseqthis value is used to transmit out-of-sequence characters in the transmit stream. using this field, the preferred characters can be inserted into the transmit fifo without affecting any transmit buffer that might currently be in progress. ? character1 to character 8these characters define the receive control characters on which interrupts can be generated. ? rccmthis value is used to mask the comparison of the character1 to character 8 parameters so that classes of control characters can be defined. a one enables the bit comparison and a zero masks it.
communication processor module 16-206 mpc823e reference manual motorola sccs communication 16 processor module ? rccrpthis value is used to hold the value of any control character that is not written to the data buffer. ? rlbcthis entry is used in synchronous uart when the rzs bit is set in the psmrCuart and contains the actual pattern of the last break character. by counting the zeros in this entry, the core can measure the break length to a bit resolution. you read rlbc by counting the number of zeros written, starting at bit 15 continuing to the point where the first one was written. therefore, rlbc = 001xxxxxxxxxxxxx (binary) indicates two zeros and rlbc = 1xxxxxxxxxxxxxxx (binary) indicates no zeros. 16.9.15.5 programming the sccx in uart mode. the sccx uart controller uses the same data structure as the other modes and supports multibuffer or multidrop operation. you can program the sccx uart controller to reject messages that are not destined for a programmable address (multidrop mode). you can also program the sccx uart controller to accept or reject control characters. if a control character is rejected, an interrupt can be generated. the receive character can be accepted using a receive character mask value. the sccx uart controller enables you to transmit break and preamble sequences. overrun, parity, noise, and framing errors are reported via the buffer descriptor table and/or error counters. an indication of the signal line status is reported in the status register and a maskable interrupt is generated when the status changes. in its simplest form, the sccx uart controller functions in a character-oriented environment, in which each character is transmitted with the stop bits and parity and received into separate 1-byte buffers. a maskable interrupt is generated when a buffer is received. using linked buffers, many applications try to take advantage of the message-oriented capabilities that the serial communication controllers support in uart mode. data is handled in a message-oriented environment, which means that you can work on entire messages rather than operating on a character-by-character basis. also, a message can span several linked buffers. for example, before handling the input data, a terminal driver may want to wait until you type an end-of-line character rather than be interrupted when a character is received. as another example, when transmitting ascii files, the data can be transferred as messages ending on the end-of-line character. each message could be both transmitted and received as a linked list of buffers without any intervention from the core, which makes it easy to program and saves processor overhead. before reception, you can define up to eight control characters and each control character can be configured to designate the end of a message or generate a maskable interrupt without being stored in the data buffer. the latter option is useful when flow control characters such as xon or xoff need to alert the core but do not belong to the received message.
communication processor module motorola mpc823e reference manual 16-207 sccs communication 16 processor module 16.9.15.6 sccx uart commands. you can program the cpm command register (cpcr) with the following commands to transmit data. ? stop transmit after the hardware or software is reset and a channel is enabled in the psmrCscc uart register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table every eight transmit clocks. this command disables the transmission of characters on the transmit channel and if it is received by the sccx uart controller while a message is transmitting, the message is aborted. the sccx uart controller finishes transmitting data that is already transferred to its fifo and then stops. as shown in section 16.9.7 sccx parameter ram memory map , the tbptr is not incremented. the uart transmitter transmits a programmable number of break sequences and starts transmitting idles. the number of break sequences (which can be zero) must be written to the brkcr before this command is given to the sccx uart controller. ? graceful stop transmit this command is used to stop transmitting smoothly, rather than abruptly. it is similar to the way the stop transmit command finishes. it stops after the current buffer has completed transmission or immediately if there is no buffer being transmitted. the gra bit in the scceCuart register is set once this transmission stops. then the uart transmit parameters, including the buffer descriptors, can be modified. the tbptr points to the next tx buffer descriptor in the table. transmission begins once the r bit of the next buffer descriptor is set and the restart transmit command is issued. ? restart transmit this command enables characters to be transmitted on the transmit channel. the sccx uart controller expects this command after it disables the channel in its psmrCscc uart register, after a stop transmit command, after a graceful stop transmit command, or after a transmitter error. the sccx in uart mode resumes transmission from the current tbptr in the channels tx buffer descriptor table. ? init tx parameters this command initializes all transmit parameters in the serial channels parameter ram to their reset state and must only be issued when the transmitter is disabled. notice that the init tx and rx params command can be used to reset both the transmit and receive parameters. you can program the cpcr with the following commands to receive data. ? enter hunt mode after the hardware or software is reset and a channel is enabled in the psmrCscc uart register (described in section 16.9.15.15 sccx uart mode register ), the channel is in receive enable mode and uses the first buffer descriptor in the table. this command forces the sccx uart controller to close the current rx buffer descriptor if it is being used and enter hunt mode. the sccx uart controller continues receiving the next buffer descriptor if a message is in progress. in the multidrop hunt mode, the sccx uart controller continually scans the input datastream for the address character. when it is not in multidrop mode, it waits for the idle sequence (one character of idle) and does not lose any data that was in the receive fifo when this command was executed.
communication processor module 16-208 mpc823e reference manual motorola sccs communication 16 processor module ? close rx bd this command forces a serial communication controller to close the rx buffer descriptor if it is currently being used and it uses the next buffer descriptor for any subsequently received data. if a serial communication controller is not in the process of receiving data, no action is taken. ? init rx parameters this command initializes all receive parameters in this serial channels parameter ram to their reset state and must only be issued when the receiver is disabled. notice that the init tx and rx params command can be used to reset the receive and transmit parameters. 16.9.15.7 recognizing addresses in sccx uart mode. in multidrop systems, more than two stations can be present on a network and each one can have a specific address. figure 16-75 illustrates two examples of this configuration. frames that consist of many characters can be broadcast as long as the first character is the destination address. to achieve this, the uart frame is extended by one bit to distinguish between an address character and the data characters. the sccx uart controller can be configured to operate in a multidrop environment that supports the following two modes: ? automatic multidrop mode the sccx uart controller automatically checks the incoming address character and accepts the data following it, but only if the address matches one of two preset values. ? manual multidrop mode the sccx uart controller receives all characters. an address character is always written to a new buffer and it can be followed by data characters. the sccx uart controller has two 16-bit address registers that support address recognitionuaddr1 and uaddr2. the upper 8 bits of these registers must be written with zero because only the lower 8 bits are used. in automatic mode, the incoming address is checked against uaddr1 and uaddr2 and when a match is made, the am bit in the buffer descriptor is set to indicate the matched address character and the data following it is written to the data buffers. note: the close rx bd command in the sccx uart controller functions the same as the enter hunt mode command, except for one difference. close rx bd does not need an idle character to be present on the line before it continues receiving. note: for characters less than 8 bits, the most-significant bits must be zero.
communication processor module motorola mpc823e reference manual 16-209 sccs communication 16 processor module 16.9.15.8 sccx uart control characters. the sccx uart controller can recognize special control characters that can be used in a message-oriented environment. you can define a maximum of eight control characters in the control characters table. each character can either be written to the receive buffer or rejected. if it is rejected, the character is written to the received control character register in internal ram and a maskable interrupt is generated. with this method, you know when the control characters (xon or xoff) that are not part of the received messages have arrived. the sccx uart controller uses a table of 16-bit entries to support control character recognition and each entry consists of the control character, a valid bit, and a reject character bit. figure 16-75. two uart multidrop mode configuration examples 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sccx base + 50 e r character1 sccx base + 52 e r character2 sccx base + 54 e r character3 ? ? ? sccx base+ 5e e r character8 sccx base+ 60 1 1 rccm sccx base + 62 rccrp uaddr1 uaddr2 tr tr tr tr 1 2 3 4 t r tr tr tr master slave 1 slave 2 slave 3 two 8-bit addresses can be automatically recognized in either configuration. choose wired-or operation in the port a open-drain register to allow multiple transmit pins to be directly connected. r +v r +v paodr
communication processor module 16-210 mpc823e reference manual motorola sccs communication 16 processor module eend of table in tables with eight control characters, this bit is always zero. 0 = this entry is valid. the lower eight bits are checked against the incoming character. 1 = this entry is invalid and must be the last entry in the control characters table. rreject character 0 = the character is not rejected, but is written into the receive buffer. the buffer is then closed and a new receive buffer is used if there is more data in the message. a maskable interrupt is generated. 1 = if this character is recognized, it is not written to the receive buffer. instead, it is written to the rccrp register and a maskable interrupt is generated. the current buffer is not closed when a control character is received with the r bit set. character1Ccharacter8control character values 1C8 these fields define control characters that will be compared to the incoming character. for characters smaller than 8 bits, the most-significant bit must be zero. rccmreceived control character mask this value is used to mask the comparison of the character1Ccharacter8 fields. the lower eight bits of the rccm correspond to the lower eight bits of character1Ccharacter8 and are decoded as follows: 0 = mask this bit when the incoming character and character1Ccharacter8 fields are compared. 1 = the address comparison on this bit proceeds normally and no masking occurs. rccrpreceived control character register when a control character match is made and the r bit is set, the sccx uart controller writes the control character into the rccrp and generates a maskable interrupt. the core must process the interrupt and read the rccrp before a second control character arrives. if this does not occur, the sccx uart controller overwrites the first control character. note: bits 0 and 1 of the rccm must be set or erratic operation will occur during the control character recognition process.
communication processor module motorola mpc823e reference manual 16-211 sccs communication 16 processor module 16.9.15.9 wake-up timer. by issuing the enter hunt mode command, you can temporarily disable the uart receiver and make it inactive until an idle or address character is recognized, depending on how the um field is set in the psmrCscc uart register. see section 16.9.15.15 sccx uart mode register for more information. if the sccx uart controller is still in the process of receiving a message that you have already decided to discard, you can abort its reception by issuing the enter hunt mode command. when the message is finished, the uart receiver is reenabled by finding the idle line or the address bit of the next message, depending on how the um field is set. when the receiver is in sleep mode and receives a break sequence, it increments the brkec counter and generates an interrupt if the brke or brks bits are enabled in the sccmCuart register. refer section 16.9.15.16 sccx uart receive buffer descriptors for more information about the type of receive interrupt that is registered. 16.9.15.10 break support. the sccx uart controller provides flexible break support to the receiver. transmitting out-of-sequence characters is also supported by the sccx uart controller and is normally used for the transmission of flow control characters like xon or xoff. this procedure is performed using the toseq entry in the sccx uart parameter ram. the sccx uart controller polls the toseq character whenever the transmitter is enabled for uart operation, including during a uart freeze operation, uart buffer transmission, and when no buffer is ready for transmission. toseq is transmitted at a higher priority than the other characters in the transmit buffer, but does not preempt characters already in the transmit fifo. this means that the xon or xoff character may not be transmitted for eight or four character times. to reduce this latency, the tfl bit in the gsmr_h must be set to decrease the fifo size to one character prior to enabling the sccx transmitter. bits 0C1 and 5C6reserved these bits are reserved and must be set to 0. reaready this bit is set by the core when the character is ready for transmission and remains 1 while the character is being transmitted. the communication processor module clears this bit after transmission. toseq bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res rea i ct res a charsend reset 000000 0 r/w r/w r/w r/w r/w r/w r/w r/w addr sccx base + 0x4e
communication processor module 16-212 mpc823e reference manual motorola sccs communication 16 processor module iinterrupt if this bit is set, the character in the charsend field is transmitted. the tx bit is then set in the scceCuart register and the core may be interrupted. ctclear-to-send lost this status bit indicates that the ctsx signal was negated when this character was transmitted. if negation occurs, the ct bit in the uart transmit buffer descriptor is also set. the diag field in the gsmr_l controls whether the ctsx signal is monitored by the serial communication controllers. aaddress 0 = in multidrop mode, the character being sent is a data character. 1 = in multidrop mode, the character being sent is address character. charsendcharacter send this field contains the character to be transmitted. any 5-, 6-, 7-, or 8-bit character value can be transmitted in accordance with the sccx uart configuration. the character is in the least-significant bits of charsend. this value can be modified only while the rea bit is cleared. 16.9.15.11 sending a break. a break is an all-zeros character without a stop bit and you can send it by issuing the stop transmit command. the sccx uart controller finishes transmitting any outstanding data, sends a programmable number of break characters according to the brkcr, and then reverts to idle or sends data if the restart transmit command was given before completion. when the break code is complete, the transmitter sends at least one high bit before transmitting anymore data to guarantee a valid start bit will be recognized. the break characters do not preempt characters already in the transmit fifo, which means that the break character may not be transmitted for eight or four character times. to reduce this latency, set the tfl bit in the gsmr_h so that the fifo size will be reduced to one character before the sccx transmitter is enabled. 16.9.15.12 sending a preamble. a preamble sequence is a convenient way for you to ensure that a line is idle before you start a new message. the preamble sequence length is constructed of consecutive ones of one character length. if the p bit in the uart transmit buffer descriptor is set, the serial communication controller will send a preamble sequence before transmitting that data buffer. for example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones is sent before the first character in the buffer. note: if the ctsx signal is negated during transmission and the communication processor module transmits this character in the middle of a buffer transmission, the ctsx signal could actually have been negated either during this characters transmission or during a buffer characters transmission. in either case, the communication processor module sets the ct bit here and in the tx buffer descriptor status word.
communication processor module motorola mpc823e reference manual 16-213 sccs communication 16 processor module 16.9.15.13 fractional stop bits. you can program the asynchronous uart transmitter to transmit fractional stop bits. using four bits in the sccx uart data synchronization register (dsrCscc uart), you can program the length of the last stop bit to be transmitted. these bits can be modified at any time and if two stop bits are transmitted, only the second one is affected. idle characters are always transmitted as full-length characters. fsbfractional stop bit the value you programmed into the tdcr determines the set of values to use here. when a serial communication controller is in uart mode with 32x oversampling, the fsb field is decoded as follows in the dsrCscc uart. 1111 = last transmitted stop bit 32/32. default value after reset. 1110 = last transmitted stop bit 31/32. 1101 = last transmitted stop bit 30/32. 1100 = last transmitted stop bit 29/32. 1011 = last transmitted stop bit 28/32. 1010 = last transmitted stop bit 27/32. 1001 = last transmitted stop bit 26/32. 1000 = last transmitted stop bit 25/32. 0111 = last transmitted stop bit 24/32. 0110 = last transmitted stop bit 23/32. 0101 = last transmitted stop bit 22/32. 0100 = last transmitted stop bit 21/32. 0011 = last transmitted stop bit 20/32. 0010 = last transmitted stop bit 19/32. 0001 = last transmitted stop bit 18/32. 0000 = last transmitted stop bit 17/32. dsrCscc uart bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field x fsb xxxxxxxxxxx reset 0 1 11001111110 r/w r/w r/w r addr (immr & 0xfff0000) + 0xa2e note: x = dont care.
communication processor module 16-214 mpc823e reference manual motorola communication 16 processor module sccs for 16x oversampling, the fsb field is decoded as follows: 1111 = last transmitted stop bit 16/16. default value after reset. 1110 = last transmitted stop bit 15/16. 1101 = last transmitted stop bit 14/16. 1100 = last transmitted stop bit 13/16. 1011 = last transmitted stop bit 12/16. 1010 = last transmitted stop bit 11/16. 1001 = last transmitted stop bit 10/16. 1000 = last transmitted stop bit 9/16. 0xxx = invalid. do not use. for 8x oversampling, the fsb field is decoded as follows: 1111 = last transmitted stop bit 8/8. default value after reset. 1110 = last transmitted stop bit 7/8. 1101 = last transmitted stop bit 6/8. 1100 = last transmitted stop bit 5/8. 10xx = invalid. do not use. 01xx = invalid. do not use. 00xx = invalid. do not use. the sccx uart receiver can always receive fractional stop bits. the next characters start bit can begin at any time after the three middle samples of the stop bit have been taken. 16.9.15.14 sccx uart controller errors. the sccx uart controller reports character reception and transmission error conditions via the channel buffer descriptors, the error counters, and the scceCuart register. the modem interface lines can be monitored by the port b and c pins. the following transmission error can be detected by the sccx uart controller. ? ctsx lost during character transmission when this error occurs, the channel stops transmission after finishing transmission of the current character from the buffer. the channel then sets the ct bit in the tx buffer descriptor and generates the tx interrupt if it is not masked. the channel resumes transmission after the restart transmit command is issued and the ctsx pin is asserted. note: using the ctsx signal, the sccx uart controller also offers an asynchronous flow control option that does not generate an error. refer to the flc bit description in section 16.9.15.15 sccx uart mode register for information about flow control.
communication processor module motorola mpc823e reference manual 16-215 communication 16 processor module sccs the following reception errors can be detected by the sccx uart controller: ? overrun error this error occurs when data is moved from the receiver fifo to the data buffer after the first byte is received. if a receiver fifo overrun occurs, the channel writes the received character into the internal fifo and over the previously received character. the channel then writes the received character to the buffer, closes it, sets the ov bit in the rx buffer descriptor, and generates the rx interrupt if it is enabled. in automatic multidrop mode, the receiver enters hunt mode immediately. ?cd lost during character reception error if this error occurs and the channel is using this pin to automatically control reception, the channel terminates character reception, closes the buffer, sets the cd bit in the rx buffer descriptor, and generates the rx interrupt if it is enabled. this error has the highest priority. the last character in the buffer is lost and other errors are not checked. in automatic multidrop mode, the receiver enters the hunt mode immediately. ? parity error when a parity error occurs, the channel writes the received character to the buffer, closes the buffer, sets the pr bit in the rx buffer descriptor, and generates the rx interrupt if it is enabled. the channel also increments the parec counter. in automatic multidrop mode, the receiver enters hunt mode immediately. ? noise error the sccx uart controller detects a noise error when three different samples are taken on every bit. when this error occurs, the channel writes the received character to the buffer, proceeds normally, but increments the noise error. ? idle sequence receive error when the sccx uart controller receiver receives all ones in the receive buffer (idle sequence), the channel counts the number of consecutive idle characters that were received. if the count reaches the value programmed into max_idl, the buffer is closed and an rx interrupt is generated. if no receive buffer is open, this event does not generate an interrupt or any status information. the internal idle counter (idlc) is reset every time a character is received. note: a noise error will not occur when the sccx uart controller is in synchronous mode. note: to disable the idle sequence function, set the max_idl value to zero.
communication processor module 16-216 mpc823e reference manual motorola communication 16 processor module sccs ? framing error the sccx uart controller gets this error when it receives a character with no stop bit. all framing errors are reported by the sccx uart controller, regardless of its mode. when this error occurs, the channel writes the received character to the buffer, closes it, sets the fr bit in the rx buffer descriptor, and generates the rx interrupt if it is enabled. the channel also increments frmec. when this error occurs, parity is not checked for this character. in automatic multidrop mode, the receiver immediately enters hunt mode. if the rzs and syn bits are set in the psmrCscc uart register when the sccx uart controller is in synchronous mode, the receiver reports all framing errors, but continues reception if the unexpected zero is really the start bit of the next character. if rzs is set, your software may not consider a reported sccx uart framing error as a true framing error, unless two or more framing errors occur within a short period of time. ? break sequence error the sccx uart controller provides flexible break support to the receiver. when the first break sequence is received, the sccx uart controller increments the brkec and issues the break start event in the scceCuart register, which can generate an interrupt if it is enabled. the sccx uart controller then measures the break length and, when the break sequence is complete, writes the length to the brkln register. after the first one is received, the sccx uart controller also issues the break end event in the scceCuart register, which can generate an interrupt if it is enabled. if the sccx uart controller was in the process of receiving characters when the break was received, it also closes the receive buffer, sets the br bit in the rx buffer descriptor, and writes the rx bit in the scceCuart register, which can generate an interrupt if it is enabled. if the rzs bit is set in the psmrCscc uart register when the sccx uart controller is in synchronous mode, then a break sequence is detected after only two successive break characters are received.
communication processor module motorola mpc823e reference manual 16-217 communication 16 processor module sccs 16.9.15.15 sccx uart mode register. when a serial communication controller is in uart mode, the 16-bit, memory-mapped, read/write protocol-specific mode register is referred to as the sccx uart mode register (psmrCscc uart). since each protocol has specific requirements, the psmr bits are different for each implementation. many of the bits can be modified on-the-fly while the receiver and transmitter are enabled. flcflow control 0 = normal operation. the gsmr_x and port c registers determine the mode of the ctsx pin. 1 = asynchronous flow control. when the ctsx pin is negated, the transmitter stops at the end of the current character. if ctsx is negated past the middle of the current character, the next full character can be sent and transmission is stopped. when ctsx is asserted once more, transmission continues where it left off and no ctsx lost error is reported. no characters except idles are transmitted while ctsx is negated. slstop length this bit selects the number of stop bits transmitted by the sccx uart controller. it can be modified on-the-fly. the receiver is always enabled for one stop bit unless the sccx uart controller is in synchronous mode and the rzs bit is set. fractional stop bits are configured in the general dsr, which is described in section 16.9.4 data synchronization register . 0 = one stop bit. 1 = two stop bits. clcharacter length this field determines the number of data bits in the character, not including the optional parity or multidrop address bits. when you use a character that is less than 8 bits, the most-signifiant bits in memory are written as zeros and they are labeled dont care when they are transmitted. this field can be modified on-the-fly. 00 = 5 data bits. 01 = 6 data bits. 10 = 7 data bits. 11 = 8 data bits. psmrCscc uart bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field flc sl cl um frz rzs syn drt res pen rpm tpm reset 00 0 0 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa28 (scc2 and a48 (scc3)
communication processor module 16-218 mpc823e reference manual motorola communication 16 processor module sccs umuart mode this field selects the protocol that is implemented over the async channel and it can be modified on-the-fly. 00 = normal uart operation. multidrop mode is disabled and an idle-line wake-up is selected. in the idle-line wake-up mode, the uart receiver is reenabled by receiving a character of all ones. 01 = manual multidrop mode. in multidrop mode, an additional address/data bit is transmitted with each character. the multidrop asynchronous modes are compatible with the mc68681 duart, mc68hc11 sci, dsp56000 sci, and intel 8051 serial interface. the uart receiver is reenabled when the last bit received in the character is a one. this means that the received character is an address that has to be processed by all inactive processors. the sccx uart controller receives the address character and writes it to a new buffer. the core then compares the written address with its own address and decides whether to ignore or process the characters. 10 = reserved. 11 = automatic multidrop mode. in this mode, the communication processor module automatically checks the address of the incoming address character using the uaddr1 and uaddr2 parameter ram values and accepts or discards the data that follows the address. frzfreeze transmission this bit allows you to stop the uart transmitter and resume transmission from the same point at a later time. 0 = normal operation. if the sccx uart controller was previously frozen, the uart resumes transmission from the next character in the same buffer that was frozen. 1 = the sccx uart controller completes transmission of any data already transferred to the uart fifo (the number of characters depends on the tfl bit in the gsmr_h) and then freezes. after this bit is reset, transmission proceeds from the next character. rzsreceive zero stop bits this bit configures the uart receiver to receive data without any stop bits. this configuration is useful in v.14 applications in which sccx uart controller data is supplied synchronously and all stop bits of a particular character can be omitted for the purpose of cross-network rate adaptation. rzs must only be set if the syn bit is also set. 0 = the receiver operates normally, but at least one stop bit is required between characters. a framing error is issued when there is a missing stop bit and a break status is set if a character with all-zero data bits is received with a zero stop bit. 1 = the receiver continues if a missing stop bit is detected. if the stop bit is a zero, the next bit is considered the first data bit of the next character. a framing error is issued if a stop bit is missing, but a break status is only reported after back-to-back reception of two break characters without stop bits.
communication processor module motorola mpc823e reference manual 16-219 communication 16 processor module sccs synsynchronous mode 0 = normal asynchronous operation. normally, you program the tenc and renc fields in the gsmr_l to nrz and select either 8 , 16 , or 32 in the rdcr and tdcr fields of the gsmr_l. 16 is the recommended value for most applications. 1 = synchronous sccx uart controller using 1 clock. normally, you program the tenc and renc fields in the gsmr_l to nrz and set the rdcr and tdcr fields in the gsmr_l to 1 mode. a 1 bit is transferred with each clock and is synchronous to the clock. as with the other modes, the clock can be provided internally or externally. this mode is sometimes referred to as isochronous uart channel operation. drtdisable receiver while transmitting 0 = normal operation. 1 = while the sccx uart controller is transmitting data, the receiver is disabled. this is useful if the sccx uart controller is configured onto a multidrop line and you do not want to receive your transmission. bit 10reserved this bit is reserved and must be set to 0. penparity enable 0 = no parity. 1 = parity is enabled and determined by the rpm and tpm bits. rpmreceiver parity mode this field selects the type of parity check that the receiver will perform. it can be modified on-the-fly. 00 = odd parity. 01 = low parity. always check for a zero in the parity bit position. 10 = even parity. 11 = high parity. always check for a one in the parity bit position. when odd parity is selected, the transmitter counts the number of ones in the data word. if the total number of ones is not an odd number, the parity bit is set to 1 and produces an odd number. if the receiver counts an even number of ones, an error in transmission has occurred. in the same manner, for even parity, an even number must result from the calculation performed at both ends of the line. in high or low parity (also called mark or space parity), if the parity bit is not high or low, a parity error is reported. note: you must set the p bit in the transmit buffer descriptor if you are using the mpc823e in multidrop uart mode.
communication processor module 16-220 mpc823e reference manual motorola communication 16 processor module sccs tpmtransmitter parity mode this field selects the type of parity that the transmitter performs. it can be modified on-the-fly. 00 = odd parity. 01 = force low parity. always send a zero in the parity bit position. 10 = even parity. 11 = force high parity. always send a one in the parity bit position. 16.9.15.16 sccx uart receive buffer descriptors. on a per-buffer basis, the communication processor module uses the receive (rx) buffer descriptors to report information about the received data. the communication processor module closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following events occur: ? a user-defined control character is received. ? an error occurs during message processing. ? a full receive buffer is detected. ? a max_idl number of consecutive idle characters is received. ? the enter hunt mode command is issued. ? the close rx bd command is issued. an address character is received in multidrop mode and is written to the next buffer for a software comparison. an example of the rx buffer descriptor process is illustrated in figure 16-76. note: the receive parity errors can be ignored, but not disabled. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-221 communication 16 processor module sccs figure 16-76. scc2 uart receive buffer descriptor example mrblr = 8 bytes for scc2 buffer byte 1 byte 2 byte 8 etc. 8 bytes long idle period fourth character has framing error! 5 chars 10 chars characters received by uart time buffer byte 9 byte 10 8 bytes buffer byte 1 byte 2 8 bytes byte 4 has framing error buffer full byte 3 byte 4 error! e length 32-bit buffer pointer receive bd 0 status 0008 pointer 0 e length 32-bit buffer pointer receive bd 1 status 0002 pointer 0 1 id 0 id e length 32-bit buffer pointer receive bd 2 status 0004 pointer 0 id 0 fr 1 e length 32-bit buffer pointer receive bd 3 status xxxx pointer 1 buffer byte 5 8 bytes reception still in progress with this buffer present time idle timeout occurred empty empty additional bytes will be stored unless idle count expires (max_idl)
communication processor module 16-222 mpc823e reference manual motorola communication 16 processor module sccs eempty 0 = the data buffer associated with this rx buffer descriptor has been filled with data or reception has been aborted because of an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor again as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or is currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 9, and 13reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer has been used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table are programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is filled. 1 = the rx bit in the scceCuart register is set when this buffer is completely filled by the communication processor module, indicating the need for the core to process the buffer. the rx bit can cause an interrupt if it is enabled. ccontrol character 0 = this buffer does not contain a control character. 1 = this buffer contains a control character. the last byte in the buffer is one of the user-defined control characters. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi c acm id am res br fr pr res ov cd offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module motorola mpc823e reference manual 16-223 communication 16 processor module sccs aaddress 0 = the buffer only contains data. 1 = when operating in manual multidrop mode, this bit indicates that the first byte of this buffer contains an address byte. the address comparison must be implemented in the software. in automatic multidrop mode, this bit indicates that the buffer descriptor contains a message that was received immediately after an address was recognized in uaddr1 or uaddr2. this address is not written into the receive buffer. cmcontinuous mode 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this buffer descriptor. however, the e bit is cleared if an error occurs during reception, regardless of how the cm bit is set. idbuffer closed on reception of idles this bit indicates that the buffer is closed because a programmable number of consecutive idle sequences (max_idl) was received. amaddress match this bit is only significant if the address bit is set and the automatic multidrop mode is selected in the um field of the psmr-scc uart. after an address match, this bit defines the address character that matched the address character that you defined, which enables the sccx uart controller to receive data. 0 = the address matched the value in uaddr2 of the sccx uart parameter ram. 1 = the address matched the value in uaddr1 of the sccx uart parameter ram. brbreak received this bit indicates that a break sequence has been received at the same time that data is being received into this buffer. frframing error this bit indicates that a character with a framing error has been received and located in the last byte of this buffer. a framing error is a character without a stop bit. a new receive buffer is used to receive more data. prparity error this bit indicates that a character with a parity error has been received and located in the last byte of this buffer. a new receive buffer is used to receive more data. ovoverrun this bit indicates that a receiver overrun has occurred while the sccx uart controller was receiving a message.
communication processor module 16-224 mpc823e reference manual motorola communication 16 processor module sccs cdcarrier detect lost this bit indicates that the carrier detect signal has been negated while the sccx uart controller was receiving a message. data length this field represents the number of octets that the communication processor module writes into this buffer descriptors data buffer. it is written by the communication processor module once the buffer descriptor is closed. rx data buffer pointer this field always points to the first location of the associated data buffer, which can be even or odd. the buffer can reside in internal or external memory. 16.9.15.17 sccx uart transmit buffer descriptor. the communication processor module receives data transmitted on an sccx channel by arranging it in buffers referenced by the channels transmit (tx) buffer descriptor table. using the buffer descriptors, the communication processor module confirms transmission and indicates error conditions so that the processor knows that the buffers have been serviced. note: the actual amount of memory allocated for this buffer must be at least as much as the contents of the mrblr. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res w i cr a cm p ns reserved ct offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-225 communication 16 processor module sccs rready 0 = the data buffer associated with this buffer descriptor is not ready to be transmitted. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered. 1 = the data buffer, which you must prepare for transmission, has not been transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1 and 9C14reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer has been used, the communication processor module will transmit data from the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table are programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the tx bit in the scceCuart register is set when this buffer is serviced by the communication processor module, which can cause an interrupt. crclear-to-send report this bit allows you to have no delay between buffers transmitted in sccx uart mode or a more accurate ctsx lost error report and three bits of idle between buffers. 0 = the buffer following this buffer is transmitted with no delay (assuming it is ready), but the ct bit may not be set in the correct tx buffer descriptor or may not be set at all in a ctsx lost condition. asynchronous flow control, however, continues to function normally. 1 = normal ctsx lost error reporting and three bits of idle occur between back-to-back buffers. aaddress this bit is only valid in multidrop mode. either automatic or manual. 0 = this buffer only contains data. 1 = set by the core, this bit indicates that this buffer contains address characters. all of the buffer data is transmitted as address characters.
communication processor module 16-226 mpc823e reference manual motorola communication 16 processor module sccs cmcontinuous mode 0 = normal operation. 1 = the communication processor module does not clear the r bit after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor. however, the r bit is cleared if an error occurs during transmission, regardless of how the cm bit is set. ppreamble 0 = no preamble sequence is sent. 1 = the sccx uart controller sends one character that consists of all ones before it sends the data so that the other remote receiver can detect an idle line before the data. if this bit is set and the data length of this buffer descriptor is zero, only a preamble is sent. nsno stop bit transmitted 0 = normal operation. stop bits are sent with all characters in this buffer. 1 = by setting the syn bit in the psmrCscc uart register, the data in this buffer is sent without stop bits if the sync mode is selected. if async is selected, the stop bit is transmitted as defined by the fsb field in the general dsr, as described in section 16.9.4 data synchronization register . ctctsx lost the communication processor module writes this bit after it finishes transmitting the associated data buffer. 0 = the ctsx signal remains asserted during transmission. 1 = the ctsx signal is negated during transmission. data length this field represents the number of octets that the communication processor module must transmit from this buffer descriptor data buffer. it is never modified by the communication processor module. normally, this value must be greater than zero. data length can be equal to zero if the p bit set and only a preamble is sent. the communication processor module writes these bits after it finishes transmitting the associated data buffer. tx data buffer pointer this field always points to the first location of the associated data buffer and can be even or odd. the buffer can reside in internal or external memory. the communication processor module writes these bits after it finishes transmitting the associated data buffer.
communication processor module motorola mpc823e reference manual 16-227 communication 16 processor module sccs 16.9.15.18 sccx uart event register. when a serial communication controller is in uart mode, the 16-bit memory-mapped sccx event register is referred to as the sccx uart event register (scceCuart). since each protocol has specific requirements, the scce bits are different for each implementation. this register is used to report events recognized by the uart channel and to generate interrupts. when an event is recognized, the sccx uart controller sets the corresponding bit in the uart event register. interrupts generated by this register can be masked in the sccmCuart register. an example of interrupts that can be generated by the sccx uart controller is illustrated in figure 16-77. figure 16-77. sccx uart interrupt event example line idle 10 characters characters received by uart time rxdx cdx line idle line idle 7 characters ctsx line idle txdx rtsx idl rx cdx cdx rx ccr ctsx ctsx tx break brks notes: 1. the first receive event assumes receive buffers are 6 bytes each. 2. the second idl event occurs after an all-ones character is received. 3. the second rx event position is programmable based on the max_idl value. 4. the brks event occurs after the first break character is received. 5. the cdx event must be programmed in the port c parallel i/o, not in the scc itself. notes: 1. tx event assumes all seven characters were put into a single buffer and cr is set to 1 in the tx buffer descriptor. 2. the ctsx event must be programmed in the port c parallel i/o, not in the scc itself. uart scce events uart scce events characters transmitted by uart idl a receive control character defined not to be stored in the receive buffer. legend: idl idl brke
communication processor module 16-228 mpc823e reference manual motorola communication 16 processor module sccs a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared at reset and can be read at any time. bits 0C2, 5, and 11reserved these bits are reserved and must be set to 0. glrglitch on rx if set, this bit indicates that a serial communication controller has encountered a clock glitch on the receive clock. glrglitch on tx if set, this bit indicates that a serial communication controller has encountered a clock glitch on the transmit clock. abauto baud if set, this bit indicates that an auto baud lock has been detected. the core must rewrite the baud rate generator with the precise divider value for the preferred baud rate. refer to section 16.8.2 baud rate generator configuration registers for more details. idlidle sequence status changed if set, this bit indicates that a change in the serial lines status has been encountered on the uart channel. the real-time status of the line can be read in the sccsCuart. idle is entered when a character of all ones is received and it is exited when a single zero is received. gragraceful stop complete if set, this bit indicates that a graceful stop, which is initiated by the graceful stop transmit command, is complete. this bit is set as soon as the transmitter has finished with any buffer in progress when the command was issued. it is set immediately if no buffer is in progress when the command is issued. brkebreak end if set, this bit indicates that an end-of-break sequence has been found. this indication is set no sooner than after an idle bit is received following a break sequence. scceCuart bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt res ab idl gra brke brks res ccr bsy tx rx reset 0 0000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x a30
communication processor module motorola mpc823e reference manual 16-229 communication 16 processor module sccs brksbreak start if set, this bit indicates when a break character is received. it is the first break of a break sequence. you do not receive multiple brks events if a long break sequence is received. ccrcontrol character received if set, this bit indicates when a control character is received and stored in the rccrp of the sccx uart parameter ram. bsybusy condition if set, this bit indicates that a character has been received and discarded due to a lack of buffers. if multidrop mode is selected, the receiver automatically enters hunt mode. otherwise, reception continues as soon as an empty buffer is provided. the latest point that an rx buffer descriptor can be changed to empty and still guarantee that a busy condition will be avoided, is the middle of the stop bit of the first character to be stored in that buffer. txtx buffer if set, this bit indicates that a buffer has been transmitted over the uart channel. if the cr bit is set to 1 in the tx buffer descriptor, this bit is set no sooner than when the last stop bit of the last character in the buffer is first transmitted. if cr is set to 0, this bit is set after the last character is written to the transmit fifo. rxrx buffer if set, this bit indicates that a buffer has been received over the uart channel. this event occurs no sooner than the middle of the first stop bit of the character that caused the buffer to close. 16.9.15.19 sccx uart mask register. when a serial communication controller is in uart mode, the 16-bit, read/write sccx mask register is referred to as the sccx uart mask register (sccmCuart). it has the same bit formats as the scceCuart register. if a bit in this register is a 1, the corresponding interrupt in the scceCuart register is enabled. if it is zero, the corresponding interrupt is masked. sccmCuart bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt res ab idl gra brke brks res ccr bsy tx rx reset 0 0000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x a34
communication processor module 16-230 mpc823e reference manual motorola communication 16 processor module sccs 16.9.15.20 sccx uart status register. when a serial communication controller is in uart mode, the 8-bit read-only sccx status register is referred to as the sccx uart status register (sccsCuart). since each protocol has specific requirements, the sccs bits are different for each implementation. this register allows you to monitor real-time status conditions on the rxdx pin. the real-time status of the ctsx and cdx pins are part of the port c parallel i/o. bits 0C6reserved these bits are reserved and must be set to 0. ididle status this bit is set when the rxdx pin has been a logic one for at least a full character time. 0 = the pin is not idle. 1 = the pin is idle. 16.9.15.21 scc2 uart programming example. the following initialization sequence is for the 9,600 baud, 8 data bits, no parity, and stop bit of the scc2 in uart mode assuming a 25mhz system frequency. brg1 is used in the example. the scc2 uart controller is configured with the rts2 , cts2 , and cd2 pins active and the cts2 pin is used as an automatic flow control signal. 1. configure the port a pins to enable the txd2 and rxd2 pins. write papar bits 13 and 12 with ones and then write the padir and paodr bits 13 and 12 with zeros. 2. configure the port c pins to enable rts2 , cts2 , and cd2 . write pcpar bit 14 with one and bits 9 and 8 with zeros, pcdir bits 14, 9, and 8 with zeros, and pcso bits 9 and 4 with ones. 3. configure brg1 and write 0x010144 to the brgc1. the div16 bit is not used and the divider is 162 (decimal). the resulting brg1 clock is 16x the preferred bit rate of scc2 in uart mode. 4. connect the brg1 clock to scc2 using the serial interface. in the sicr, set the r2cs field to 000 and the t2cs field to 000. 5. write 0x0001 to the sdcr to set the sdma bus arbitration level to 5. 6. connect the scc2 to the nmsi and clear the sc2 bit in the sicr. sccsCuart bit 0 1 2 3 4 5 6 7 field reserved id reset 00 r/w rr addr (immr & 0xffff0000) + 0xa37
communication processor module motorola mpc823e reference manual 16-231 communication 16 processor module sccs 7. write to rbase and tbase in the scc2 parameter ram to point to the rx and tx buffer descriptors in the dual-port ram. assuming one rx buffer descriptor at the beginning of dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write 0x2000 to rbase and 0x2008 to tbase. 8. write 0x0041 to the cpcr to execute the init rx and tx params command for scc2. 9. write 0x15 to the rfcr and 0x15 to the tfcr for normal operation. 10. write the maximum number of bytes per receive buffer to the mrblr. for this case, assume 16 bytes, so mrblr = 0x0010. 11. write 0x0000 to the max_idl in the scc2 uart parameter ram to disable the max_idl functionality for this example. 12. write 0x0001 to the brkcr, so that if a stop transmit command is issued, one break character is sent. 13. clear parec, frmec, nosec, and brkec in the scc2 uart parameter ram. 14. clear uaddr1 and uaddr2. they are not used. 15. clear toseq. it is not used. 16. write 0x8000 to character1Ccharacter8. they are not used. 17. write 0xc0ff to the rccm. it is not used. 18. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. 19. initialize the tx buffer descriptor. assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xb000 to tx_bd_status, 0x0010 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 20. write 0xffff to the scceCuart register to clear any previous events. 21. write 0x0003 to the sccmCuart register to enable the transmit and receive interrupts. 22. write 0x20000000 to the cimr so the scc2 can generate a system interrupt. the cicr must also be initialized. 23. write 0x00000020 to the gsmr_h to configure a small receive fifo width. 24. write 0x00028004 to the gsmr_l to configure 16 oversampling for transmit and receive, the cts2 and cd2 pins to automatically control transmission and reception (diag field) and the scc2 uart mode. notice that the transmitter (ent bit) and receiver (enr bit) have not been enabled yet. 25. write 0xb000 to the psmrCscc2 uart to configure automatic flow control using the cts2 pin, 8-bit characters, no parity, 1 stop bit, and asynchronous scc2 uart operation. 26. write 0x00028034 to the gsmr_l register to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits are enabled last.
communication processor module 16-232 mpc823e reference manual motorola communication 16 processor module sccs 16.9.15.22 s-record programming example. the following is an example of a downloading application that uses a sccx channel as a uart controller. the application performs s-record downloads and uploads between a host computer and an intelligent peripheral through a serial asynchronous line. the s-records are strings of ascii characters that begin with s and end in an end-of-line character. this characteristic is used to impose a message structure on the communication between the devices. each device can transmit xon and xoff characters for flow control, which do not form part of the program being uploaded or downloaded. the psmrscc uart register must be set as needed with the frz bit cleared and the ent and enr bits set. receive buffers must be linked to the receive buffer table with the i bit set. for simplicity, assume that the line is not multidrop (no addresses are transmitted) and that each s-record fits into a single data buffer. three characters must first be entered into the sccx uart control character table: ? line feedboth the e and r bits must be cleared. when an end-of-line character is received, the current buffer is closed and made available to the core for processing. this buffer contains an entire s-record that the processor can now check and copy to memory or disk as required. ? xoffe must be cleared and r must be set. whenever the core receives a control character received interrupt and the receive control character register contains xoff, the software must immediately stop transmitting to the other station by setting the frz bit in the psmrCscc uart. this prevents data from being lost by the other station when it runs out of receive buffers. ? xonthis character must be received after xoff. the e bit must be cleared and the r bit must be set. the frz bit on the transmitter must now be cleared. the communication processor module automatically resumes transmission of the serial line at the point at which it was previously stopped. like xoff, the xon character is not stored in the receive buffer. to receive the s-records, the core must only wait for the receive interrupt, thus indicating that a complete s-record buffer has been received. transmission requires assembling s-records into data buffers and linking them to the transmit buffer table and it can be temporarily stopped when an xoff character is received. this scheme minimizes the number of interrupts received by the core (one per s-record) and relieves it from the task of continually scanning for control characters. note: after 16 bytes are transmitted, the tx buffer descriptor is closed. additionally, the receive buffer is closed after 16 bytes are received. any data received after 16 bytes causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module motorola mpc823e reference manual 16-233 communication 16 processor module sccs 16.9.16 the sccs in hdlc mode layer 2 of the seven-layer open systems interconnection model from iso is the data link layer and one of the most common protocols in this layer is high-level data link control (hdlc). in fact, many other common layer 2 protocolssdlc, ss#7, appletalk, lapb, and lapdare based on hdlc and its framing structure, which is illustrated in figure 16-78. hdlc uses a zero insertion/deletion process (referred to as bit-stuffing) to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. the hdlc frame is synchronous and relies on the physical layer to provide a method for clocking and synchronizing the transmitter/receiver. since the layer 2 frame can be transmitted over a point-to-point link, a broadcast network, or packet and circuit switched systems, an address field is needed to carry the frame's destination address. the length of this field is commonly 0, 8, or 16 bits, depending on the data link layer protocol. for instance, sdlc and lapb use an 8-bit address and ss#7 has no address field at all because it is always used in point-to-point signaling links. lapd further divides its 16-bit address into different fields to specify various access points within one piece of equipment. it also defines a broadcast address. some hdlc-type protocols allow for extended addressing beyond 16 bits. the 8- or 16-bit control field provides a flow control number and defines the frame type (control or data). the exact use and structure of this field depends on the protocol using the frame. data is transmitted in the data field and its length is dependent on the protocol of the frame. layer 3 frames are carried in this data field. error control is implemented by appending a cyclic redundancy check (crc) to the frame, which in most protocols is 16 bits long but can be as long as 32 bits. in hdlc, the least-significant bit of each octet is transmitted first and the most-significant bit of the crc is transmitted first. when the mode field of the gsmr_l is set to hdlc mode, a serial communication controller is functioning in hdlc mode. when you use an sccx in hdlc mode with a nonmultiplexed modem interface, the serial communication controller outputs are connected directly to the external pins. modem signals can be supported through the port b and c pins. the receive and transmit clocks can be supplied from either the bank of baud rate generators, by the dpll, or externally. you can also connect the sccx in hdlc mode to the tdm channels of the serial interface and use it with the time-slot assigner. the sccx in hdlc mode, also called the sccx hdlc controller, consists of separate transmit and receive sections whose operations are asynchronous with the core. you can allocate up to 196 buffer descriptors, so that you can transmit or receive many frames without interference from the host.
communication processor module 16-234 mpc823e reference manual motorola communication 16 processor module sccs 16.9.16.1 features. the following list summarizes the main features of the sccx in hdlc mode: ? flexible data buffers with multiple buffers per frame ? separate interrupts for frames and buffers (receive and transmit) ? received frames threshold to reduce interrupt overhead ? can be used with the sccx dpll ? four address comparison registers with mask ? maintenance of five 16-bit error counters ? flag/abort/idle generation or detection ? zero insertion/deletion ? 16- or 32-bit crc-ccitt generation/checking ? detection of nonoctet aligned frames ? detection of frames that are too long ? programmable flags (0C15) between successive frames ? automatic retransmission in case of collision 16.9.16.2 sccx hdlc channel frame transmission process. the hdlc transmitter is designed to operate with little or no intervention from the core. when the core enables one of the transmitters, it starts transmitting flags or idles as programmed in the psmrCscc hdlc register. the sccx hdlc controller polls the first buffer descriptor in the transmit channel buffer descriptor table. when there is a frame to transmit, the sccx hdlc controller fetches the data from memory and starts transmitting the frame after it transmits the minimum number of flags that you specify between frames. when the end of the current buffer descriptor has been reached and the last buffer in the frame bit is set, the crc and closing flag are appended. in hdlc mode, the least-significant bit of each octet and the most-significant bit of the crc are transmitted first. an hdlc frame is illustrated in figure 16-78. after a closing flag is transmitted, the sccx hdlc controller writes the frame status bits into the buffer descriptor and clears the r bit. when you reach the end of the current buffer descriptor and the last bit is not set, only the r bit is cleared. in either mode, an interrupt can be issued if the i bit in the tx buffer descriptor is set. the sccx hdlc controller then proceeds to the next tx buffer descriptor in the table. this method allows you to be interrupted after each buffer, a specific buffer, or each frame. opening flag address control information (optional) crc closing flag 8 bits 16 bits 8 bits 8n bits 16 bits 8 bits figure 16-78. sccx hdlc framing structure
communication processor module motorola mpc823e reference manual 16-235 communication 16 processor module sccs to rearrange the transmit queue before the communication processor module finishes transmitting all of the buffers, issue the stop transmit command. this can be useful for transmitting expedited data before previously linked buffers or when an error occurs. when receiving the stop transmit command, the sccx hdlc controller stops transmitting the current frame and starts transmitting idles or flags. when the sccx hdlc controller receives the restart transmit command, it resumes transmission. to insert a high-priority frame without aborting the current frame, the graceful stop transmit command can be issued. a special interrupt can be generated in the event register when the current frame is complete. 16.9.16.3 sccx hdlc channel frame reception process. the hdlc receiver is designed to operate with little or no intervention from the core and can perform address recognition, crc checking, and maximum frame length checking. you are free to use the received frame to perform any hdlc-based protocol. when the core enables one of the receivers, the receiver waits for an opening flag character and when it detects the first byte of the frame, the sccx hdlc controller compares the frame address against the user-programmable addresses. you have four 16-bit address registers and an address mask available for address matching. the sccx hdlc controller compares the received address field to the user-defined values after masking with the address mask. the sccx hdlc controller can also detect broadcast (all ones) address frames if one address register is written with all ones. if a match is detected, the sccx hdlc controller fetches the next buffer descriptor and if it is empty, it starts transferring the incoming frame to the buffer descriptor associated data buffer. when the data buffer has been filled, the sccx hdlc controller clears the e bit in the buffer descriptor and generates an interrupt if the i bit in the buffer descriptor is set. if the incoming frame exceeds the length of the data buffer, the sccx hdlc controller fetches the next buffer descriptor in the table and, if it is empty, continues transferring the rest of the frame to this buffer descriptor associated data buffer. during this process, the sccx hdlc controller checks for a frame that is too long. when the frame ends, the crc field is checked against the recalculated value and written to the data buffer. the data length written to the last buffer descriptor in the hdlc frame is the length of the entire frame. this enables hdlc protocols that lose frames to correctly recognize the frame-too-long condition. the sccx hdlc controller then sets the last buffer in the frame bit, writes the frame status bits into the buffer descriptor, and clears the e bit. the sccx hdlc controller next generates a maskable interrupt, indicating that a frame has been received and is in memory. the sccx hdlc controller then waits for a new frame. back-to-back frames can be received with only a single shared flag between frames. in the received frames threshold (rfthr) location of the parameter ram, you can configure the sccx hdlc controller not to interrupt the core until a certain number of frames are received. you can combine this function with a timer to implement a timeout if less than the threshold number of frames are received.
communication processor module 16-236 mpc823e reference manual motorola communication 16 processor module sccs 16.9.16.4 sccx hdlc parameter ram memory map. when configured to operate in hdlc mode, the serial communication controllers overlay the structure used in table 16- 24 with the hdlc parameters that are described in table 16-27 below. note: the sccx hdlc controller must receive a maximum of eight clocks (after a frame is received) to complete the reception. table 16-27. sccx hdlc parameter ram memory map address name width description sccx base + 30 res word reserved sccx base + 34 c_mask word crc constant sccx base + 38 c_pres word crc preset sccx base + 3c disfc half-word discard frame counter sccx base + 3e crcec half-word crc error counter sccx base + 40 abtsc half-word abort sequence counter sccx base + 42 nmarc half-word nonmatching address rx counter sccx base + 44 retrc half-word frame transmission counter sccx base + 46 mflr half-word max frame length register sccx base + 48 max_cnt half-word maximum length counter sccx base + 4a rfthr half-word received frames threshold sccx base + 4c rfcnt half-word received frames count sccx base + 4e hmask half-word user-defined frame address mask sccx base + 50 haddr1 half-word user-defined frame address sccx base + 52 haddr2 half-word user-defined frame address sccx base + 54 haddr3 half-word user-defined frame address sccx base + 56 haddr4 half-word user-defined frame address sccx base + 58 tmp half-word temp storage sccx base + 5a tmp_mb half-word temp storage note: you are only responsible for initializing the items in bold. sccx base = (immr & 0xffff0000) + 0x3d00 (scc2) and 0x3e00 (scc3). all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register.
communication processor module motorola mpc823e reference manual 16-237 communication 16 processor module sccs ? c_maskfor the 16-bit crc-ccitt, c_mask must be initialized with 0x0000f0b8. for the 32-bit crc-ccitt, c_mask must be initialized with 0xdebb20e3. ? c_presfor the 16-bit crc-ccitt, c_pres must be initialized with 0x0000ffff. for the 32-bit crc-ccitt, c_pres must be initialized with 0xffffffff. ? disfc, crcec, abtsc, nmarc, and retrcthese 16-bit (modulo 2 16 ) counters are maintained by the communication processor module. you can initialize the following counters while the channel is disabled. o disfcCdiscarded frame counter (error-free frames, but no free buffers). o crcecCcrc error counter. includes frames not addressed to you or frames received in the bsy condition, but does not include overrun errors. o abtscCabort sequence counter. o nmarcCnonmatching address received counter (error-free frames only). o retrcCframe retransmission counter (due to collision). ? mflrthe sccx hdlc controller compares the length of an incoming hdlc frame with the user-defined value given in this 16-bit register. if this limit is exceeded, the remainder of the incoming hdlc frame is discarded and the lg bit is set in the last rx buffer descriptor belonging to that frame. the sccx hdlc controller waits until the end of the frame and then reports the frame status and length in the last rx buffer descriptor. the mflr is defined as all the in-frame bytes between the opening and closing flags. ? max_cnta temporary down-counter used to track the frame length. ? rfthrthe received frames threshold value is used to reduce the interrupt overhead that might otherwise occur when a series of short hdlc frames arrives, each causing an rxf interrupt. by setting the rfthr value, you limit the frequency of rxf interrupts, which only occurs when the rfthr value is reached. ? rfcnta temporary down-counter used to implement the rfthr feature. ? hmask, haddr1, haddr2, haddr3, and haddr4the sccx hdlc controller has five 16-bit registers for address recognition: one mask register and four address registers. the sccx hdlc controller reads the frame address from the hdlc receiver, compares it against the four address register values, and then masks the result with the user-defined mask register. a one in the mask register represents a bit position for which address comparison must occur and a zero represents a masked bit position. when an address match is made, the address and the data following it are written into the data buffers. when the addresses are not matched and the frame is error-free, the nonmatching address received counter (nmarc) is incremented. note: you must provide enough empty rx buffer descriptors to receive the number of frames specified in the rfthr.
communication processor module 16-238 mpc823e reference manual motorola communication 16 processor module sccs ? tmpa temporary register that is only used by the communication processor module. ? tmp_mba temporary register that is only used by the communication processor module. 16.9.16.5 programming the sccs in hdlc mode. the core configures the serial communication controllers to operate in one of the protocols set in the mode field of the gsmr_l. the sccx hdlc controller uses the same data structure as other modes and it supports multibuffer operation and address comparisons. the reception errors are reported through the rx buffer descriptor and the transmit errors are reported through the tx buffer descriptor. note: for 8-bit addresses, the eight high-order bits in hmask must be masked out (cleared). the eight low-order bits of hmask and haddrx must contain the address byte that immediately follows the opening flag. for, example, to recognize a frame that begins 0x7e, 0x68, 0xaa, using 16-bit address recognition, haddrx must contain 0xaa68 and hmask must contain 0xffff. refer to figure 16-79 for details. figure 16-79. hdlc address recognition example hmask 8-bit address recognition address 0x68 control 0x44 flag 0x7e address 0xaa etc. 16-bit address recognition 0xffff 0xaa68 0xffff 0xaa68 0xaa68 recognizes one 16-bit address (haddr1) and the 16-bit broadcast address (haddr2) hmask address 0x55 control 0x44 flag 0x7e etc. 0x00ff 0xxx55 0xxx55 0xxx55 0xxx55 recognizes a single 8-bit address (haddr1) haddr1 haddr2 haddr3 haddr4 haddr1 haddr2 haddr3 haddr4
communication processor module motorola mpc823e reference manual 16-239 communication 16 processor module sccs 16.9.16.6 sccx hdlc commands. you can program the cpm command register (cpcr) with the following commands to transmit data. ? stop transmit after the hardware or software is reset and the channel is enabled in the psmrCscc hdlc register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table every 64 transmit clocks or immediately if the tod bit is set in the transmit-on-demand register (todr). the channel stop transmit command disables the transmission of frames on the transmit channel. if the sccx hdlc controller receives this command while a frame is transmitting, transmission is aborted after a maximum of 64 additional bits and the transmit fifo is flushed. the tbptr is not advanced, no new buffer descriptor is accessed, and no new frames are transmitted for this channel. the transmitter transmits an abort sequence consisting of 01111111 (if the command was given during frame transmission) and begins transmitting flags or idles, as indicated by the psmrCscc hdlc register. ? graceful stop transmit this command is used to stop transmission smoothly, instead of abruptly, like the stop transmit command. it stops transmission after the current frame is finished or immediately if there is no frame being transmitted. the gra bit in the scceChdlc is set once transmission has stopped. then the hdlc transmit parameters and their buffer descriptors can be modified. the tbptr points to the next tx buffer descriptor in the table. transmission begins once the r bit of the next buffer descriptor is set and the restart transmit command is issued. ? restart transmit this command enables characters to be transmitted on the transmit channel. the sccx hdlc controller expects this command after a stop transmit command is issued or after a graceful stop transmit command is issued or a transmitter error occurs. the sccx hdlc controller resumes transmission from the current tbptr in the channel tx buffer descriptor table. ? init tx parameters this command initializes all transmit parameters in this serial channel parameter ram to their reset state and must only be issued when the transmitter is disabled. the init tx and rx params command can be used to reset the transmit and receive parameters. note: if the mff bit in the psmrCscc uart is set, one or more small frames can be flushed from the transmit fifo. issue the graceful stop transmit command to prevent this from occurring.
communication processor module 16-240 mpc823e reference manual motorola communication 16 processor module sccs you can program the cpm command register with the following commands to receive data. ? enter hunt mode after the hardware or software is reset and the channel is enabled in the psmrCscc hdlc register, the channel is in receive enable mode and uses the first buffer descriptor in the table. the enter hunt mode command is generally used to force the hdlc receiver to stop receiving the current frame and enter hunt mode. in hunt mode, the sccx hdlc controller continually scans the input datastream for the flag sequence. after receiving the command, the current receive buffer is closed and the crc is reset. additional frame reception uses the next buffer descriptor. ? close rx bd this command must not be used in the hdlc protocol. ? init rx parameters this command initializes all the receive parameters in this serial channel parameter ram to their reset state and must only be issued when the receiver is disabled. the init tx and rx params command can be used to reset the receive and transmit parameters. 16.9.16.7 sccx hdlc controller errors. the sccx hdlc controller reports frame reception and transmission error conditions using the channel buffer descriptors, error counters, and scceChdlc register. the following transmission errors can be detected by the sccx hdlc controller. ? transmitter underrun error when this error occurs, the channel terminates buffer transmission, closes the buffer, sets the un bit in the tx buffer descriptor, and generates the txe interrupt if it is enabled. the channel continues transmitting after it receives the restart transmit command. the transmit fifo size is 32 bytes for each serial communication controller. ? cts lost during frame transmission error when this error occurs, the channel terminates buffer transmission, closes the buffer, sets the ct bit in the tx buffer descriptor, and generates the txe interrupt if it is enabled. the channel continues transmitting after it receives the restart transmit command. if this error occurs on the first or second buffer of the frame and the rte bit in the psmrCscc hdlc is set, the channel retransmits the frame when the ctsx signal becomes active again. when you are working in sccx hdlc mode with the possibility of a collision, in order to ensure the retransmission method functions properly, the first and second data buffers must contain more than 36 bytes of data and 20 bytes of data if multiple buffers per frame are used. the channel also increments the retransmission counter. this requirement does not apply to small frames that consist of a single buffer.
communication processor module motorola mpc823e reference manual 16-241 communication 16 processor module sccs the following reception errors can be detected by the sccx hdlc controller. ? overrun errorthe sccx hdlc controller maintains an internal fifo for receiving data. the communication processor module begins programming the sdma channel and updating the crc when 8 or 32 bits are received in the fifo. when a receive fifo overrun occurs, the channel writes the received data byte to the internal fifo over the previously received byte. the previous data byte and the frame status are lost. the channel closes the buffer with the ov bit in the rx buffer descriptor set and generates the rxf interrupt if it is enabled. the receiver then enters hunt mode. even if an overrun occurs during a frame whose address is not matched in the address recognition logic, an rx buffer descriptor with a data length of two is opened to report the overrun and the rxf interrupt is generated if it is enabled. ? cd lost during frame reception error when this error occurs, the channel terminates frame reception, closes the buffer, sets the cd bit in the rx buffer descriptor, and generates the rxf interrupt if it is enabled. this error has the highest priority. the rest of the frame is lost and other errors are not checked in that frame. at this point, the receiver enters hunt mode. ? abort sequence error this error occurs when seven or more consecutive ones are received. when it does occur and the sccx hdlc controller receives a frame, the channel closes the buffer by setting the ab bit in the rx buffer descriptor and generating the rxf interrupt, if enabled. the channel also increments the abort sequence counter. the crc and nonoctet error status conditions are not checked on aborted frames. the receiver then enters hunt mode. when an abort is received, you are given no indication that an sccx hdlc controller is not currently receiving a frame. ? nonoctet aligned frame error when this error occurs, the channel writes the received data to the data buffer, closes the buffer, sets the no bit in the rx buffer descriptor, and generates the rxf interrupt if it is enabled. the crc error status must be disregarded on nonoctet frames. after a nonoctet aligned frame is received, the receiver enters hunt mode. an immediate back-to-back frame is still received. the nonoctet data may be derived from the last word in the data buffer as follows: msb lsb 10 0 note: if you are using the data buffer swapping option, the above diagram refers to the last byte of the data buffer, not the last word. in sccx-hdlc mode, the least- significant bit of each octet is transmitted first and the most-significant bit of the crc is transmitted first.
communication processor module 16-242 mpc823e reference manual motorola communication 16 processor module sccs ? crcwhen this error occurs, the channel writes the received crc to the data buffer, closes the buffer, sets the cr bit in the rx buffer descriptor, and generates the rxf interrupt if it is enabled. the channel also increments the crc error counter. after receiving a frame with a crc error, the receiver enters hunt mode. an immediate back- to-back frame is still received. crc checking cannot be disabled, but the crc error can be ignored if checking is not required. 16.9.16.8 sccx hdlc mode register. when a serial communication controller is in hdlc mode, the 16-bit, memory-mapped, read/write protocol-specific mode register is referred to as the sccx hdlc mode register (psmrCscc hdlc). since each protocol has specific requirements, the psmr bits are different for each implementation. nofnumber of flags this field signifies the minimum number of flags between or before frames. if nof = 0000, then no flags are inserted between the frames. thus, the closing flag of one frame is immediately followed by the opening flag of the next frame in the case of back-to-back frames. these bits can be modified on-the-fly. crccrc selection 00 = 16-bit ccitt-crc (hdlc). x16 + x12 + x5 + 1. 01 = reserved. 10 = 32-bit ccitt-crc (ethernet and hdlc). x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1. 11 = reserved. rteretransmit enable 0 = no retransmission. 1 = automatic frame retransmission is enabled. retransmission only occurs if the lost ctsx occurs on the first or second buffer of the frame. bits 7 and 13C15reserved these bits are reserved and must be set to 0. psmrCscc hdlc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field nof crc rte res fse drt bus brm mff reserved reset 0 0 0000000 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa28
communication processor module motorola mpc823e reference manual 16-243 communication 16 processor module sccs fseflag sharing enable. this bit is only valid if the rtsm bit is set in the gsmr_h. this bit can be modified on-the-fly. 0 = normal operation. 1 = if the nof0Cnof3 field is set to 0000, then a single shared flag is transmitted between back-to-back frames. other values of nof0Cnof3 are decremented by 1 when this bit is set. this is useful in signaling system #7 (ss#7) applications. drtdisable receiver while transmitting 0 = normal operation. 1 = while data is being transmitted by a serial communication controller, the receiver is disabled. this configuration is useful if the hdlc channel is configured onto a multidrop line and you do not want to receive your own transmission. bushdlc bus mode 0 = normal hdlc operation. 1 = hdlc bus operation is selected. refer to section 16.9.17 the hdlc bus controller for more details. brmhdlc bus rts mode this bit is only valid if the bus bit is set to 1. otherwise, it is ignored. 0 = normal rtsx operation during hdlc bus mode. rtsx is asserted on the first bit of the transmit frame and negated after the first collision bit is received. 1 = special rtsx operation during hdlc bus mode. rtsx is delayed by one bit with respect to the normal case. this is useful when the hdlc bus protocol is being run locally and transmitted over a long-distance transmission line at the same time. data can be delayed one bit before it is sent over the transmission line, thus rtsx can be used to enable the transmission line buffers. the result is a clean signal level sent over the transmission line. mffmultiple frames in fifo 0 = normal operation. the transmit fifo must never contain more than one hdlc frame. the ctsx lost status is reported accurately on a per-frame basis. the receiver is not affected by this bit. 1 = the transmit fifo can contain multiple frames, but lost ctsx is not guaranteed to be reported on the exact buffer/frame it truly occurred on. this option, however, can improve the performance of hdlc transmissions of small back-to-back frames or in cases where you prefer to limit the number of flags transmitted between frames. the receiver is not affected by this bit.
communication processor module 16-244 mpc823e reference manual motorola communication 16 processor module sccs 16.9.16.9 sccx hdlc receive buffer descriptor. the sccx hdlc controller uses the receive (rx) buffer descriptor to report information about the data received for each buffer. an example of the rx buffer descriptor process is illustrated in figure 16-80. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-245 communication 16 processor module sccs figure 16-80. scc2 hdlc receive buffer descriptor example mrblr = 8 bytes for scc2 buffer 8 bytes time buffer 8 bytes empty buffer 8 bytes empty buffer full e length receive bd 0 status 0008 pointer 0 e length receive bd 1 status 000b pointer 0 1 0 l e length receive bd 2 status 0003 pointer 0 ab 1 e length receive bd 3 status xxxx pointer 1 buffer 8 bytes present time empty buffer still empty abort was received after control byte buffer closed when closing flag received 1 f 0 lf 1 1 stored in rx buffer stored in rx buffer faaciiiii icrcrf two frames received in hdlc line idle address 1 address 2 control byte last i-field byte crc byte 1 crc byte 2 address 1 address 2 control byte 5 information (i-field) bytes unexpected abort occurs before closing flag abort/idle faac f = flag a = address byte c = control byte i = information byte legend: cr = crc byte l f 32-bit buffer pointer 32-bit buffer pointer 32-bit buffer pointer 32-bit buffer pointer
communication processor module 16-246 mpc823e reference manual motorola communication 16 processor module sccs eempty 0 = the data buffer associated with this rx buffer descriptor has been filled with data or reception has been aborted because of an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or is currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 7, and 9reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = the rxb bit is not set after this buffer is used, but rxf operation remains unaffected. 1 = the rxb or rxf bit in the scceChdlc register is set when the sccx hdlc controller uses this buffer. these two bits can cause interrupts if they are enabled. llast in frame this bit is set by the sccx hdlc controller when this buffer is the last one in a frame. this implies the reception of a closing flag or reception of an error, in which case one or more of the cd, ov, ab, and lg bits are set. the sccx hdlc controller writes the number of frame octets to the data length field. 0 = this buffer is not the last one in a frame. 1 = this buffer is the last one in a frame. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi lf cm res de res lg no ab cr ov cd offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module motorola mpc823e reference manual 16-247 communication 16 processor module sccs ffirst in frame this bit is set by the sccx hdlc controller when this buffer is the first in a frame. 0 = the buffer is not the first one in a frame. 1 = the buffer is the first one in a frame. cmcontinuous mode 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this buffer descriptor. the e bit is cleared if an error occurs during reception, regardless of how the cm bit is set. dedpll error this bit is set by the sccx hdlc controller if a dpll error occurs while this buffer is being received. in decoding modes in which a transition is promised every bit, the de bit is set when a missing transition occurs. lgrx frame length violation this bit indicates when a frame length greater than the maximum defined for this channel is recognized and only the maximum-allowed number of bytes (mflr) is written to the data buffer. this event is not reported until the rx buffer descriptor is closed, the rxf bit is set, and the closing flag is received. the actual number of bytes received between flags is written to the data length field of this buffer descriptor. norx nonoctet aligned frame this bit indicates that a frame has been received that contains a number of bits almost divisible by eight. abrx abort sequence this bit indicates that a minimum of seven consecutive ones have been received when a frame is received. crrx crc error this bit indicates that this frame contains a crc error. the received crc bytes are always written to the receive buffer. ovoverrun this bit indicates that a receiver overrun has occurred while a frame was being received. cdcarrier detect lost this bit indicates that a carrier detect signal has been negated while a frame was being received. this bit is only valid when working in nmsi mode.
communication processor module 16-248 mpc823e reference manual motorola communication 16 processor module sccs data length this field represents the number of octets the communication processor module writes into this buffer descriptor data buffer. it is written by the communication processor module once the buffer descriptor is closed. when this buffer descriptor is the last buffer descriptor in the frame (l = 1), the data length contains the total number of frame octets, including 2 or 4 bytes for crc. the actual amount of memory allocated for this buffer must be greater than or equal to the mrblr. rx data buffer pointer this field points to the first location of the associated data buffer. it resides in internal or external memory and must be divisible by four. 16.9.16.10 sccx hdlc transmit buffer descriptor. data is sent to the sccx hdlc controller for transmission on an sccx channel by arranging it in buffers referenced by the channels tx buffer descriptor table. using the transmit (tx) buffer descriptors, the communication processor module confirms transmission and indicates error conditions so that the core knows the buffers have been serviced. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer has been transmitted or an error condition is encountered. 1 = the data buffer, which you have prepared, has not been transmitted or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1 and 7C13reserved these bits are reserved and must be set to 0. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi ltccm reserved un ct offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-249 communication 16 processor module sccs wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer has been used, the communication processor module transmits data from the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table are programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the txb or txe bit in the scceChdlc register is set when this buffer is serviced by the sccx hdlc controller. these bits can cause interrupts if they are enabled. llast 0 = this is not the last buffer in the frame. 1 = this is the last buffer in the frame. tctx crc this bit is valid only when the l bit is set. otherwise, it is ignored. 0 = transmit the closing flag after the last data byte. this setting can be used to send a bad crc after the data for testing purposes. 1 = transmit the crc sequence after the last data byte. cmcontinuous mode 0 = normal operation. 1 = the r bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor. however, the r bit is cleared if an error occurs during transmission, regardless of how the cm bit is set. ununderrun this bit indicates when the sccx hdlc controller encounters a transmitter underrun condition while transmitting the associated data buffer. the sccx hdlc controller writes these bits after it finishes transmitting the associated data buffer. ctcts lost this bit indicates when ctsx in nmsi mode or layer 1 grant is lost in gci mode during frame transmission. if data from more than one buffer is currently in the fifo when this error occurs, this bit is set in the currently open tx buffer descriptor. the sccx hdlc controller writes these bits after it finishes transmitting the associated data buffer.
communication processor module 16-250 mpc823e reference manual motorola communication 16 processor module sccs data length this field represents the number of bytes the sccx hdlc controller transmits from this buffer descriptor data buffer. it is never modified by the communication processor module. the value of this field must be greater than zero. the sccx hdlc controller writes these bits after it finishes transmitting the associated data buffer. tx data buffer pointer this field contains the address of the associated data buffer and can be even or odd. the buffer can reside in internal or external memory. this value is never modified by the communication processor module. the sccx hdlc controller writes these bits after it finishes transmitting the associated data buffer. 16.9.16.11 sccx hdlc event register. when a serial communication controller is in hdlc mode, the 16-bit, memory-mapped sccx event register is referred to as the sccx hdlc event register (scceChdlc). since each protocol has specific requirements, the scce bits are different for each implementation. this register is used to report events recognized by the hdlc channel and to generate interrupts. when an event is recognized, the sccx hdlc controller sets the corresponding bit in this register. interrupts generated by this register can be masked in the sccmChdlc register. an example of interrupts that can be generated using the hdlc protocol is illustrated in figure 16-81.
communication processor module motorola mpc823e reference manual 16-251 communication 16 processor module sccs figure 16-81. hdlc interrupt event example line idle stored in rx buffer frame received in hdlc time rxdx cdx line idle line idle stored in tx buffer ctsx line idle txdx rtsx idl cdx cdx rxb ctsx ctsx txb notes: 1. rxb event assumes receive buffers are 6 bytes each. 2. the second idl event occurs after 15 ones are received in a row. 3. the flg interrupts show the beginning and end of flag reception. 4. the flg interrupt at the end of the frame may precede the rxf interrupt due to receive fifo latency. 5. the cdx event must be programmed in the port c parallel i/o, not in the scc itself. 6. f is set to flag, a is set to address byte, c is set to control byte, i is set to information byte, and cr is set to cr c byte. notes: 1. txb event shown assumes all three bytes were put into a single buffer. 2. example shows one additional opening flag. this is programmable. 3. the ctsx event must be programmed in the port c parallel i/o, not in the scc itself. hdlc scce events hdlc scce events frame transmitted by hdlc f a a c i cr cr i if rxf flg idl f a a c cr cr f f flg flg f flg
communication processor module 16-252 mpc823e reference manual motorola communication 16 processor module sccs a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. also, all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared at reset and can be read at any time. bits 0C2 and 9C10reserved these bits are reserved and must be set to 0. glrglitch on rx if set, this bit indicates that a serial communication controller has detected a clock glitch on the receive clock. gltglitch on tx if set, this bit indicates that a serial communication controller has detected a clock glitch on the transmit clock. dccdpll carrier-sense changed this bit indicates that the carrier-sense status generated by the dpll has changed state. its real-time status can be found in the sccsChdlc register. this is not the cdx pin status that is reported in port c and it is only valid when the dpll is used. flgflag status this bit indicates that the sccx hdlc controller has stopped or started receiving hdlc flags. its real-time status can be obtained in the sccsChdlc register. idlidle sequence status changed this bit indicates that a change has occurred in the status of the serial line on the hdlc line. the real-time status of the line can be read in the sccsChdlc register. gragraceful stop complete this bit indicates that a graceful stop, which was initiated by the graceful stop transmit command, has completed. this bit is set as soon as the transmitter finishes transmitting any frame that was in progress when the command was issued. it is set immediately if no frame was in progress when the command was issued. txetx error this bit indicates that an error has occurred on the transmitter channel. scceChdlc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt dcc flg idl gra reserved txe rxf bsy txb rxb reset 0 000000 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa30
communication processor module motorola mpc823e reference manual 16-253 communication 16 processor module sccs rxfrx frame this bit indicates when a complete frame is received on the hdlc channel. this bit is set no sooner than two clocks after the last bit of the closing flag is received. bsybusy condition this bit indicates when a frame has been received and discarded due to a lack of buffers. txbtransmit buffer this bit indicates that a buffer has been transmitted on the hdlc channel. this bit is set no sooner than when the last bit of the closing flag begins its transmission if the buffer is the last one in the frame. otherwise, this bit is set after the last byte of the buffer is written to the transmit fifo. rxbreceive buffer this bit indicates that the hdlc channel received a buffer that is not a complete frame. 16.9.16.12 sccx hdlc mask register. when a serial communication controller is in hdlc mode, the 16-bit, read/write sccx mask register is referred to as the sccx hdlc mask register (sccmChdlc). it has the same bit formats as the scceChdlc register. if a bit in this register is a 1, the corresponding interrupt in the scceChdlc register is enabled. if the bit is zero, the corresponding interrupt in the scceChdlc is masked. sccmChdlc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt dcc flg idl gra reserved txe rxf bsy txb rxb reset 0 000000 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa34
communication processor module 16-254 mpc823e reference manual motorola communication 16 processor module sccs 16.9.16.13 sccx hdlc status register. when a serial communication controller is in hdlc mode, the 8-bit read-only sccx status register is referred to as the sccx hdlc status register (sccsChdlc). since each protocol has specific requirements, the sccs bits are different for each implementation. this register allows you to monitor real-time status conditions on the rxdx pin. the real-time status of the ctsx and cdx pins are part of the port c parallel i/o. bits 0C4reserved these bits are reserved and must be set to 0. fgflags when this bit is cleared, the most recently received eight bits are examined every bit time to see if a flag is present. fg is set as soon as an hdlc flag (0x7e) is received on the line and once it is set, it remains set at least eight bit times and the next eight received bits are examined. if another flag occurs, this bit stays set for at least another eight bits. otherwise, it is cleared and the search begins again. the line is checked after the data has been decoded by the dpll. 0 = hdlc flags are not being received. 1 = hdlc flags are being received. cscarrier sense (dpll) this bit shows the real-time carrier sense of the line as determined by the dpll. 0 = the dpll does not sense a carrier. 1 = the dpll senses a carrier. ididle status this bit is set when the rxdx pin is a logic one for 15 or more consecutive bit times. it is cleared after a single logic zero is received. 0 = the rxdx pin is busy. 1 = the rxdx pin is idle. sccsChdlc bit 0 1 2 3 4 5 6 7 field reserved fg cs id reset 0 000 r/w rrorr addr (immr & 0xffff0000) + 0xa37
communication processor module motorola mpc823e reference manual 16-255 communication 16 processor module sccs 16.9.16.14 scc2 hdlc programming example #1. the following initialization sequence is for an scc2 hdlc channel with an external clock. the scc2 in hdlc mode is configured with the rts2 , cts2 , and cd2 pins active and the clk3 pin is used for both the hdlc receiver and transmitter. 1. configure the port a pins to enable the txd2 and rxd2 pins. write papar bits 13 and 12 with ones and then write padir and paodr bits 13 and 12 with zeros. 2. configure the port c pins to enable rts2 , cts2 , and cd2 . write pcpar bit 14 with one, and bits 9 and 8 with zeros, pcdir bits 14, 9, and 8 with zeros, and pcso bits 9 and 8 with ones. 3. configure port a to enable the clk3 pin. write papar bit 5 with a one and padir bit 5 with a zero. 4. connect the clk3 pin to scc2 using the serial interface. in the sicr, set the r2cs and t2cs bits to 110. 5. connect the scc2 to the nmsi (its own set of pins) and clear the sc2 bit in the sicr. 6. write 0x0001 to the sdcr to set the sdma bus arbitration level to 5. 7. write rbase and tbase in the scc2 parameter ram to point to the rx buffer descriptor and tx buffer descriptors in the dual-port ram. assuming one rx buffer descriptor at the beginning of dual-port ram and one tx buffer descriptor following it, write 0x2000 to rbase and 0x2008 to tbase. 8. program the cpcr to execute the init rx and tx params command for the scc2. this command causes the rbptr and tbptr parameters of the serial channel to be updated with the new values just programmed into rbase and tbase. 9. write 0x18 to the rfcr and 0x18 to the tfcr for normal operation. 10. write h the maximum number of bytes per receive buffer to the mrblr. assume 256 bytes, so mrblr = 0x0100. the value 256 is chosen so that an entire receive frame can fit into one receive buffer. 11. write 0x0000f0b8 to c_mask to comply with 16-bit ccitt-crc. 12. write 0x0000ffff to c_pres to comply with 16-bit ccitt-crc. 13. clear disfc, crcec, abtsc, nmarc, and retrc for clarity. 14. write 0x0100 to mflr so the maximum frame size is 256 bytes. 15. write 0x0001 to rfthr to allow interrupts after each frame. 16. write 0x0000 to hmask to allow all addresses to be recognized. 17. clear haddr1, haddr2, haddr3, and haddr4 for clarity. 18. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, write 0x0000 to rx_bd_length (not required), and 0x00001000 to rx_bd_pointer. 19. initialize the tx buffer descriptor. assume the tx data frame is at 0x00002000 in main memory and contains five 8-bit characters. write 0xbc00 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 20. write 0xffff to the scceChdlc to clear any previous events.
communication processor module 16-256 mpc823e reference manual motorola communication 16 processor module sccs 21. write 0x001a to the sccmChdlc to enable the txe, rxf, and txb interrupts. 22. write 0x20000000 to the cimr so the scc2 can generate a system interrupt. the cicr must also be initialized. 23. write 0x00000000 to the gsmr_h to enable normal behavior of the cts2 and cd2 pins and idles between frames (as opposed to flags). 24. write 0x00000000 to the gsmr_l to configure the cts2 and cd2 pins to automatically control transmission and reception and the hdlc mode. normal operation of the transmit clock is used. notice that the transmitter (ent) and receiver (enr) have not been enabled. if inverted hdlc operation is preferred, set the rinv and tinv bits in the gsmr_l. 25. write 0x0000 to the psmrChdlc to configure one opening and one closing flag, 16-bit ccitt-crc, and to prevent multiple frames in the fifo. 26. write 0x00000030 to the gsmr_l to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits are enabled last. 16.9.16.15 scc2 hdlc programming example #2. the following initialization sequence is for an scc2 hdlc channel that uses the dpll in a manchester encoding. you must provide a clock that is 16 the preferred bit rate on the clk3 pin. clk3 is then connected to the hdlc transmitter and receiver. a baud rate generator could also be used. the scc2 hdlc controller is configured with the rts2 , cts 2, and cd2 pins active. 1. follow steps 1 through 22 in example #1 above. 2. write 0x00000000 to the gsmr_h to enable normal behavior of the cts2 and cd2 pins and idles between frames. 3. write 0x004aa400 to the gsmr_l to configure the carrier sense as always active, a 16-bit preamble of 01 pattern, 16 operation of the dpll for the receiver and transmitter, manchester encoding for the receiver and transmitter, and hdlc mode. the cts2 and cd2 pins must also be configured to automatically control transmission and reception. notice that the transmitter (ent) and receiver (enr) have not been enabled yet. 4. write 0x0000 to the psmrChdlc to configure one opening and one closing flag and 16-bit ccitt-crc. multiple frames in the fifo are not allowed in this example. 5. write 0x004aa430 to the gsmr_l to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits are enabled last. note: after 5 bytes and crc have been transmitted, the tx buffer descriptor is automatically closed. once a complete frame is received, the rx buffer descriptor is closed. any data received after 256 bytes or a single frame causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module motorola mpc823e reference manual 16-257 communication 16 processor module sccs 16.9.17 the hdlc bus controller the hdlc bus is an enhancement that makes it easy to implement an hdlc-based lan and other point-to-multipoint configurations. most hdlc-based controllers only provide point-to-point communications. the hdlc bus is based on the techniques used in the ccitt isdn i.430 and ansi t1.605 standards for d channel point-to-multipoint operation over the s/t interface. however, the hdlc bus is not fully compliant with i.430 or t1.605 and cannot be used to replace devices that implement these protocols. instead, it is more suited to fulfill the needs of non-isdn lan and point-to-multipoint configurations. you must review the basic features of the i.430 and t1.605 before learning about the hdlc bus. the i.430 and t1.605 define a method whereby eight terminals can be connected over the d-channel of the s/t bus of isdn. the protocol used at layer 2 is a variant of hdlc, called lapd. however, at layer 1, a method is provided that allows the eight terminals to access the physical s/t bus so they can send frames to the switch. to find out if a channel is clear, the s/t interface device looks at an echo bit on the line designed to echo the last bit transmitted on the d channel. depending on the class of the terminal and the particular situation, the s/t interface device can wait for 7, 8, 9, or 10 ones on the echo bit before allowing the lapd frame to begin transmission. once transmission begins, the s/t chip monitors the data that is sent and if the echo bit matches the transmitted data, transmission continues. if the echo bit is zero when the transmit bit is 1, then a collision will occur between terminals and the station that transmitted a zero will no longer transmit. the station that transmitted a one, however, continues as normal. the i.430 and t1.605 provide a physical layer protocol that allows multiple terminals to share the same physical connection. where collisions are concerned, these protocols use the bus efficiently because one station is always able to complete its transmission. once a station completes a transmission, it lowers its own priority to give other devices fair access to the physical connection. note: after 5 bytes in the preamble have been transmitted, the tx buffer descriptor is automatically closed. once 16 bytes have been received, the rx buffer descriptor is closed. any data received after 16 bytes causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module 16-258 mpc823e reference manual motorola communication 16 processor module sccs the hdlc bus does not use the echo bit, but rather a separate pin to monitor the data that is transmitted. the transmitted data is simply connected to the ctsx input. second, the hdlc bus is a synchronous digital open-drain connection for short-distance configurations, rather than the more complex configurations of an s/t interface. third, the hdlc bus allows any hdlc-based frame protocol to be implemented at layer 2, not just lapd. fourth, the hdlc bus devices wait either 8 or 10 bit times before transmitting, rather than 7, 8, 9, or 10 bits. figure 16-82 illustrates the hdlc bus in its most common lan configuration, the multimaster configuration. all stations can transmit and receive data to or from every other station on the lan and all transmissions are half-duplex, which is typical in lans. figure 16-82. typical hdlc bus multimaster configuration master master hdlc controller hdlc bus lan a hdlc bus controller b hdlc bus controller c master r +5 notes: 1. transceivers may be used to extend the lan size, if necessary. 2. the txdx pins of slave devices must be configured to open-drain in the port c parallel i/o port. txdx rxdx ctsx txdx rxdx txdx rxdx ctsx ctsx
communication processor module motorola mpc823e reference manual 16-259 communication 16 processor module sccs in single-master configuration, a master station transmits to any slave station without any collisions. the slaves only communicate with the master, but can experience collisions in their access over the bus. in this configuration, a slave that communicates with another slave must first transmit its data to the master, where the data is buffered in ram and then retransmitted to the other slave. the benefit of this configuration, however, is that full-duplex operation can be obtained. in a point-to-multipoint environment, this is the preferred configuration. figure 16-83 illustrates the single-master configuration. 16.9.17.1 features. the following list contains the main features of the hdlc bus: ? superset of the sccx in hdlc mode ? automatic hdlc bus access ? automatic retransmission in case of a collision ? may be used with the nmsi mode or a tdm bus ? delayed rtsx mode figure 16-83. typical hdlc bus single-master configuration hdlc controller hdlc bus lan a hdlc bus controller b hdlc bus controller c master slave slave r +5 notes: 1. transceivers may be used to extend the lan size, if necessary. 2. the txdx pins of slave devices must be configured to open-drain in the port c parallel i/o port. txdx rxdx ctsx txdx rxdx ctsx txdx rxdx
communication processor module 16-260 mpc823e reference manual motorola communication 16 processor module sccs 16.9.17.2 accessing the hdlc bus. the hdlc bus ensures an orderly access to the bus when two or more transmitters attempt to access it simultaneously. one transmitter is always successful in completing its transmission. while in the active condition, the hdlc bus controller monitors the bus using the ctsx pin. it counts the number of one bits using the ctsx pin and if a zero is detected, the internal counter is cleared. once eight consecutive ones have been received, the hdlc bus controller starts transmitting on the line. while it is transmitting information on the bus, the data is continuously compared with the ctsx pin and used to sample the external bus. the ctsx sample is taken halfway through the bit time using the rising edge of the transmit clock. if the transmitted bit is the same as the received ctsx sample, the hdlc bus controller continues its transmission. if, however, the received ctsx sample is zero, but the transmitted bit was 1, the hdlc bus controller stops transmitting after that bit and returns to active condition. since the hdlc bus uses a wired-or scheme, a transmitted zero has priority over a transmitted 1. figure 16-84 illustrates how the ctsx pin is used. if the source address is included in the hdlc frame and destination address, a predefined priority of nodes results. collisions can be detected no later than the end of the source address, if one is included. figure 16-84. detecting an hdlc bus collision note: the hdlc bus can be used with many different hdlc-based frame formats. txdx (output) tclk ctsx (input) ctsx sampled at halfway point. collision detected when txd2 is set to 1, but ctsx is set to 0.
communication processor module motorola mpc823e reference manual 16-261 communication 16 processor module sccs to ensure that all stations gain an equal share of the bus, a priority mechanism is implemented on the hdlc bus. once an hdlc bus node has finished transmitting a frame, it waits 10 consecutive one bits, instead of eight, before beginning the next transmission. using this method, all nodes that need to transmit can obtain the bus before a node transmits twice. once a node detects that 10 consecutive ones have occurred on the bus, it tries to transmit and reinstate its original priority of waiting for eight ones. 16.9.17.2.1 improving performance. since the hdlc bus is used in a wired-or configuration, the limitations of the hdlc bus is determined by the rise time of the one bit. figure 16-85 illustrates a method to increase performance. you must supply a clock that is lower more than it is high, which allows the one bit to have more rise time. figure 16-85. example of a nonsymmetrical duty cycle tclk ctsx (input) txdx (output) ctsx sampled at three quarter point. collision detected when txdx=1, but ctsx =0.
communication processor module 16-262 mpc823e reference manual motorola communication 16 processor module sccs 16.9.17.2.2 delaying rts mode. sometimes the hdlc bus can be used in a configuration with a local hdlc bus and a standard transmission line that is not an hdlc bus. this situation is illustrated in figure 16-86. the local hdlc bus controllers do not communicate with each other, but with a station on the transmission line; yet the hdlc bus protocol is used to control access to the transmission line. normally, the rtsx pin goes active at the beginning of the opening flags first bit. although using the rtsx pin is not required, there is a mode on the mpc823e hdlc bus that delays the rtsx signal by one bit. this mode is selected with the brm bit in the psmrCscc hdlc register. delayed rtsx mode is useful when the hdlc bus connects multiple local nodes to a transmission line. if the transmission line driver has a one-bit delay, then the delayed rtsx line can be used to enable the output of the transmission line driver. the result is that the transmission line bits always drive clean and without any collisions. rtsx timing is illustrated in figure 16-87. figure 16-86. hdlc bus transmission line configuration local hdlc bus hdlc bus controller a hdlc bus controller b notes: 1. the txdx pins of slave devices should be configured to open-drain in the port c parallel i/o port. 2. the rtsx pins of each hdlc bus controller are configured to delayed rtsx mode. line driver rx tx rtsx rtsx en r +5 txdx rxdx ctsx txdx rxdx ctsx (1-bit delay)
communication processor module motorola mpc823e reference manual 16-263 communication 16 processor module sccs 16.9.17.2.3 using the time-slot assigner. sometimes the hdlc bus can be used in a configuration that has a local hdlc bus and a time-division multiplex transmission line that is not an hdlc bus. figure 16-88 illustrates such a case. the local hdlc bus controllers all communicate over time-slots. however, more than one hdlc bus controller is assigned to a given time-slot and the hdlc bus protocol controls access during that time-slot. figure 16-87. delayed rtsx mode figure 16-88. hdlc bus time-slot assigner transmission line configuration tclk txdx ctsx rtsx collision 1st bit 2nd bit 3rd bit rtsx active for only 2 bit times hdlc bus controller l1txdx l1rxdx a notes: 1. all tx pins of slave devices should be configured to open-drain in the port c parallel i/o port. 2. the tsa in the serial interface of each station is used to configure the preferred time-slot. 3. you can choose the number of stations to share a time-slot. in this example, two are used. rx tx local hdlc bus stations share time-slot n stations share time-slot m r +5 ctsx hdlc bus controller l1txdx l1rxdx b ctsx hdlc bus controller l1txdx l1rxdx c ctsx hdlc bus controller l1txdx l1rxdx d ctsx line driver
communication processor module 16-264 mpc823e reference manual motorola communication 16 processor module sccs if a serial communication controller is configured to operate using the time-slot assigner of the serial interface, then the data is received and transmitted using the l1txdx and l1rxdx pins. the collision sensing is still obtained from the individual serial communication controller ctsx pin, so the ctsx pin must be configured in port c to connect to the preferred serial communication controller. since a serial communication controller only receives clocks during its time-slot, the ctsx pin is only sampled during the transmit clock edges of the particular serial communication controller time-slot. 16.9.17.3 hdlc bus memory map and programming. the hdlc bus on the mpc823e is implemented using the sccx in hdlc mode with certain bits set. if you want to do otherwise, see section 16.9.16.5 programming the sccs in hdlc mode for information about hdlc mode programming. use the general sccx mode high and low registers (gsmr_x) described in section 16.9.2 the general sccx mode registers to program the hdlc bus controller as follows: 1. set the mode field to hdlc mode in the gsmr_l. 2. set the ctss field to 1 and all other bits to zero or default in the gsmr_h. 3. set the diag field to normal operation in the gsmr_l. 4. set the rdcr and tdcr bits to 1x clock in the gsmr_l. 5. set the tenc and renc bits to nrz in the gsmr_l. 6. clear the rtsm bit in the gsmr_h. 7. set the ent and enr bits in the gsmr_l. use the sccx protocol-specific mode register described in section 16.9.16.8 sccx hdlc mode register to program the hdlc bus controller as follows: 1. set the nof field as preferred. 2. set the crc field to 16-bit crc ccitt. 3. set the rte bit. 4. set the bus bit. 5. set the brm bit to 1 or zero. 6. set all other bits to zero or default. 16.9.17.3.1 hdlc bus controller programming example. except for the previously discussed gsmr_x and psmrCscc hdlc programming, use the example in section 16.9.16.14 scc2 hdlc programming example #1 .
communication processor module motorola mpc823e reference manual 16-265 communication 16 processor module sccs 16.9.18 the sccs in appletalk mode appletalk ? is a set of protocols developed by apple computer inc. to provide a lan service between macintosh computers and printers. although appletalk can be implemented over a variety of physical and link layers, including ethernet, the appletalk protocols have traditionally been more closely associated with one particular physical and link layer protocol called localtalk. localtalk refers to an hdlc-based link and physical layer protocol that runs at the rate of 230.4kbps. in this manual, the term appletalk controller refers to a support that the mpc823e provides for the localtalk protocol. the appletalk controller provides the required frame synchronization, bit sequence, preamble, and postamble onto standard hdlc frames. these capabilities, as well as the use of the hdlc controller in conjunction with dpll operation in fm0 mode, provide the proper connection formats to the localtalk bus. 16.9.18.1 operating the localtalk bus. a localtalk frame is basically a modified hdlc frame. the frame begins when a synchronization sequence greater than three bits is sent. this sequence consists of at least one logical 1 bit (fm0-encoded) followed by greater than two bit times of line idle with no particular maximum time specified. the idle time allows localtalk equipment to sense a carrier by detecting a missing clock on the line. the remainder of the frame is a typical half-duplex hdlc frame. two or more flags are sent, which allows for bit, byte, and frame delineation or detection. then, two bytes of address, destination, and source are transmitted, followed by a byte of control and 0 to 600 data bytes. next, two bytes of crc (described in section 16.9.16.8 sccx hdlc mode register ) are sent. the localtalk frame is then terminated by a flag and a restricted hdlc abort sequence. then the transmitters driver is disabled. the control byte within the localtalk frame indicates the type of frame. control byte values that range from 0x01 to 0x7f are data frames and control byte values that range from 0x80 to 0xff are control frames. there are four types of control frames: ? enqenquiry ? ackenquiry acknowledgment ? rtsrequest to send a data frame ? ctsclear to send a data frame figure 16-89. localtalk frame format sync seq abort sequence hdlc flags closing flag crc-16 dest addr source addr control byte data (optional) > 3 bits 2 or more bytes 1 byte 1 byte 1 byte 0C600 bytes 2 bytes 1 byte 12C18 ones
communication processor module 16-266 mpc823e reference manual motorola communication 16 processor module sccs frames are sent in groups called dialogs, which are handled by the software. for instance, to transfer a data frame, three frames are actually sent over the network. an rts frame (not to be confused with the rs-232 rtsx pin) is sent to request the network, then a cts frame is sent by the destination node, and the data frame is sent by the requesting node. these three frames comprise one possible type of dialog. once a dialog has begun, other nodes cannot start transmitting until the dialog is complete. frames within a dialog are transmitted with a maximum interframe gap (ifg) of 200 microseconds. although the localtalk specification does not state it, there is also a minimum recommended ifg of 50ms. dialogs must be separated by a minimum interdialog gap (idg) of 400ms. these gaps are implemented by the software. depending on the protocol, collisions must only be encountered during rts and enq frames. once frame transmission begins, it is fully transmitted, regardless of whether it collides with another frame. enq frames are infrequent and only sent when a node powers up and enters the network. a higher level protocol controls the uniqueness and transmission of enq frames. in addition to the frame fields, localtalk requires that the frame be fm0 (differential manchester space) encoded, which requires one level transition on every bit boundary. if the value to be encoded is a logic zero, fm0 requires a second transition in the middle of the bit time. the purpose of fm0 encoding is to avoid having to transmit clocking information on a separate wire. with fm0, the clocking information is present whenever valid data is present. 16.9.18.2 features. the following list summarizes the features of the serial communication controller in appletalk mode: ? superset of the hdlc controller features ? fm0 encoding/decoding ? programmable transmission of sync sequence ? automatic postamble transmission ? reception of sync sequence does not cause extra cdx interrupts ? reception is automatically disabled while transmitting a frame ? transmit-on-demand feature that expedites frames ? connects directly to an rs-422 transceiver
communication processor module motorola mpc823e reference manual 16-267 communication 16 processor module sccs 16.9.18.3 connecting to appletalk. the mpc823e connects to localtalk and, using the txdx, rtsx , and rxdx pins, is an interface for the rs-422 transceiver. the rs-422, in turn, is an interface for the localtalk connector. although it is not shown, a passive rc circuit is recommended between the transceiver and connector. figure 16-90 illustrates how to connect the mpc823e to localtalk. the 16x multiplier of a 3.686mhz clock can be generated from an external frequency source or from one of the baud rate generators if the resulting output frequency is close to a multiple of the 3.686mhz frequency. the mpc823e asserts the rtsx signal throughout the duration of the frame so that rtsx can be used to enable the rs-422 transceiver. mpc823e figure 16-90. connecting the mpc823e to appletalk mpc823 rs-422 mini-din 8 scc txdx rtsx rxdx tx data rx data tx enable 16 ones (abort) crc-16 stored in transmit buffer stored in receive buffer rtsx txdx dest addr source addr control byte data standard hdlc frame handling 6-bit sync seq two hdlc flags closing flag
communication processor module 16-268 mpc823e reference manual motorola communication 16 processor module sccs 16.9.18.4 programming the sccs in appletalk mode. you can implement the sccx appletalk controller by setting certain bits in the sccx hdlc controller. otherwise, you must consult section 16.9.17 the hdlc bus controller for detailed information about how to program the sccx hdlc controller. you can use a serial communication controller gsmr, psmr, or todr to program the appletalk controller. use the general sccx mode high and low registers (gsmr_x) described in section 16.9.2 the general sccx mode registers to program the appletalk controller with the following steps: 1. set the mode field in the gsmr_l to appletalk. 2. set the ent and enr bits in the gsmr_l. 3. set the diag field in the gsmr_l for normal operation, with the cdx and ctsx pins grounded or configured for parallel i/o. this causes cdx and ctsx to be internally asserted to a serial communication controller. 4. set the rdcr and tdcr fields in the gsmr_l to a 16 clock. 5. set the tenc and renc fields in the gsmr_l to fm0. 6. set the tend bit in the gsmr_l to 0. 7. set the tpp field in the gsmr_l to 11. 8. set the tpl field to 000 to transmit the next frame with no synchronization sequence and to 001 to transmit the next frame with the localtalk synchronization sequence. for example, data frames do not require a preceding synchronization sequence. this field may be modified on-the-fly if the appletalk protocol is selected. 9. set the tinv and rinv bits in the gsmr_l to zero. 10. set the tsnc field in the gsmr_l to 10. 11. set the edge field to 0. 12. set the rtsm bit in the gsmr_h to 0. 13. set all other bits to 0 or default. use the sccx protocol-specific mode register described in section 16.9.3 protocol- specific mode register to program the appletalk controller with the following steps: 1. set the nof field to 0001 (binary) giving two flags before frames (one opening flag and one additional flag). 2. set the crc field to 16-bit crc-ccitt. 3. set the drt bit to 1. 4. set all other bits to 0 or default. use the transmit-on-demand register described in section 16.9.5 transmit-on-demand register to expedite a transmit frame by setting the tod bit to 1.
communication processor module motorola mpc823e reference manual 16-269 communication 16 processor module sccs 16.9.18.5 sccx appletalk programming example. except for the previously discussed register programming, use the example in section 16.9.16.14 scc2 hdlc programming example #1 . 16.9.19 the sccx in asynchronous hdlc mode asynchronous hdlc is a frame-based protocol that uses hdlc framing techniques in conjunction with uart-type characters. this protocol is typically used as the physical layer for the point-to-point protocol (ppp) and the infrared link access protocol (irlap). even though asynchronous hdlc can be implemented in conjunction with the core, it is more efficient and less computationally intensive to allow the communication processor module to perform the framing and transparency functions. a serial communication controller in async hdlc mode is also referred to as a sccx async hdlc controller. 16.9.19.1 features. the following list summarizes the main features of the sccx in asynchronous hdlc mode: ? flexible data buffer structure that allows an entire frame or a section of a frame to be transmitted and received ? separate interrupts for received frames and transmitted buffers ? automatic crc generation and checking ? support for nonmultiplexed serial interface control signals ? automatic generation of opening and closing flags ? reception of frames with only one shared flag ? automatic generation and stripping of transparency characters according to rfc 1549 using transmit and receive control character maps ? programmable opening flag, closing flag, and control escape characters ? automatic transmission of the abort sequence after the stop transmit command is issued ? automatic transmission of idle characters between frames 16.9.19.2 sccx async hdlc channel frame transmission process. the sccx async hdlc controller, is designed to operate with a minimum amount of intervention from the core and operates similar to the sccx in hdlc mode. when the core enables the transmitter and sets the r bit in the first transmit buffer descriptor, the sccx async hdlc controller fetches the data from memory and starts transmitting the frame. when the controller reaches the end of the current buffer descriptor, the crc and closing flag are appended if the l bit in the tx buffer descriptor is set. if the cm bit is clear, the asynchronous hdlc transmitter writes the frame status bits into the buffer descriptor and clears the r bit. if the i bit is set, the controller sets the txb bit in the scceCasync hdlc register. thus, the i bit can be used to generate an interrupt after each buffer, after a group of buffers, or after each complete frame has been transmitted.
communication processor module 16-270 mpc823e reference manual motorola communication 16 processor module sccs if the cm bit in the tx buffer descriptor is set, the sccx async hdlc controller writes the signal unit status bits into the buffer descriptor after transmission, but it does not clear the r bit. the sccx async hdlc controller then proceeds to the next tx buffer descriptor in the table. if it is not ready, it waits until it is ready. while the sccx async hdlc controller is transmitting data from the buffers, it automatically performs the transparency encoding specified by the protocol. this encoding is described in section 16.9.19.4 transmitter transparency encoding . you must issue the stop transmit command to rearrange the transmit queue before the communication processor module finishes transmitting all the buffers. this can be useful when transmitting expedited data prior to previously linked buffers or for error situations. when the sccx async hdlc controller receives the stop transmit command, it stops transmitting and sends the abort sequence. it then transmits idle characters until the restart transmit command is given, at which point it resumes transmission with the next tx buffer descriptor. 16.9.19.3 sccx async hdlc channel frame reception process. the sccx async hdlc receiver is designed to operate with a minimum amount of intervention from the core and can decode the transparency characters, check the crc of the frame, and detect errors on the line and in the controller. when the core enables the receiver, the receiver waits for data to be present on the line. when the receiver detects a data byte of the incoming frame that was preceded by one or more opening flags, the sccx async hdlc controller fetches the next buffer descriptor and if the e bit is set it starts transferring the incoming frame into the buffer descriptor associated data buffer. when the data buffer is full, the sccx async hdlc controller clears the e bit in the buffer descriptor. if the incoming frame exceeds the length of the data buffer, the sccx async hdlc controller fetches the next buffer descriptor in the table and, if empty, continues transferring the rest of the frame into the associated data buffer. during this process, the receiver automatically decodes the transparency character required of the sccx async hdlc protocol. this procedure is described in detail in section 16.9.19.5 receiver transparency decoding . when the frame ends, the controller checks the incoming crc field and writes it to the data buffer. it then writes the length of the entire frame to the data length field of the last buffer descriptor. the sccx async hdlc controller sets the l bit, writes the frame status bits into the buffer descriptor, and clears the e bit if the cm bit is clear. it then sets the rxf bit in the scceCasync hdlc register, which indicates that a frame has been received and is in memory. the sccx async hdlc controller then waits for the start of the next frame which may or may not have an opening flag. figure 16-91. async hdlc frame structure bof eof fcs i c a 8 bits 8 bits 8 bits 8 bits 2 * 8 bits m * 8 bits
communication processor module motorola mpc823e reference manual 16-271 communication 16 processor module sccs 16.9.19.4 transmitter transparency encoding. the sccx async hdlc controller maps characters according to the rfc 1549 standard. it examines the outgoing data bytes and performs a transparency algorithm on a given byte if one of the following conditions apply: ? the byte is a flag (0x7e-ppp, 0xc0/0xc1-irlap) ? the byte is a control-escape character (0x7d) ? the byte has a value between 0x00 and 0x1f and the corresponding bit in the tx control character table is set when a condition applies, a two-byte sequence is transmitted in place of the byte. the sequence consists of the control-escape character (0x7d) followed by the original byte exclusive-ored with 0x20. 16.9.19.5 receiver transparency decoding. the sccx async hdlc controller maps characters according to the rfc 1549. to recover the original data, it examines the incoming data bytes and performs the transparency algorithm in the following ways: ? discards any character that has its corresponding bit set in the rx control character map. this character is assumed to have been inserted in the character stream by an intermediate device and is not part of the originally transmitted frame. ? reverses the transmission transparency sequence by discarding a received control-escape character (0x7d) and exclusive-oring the following byte with 0x20 before performing the crc calculation and writing the byte into memory.
communication processor module 16-272 mpc823e reference manual motorola communication 16 processor module sccs figure 16-92 illustrates the algorithms, since some cases are not addressed in rfc 1549. figure 16-92. reception flowchart char 3 = closing flag ? char ? 0x20 xor_next =0 char 3 0x20 mapped ? char 3 = ctrl esc? write char to buffer xor_next=1 xor_next ? exit char 3 = closing flag ? abort exit rx char end of frame f f f f f f
communication processor module motorola mpc823e reference manual 16-273 communication 16 processor module sccs 16.9.19.6 exceptions to rfc 1549. the following beheviors do not conform to rfc 1549. ? if an 0x7d is followed by a control character and the control character is not mapped, the control character itself is modified by the xor process. the crc check must catch this exception. this is a case where the transmitter control character table differs from the receiver. ? in addition to the abort sequence, frames are terminated by the following errors: o carrier detect lost o receiver overrun o framing error o break sequence ? if the invalid sequence is received, the first control escape character is discarded, and the second is unconditionally exclusive-ored with 0x20. this sequence is stored in the buffer descriptor as 0x5d. 16.9.19.7 sccx async hdlc implementation. the following behaviors represent the key aspects of the sccx async hdlc controller. ? flag sequencewhen transmitting, the controller automatically generates the opening and closing flag for the frame. when receiving, the controller strips off the opening and closing flag before writing the frame to memory. it receives frames with only one shared flag between them and ignores multiple flags between frames. ? address fieldthe address field is neither generated nor examined by the microcode while transmitting or receiving. the address field of the frame must be included in the data buffer that the transmit buffer descriptor points to. any address field compression, expansion, or checking must be performed by the core. ? control fieldthe control field is neither generated nor examined by the microcode while transmitting or receiving. the control field of the frame must be included in the data buffer that the transmit buffer descriptor points to. any control field compression, expansion, or checking must be performed by the core. ? frame check sequencewhen transmitting, the frame check sequence (crc) is automatically appended to the end of the frame before the closing flag is transmitted. the frame check sequence is generated on the original frame before the transparency characters, start/stop bits, or flags are added. the controller uses a 16-bit crc-ccitt polynomial. when receiving, the frame check sequence is automatically checked. the frame check sequence is calculated after any transparency characters, start/stop bits, and flags are removed. the controller uses a 16-bit crc-ccitt polynomial. ? encodingthe sccx async hdlc controller only supports 8 data bits, one start bit, one stop bit, and no parity. this must be programmed in the psmrCscc async hdlc register so that bits 2 and 3 are set to 1 for proper operation. ? time-fill (idling)when transmitting, the sccx async hdlc controller transmits idle characters when no data is available for transmission. when receiving, the sccx async hdlc controller ignores idle characters.
communication processor module 16-274 mpc823e reference manual motorola communication 16 processor module sccs 16.9.19.8 sccx async hdlc parameter ram memory map. when configured as an sccx async hdlc controller, a serial communication controller overlays the structure used in table 16-24 with the sccx async hdlc parameters described in table 16-28. ? c_maskthis value must be initialized with 0x0000f0b8. ? c_presthis value must be initialized with 0x0000ffff. ? bofthis value must be initialized to the beginning of the flag character (ppp is 0x7e and irlap is 0xc0). ? eofthis value must be initialized to the end of the flag character (ppp is 0x7e and irlap is 0xc1). ? escthis value must be initialized to the control escape character (ppp is 0x 7d and irlap is 0x7d). ? reservedthese areas are temporary storage locations for the microcode. they must not be initialized or modified. ? zeroyou must set this field to zero. ? rfthrthe received frames threshold indicates how many frames are received before the rxf bit is set in the scceCasync hdlc register. table 16-28. sccx async hdlc parameter ram memory map address name width description sccx base+34 c_mask word crc constant sccx base+38 c_pres word crc preset sccx base+3c bof half-word beginning of flag character sccx base+3e eof half-word end of flag character sccx base+40 esc half-word control escape character sccx base+42 res half-word reserved sccx base+44 res half-word reserved sccx base+46 zero half-word reserved sccx base+48 res half-word reserved sccx base+4a rfthr half-word received frames threshold sccx base+4c res half-word reserved sccx base+4e res half-word reserved sccx base+50 txctl_tbl word tx control character mapping table sccx base+54 rxctl_tbl word rx control character mapping table sccx base+58 nof half-word number of opening flags sccx base+5a res half-word reserved note: you are only responsible for initializing the items in bold. sccx base = (immr & 0xffff0000) + 0x3d00 (scc2 ) and 0x3e00 (scc3).
communication processor module motorola mpc823e reference manual 16-275 communication 16 processor module sccs ? txctl_tblthe transmit control character table stores the bit array used for the tx control character table. each bit corresponds to a character that must be mapped according to rfc 1549. if the bit is set, the character corresponding to that bit is mapped and if the bit is not set, the corresponding character is not mapped. the transmit control character table must be initialized to zero for irlap. ? rxctl_tblthe receive control character table stores the bit array used for the rx control character table. each bit corresponds to a character that must be mapped according to rfc 1549. if the bit is set, the character corresponding to that bit is discarded if received and if the bit is not set, the corresponding character is received normally. the receive control character table must be initialized to zero for irlap. ? nofthis entry must be initialized to the number of opening flags to be transmitted at the beginning of a frame. a value of n corresponds to n +1 flags. txctl_tbl byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 value ox1f ox1e ox1d ox1c ox1b ox1a ox19 ox18 ox17 ox16 ox15 ox14 ox13 ox12 ox11 ox10 byte 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 value ox9 ox8 ox7 ox6 ox5 ox4 ox3 ox2 ox1 ox0 oxo5 oxo4 oxo3 oxo2 oxo1 oxoo rxctl_tbl byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 value ox1f ox1e ox1d ox1c ox1b ox1a ox19 ox18 ox17 ox16 ox15 ox14 ox13 ox12 ox11 ox10 byte 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 value ox9 ox8 ox7 ox6 ox5 ox4 ox3 ox2 ox1 ox0 oxo5 oxo4 oxo3 oxo2 oxo1 oxoo
communication processor module 16-276 mpc823e reference manual motorola communication 16 processor module sccs 16.9.19.9 configuring the sccx async hdlc parameters. the sccx async hdlc parameters can be configured as described in section 16.9 the serial communication controllers through section 16.9.8 handling interrupts in the sccs , except for the changes in the following registers. when you are in asynchronous hdlc mode, some of the bits in the gsmr_x and general dsr have different meanings. for the sccx in async hdlc mode, the general sccx mode high and low register (gsmr_x) bit descriptions remain the same, except for: ? rfwrx fifo width (gsmr_h) 0 = must not be used. 1 = low-latency operation. the rx fifo is 8 bits wide and the receive fifo is one quarter its normal size (8 bytes). this allows data to be written to the data buffer each time a character is received, without forcing you to wait for 32 bits to be received. you must choose this configuration for character-oriented protocols like uart and asynchronous hdlc. ? tdcrtransmit divide clock rate (gsmr_l) these bits determine the divider rate of the transmitter. if the dpll is not used, you must choose the 1 value. in asynchronous uart or hdlc mode, you must choose 8 , 16 , or 32 . you must program these bits to equal the rdcr field in most applications. 00 = do not use. 01 = 8 clock mode (do not use for irlap). 10 = 16 clock mode. 11 = 32 clock mode (do not use for irlap). ? rdcrreceive dpll clock rate (gsnr_l) these bits determine the divider rate of the receive dpll. if the dpll is not used, you must choose the 1 value. in asynchronous uart or hdlc mode, you must choose 8 , 16 , or 32 . you must program these bits to equal the tdcr field in most applications. 00 = do not use. 01 = 8 clock mode (do not use for irlap). 10 = 16 clock mode. 11 = 32 clock mode (do not use for irlap). the data synchronization register (dsr) is reserved in asynchronous hdlc mode. it must be set to 0x7e7e.
communication processor module motorola mpc823e reference manual 16-277 communication 16 processor module sccs 16.9.19.10 sccx async hdlc commands. you can program the cpm command register (cpcr) with the following commands to transmit data. see section 16.2.6.1 cpm command register for additional information. after the hardware or software is reset and the channel is enabled by the sccmCasync hdlc register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table every eight transmit bit times or immediately if the tod bit of the todr is set. ? stop transmit this command transmits the asynchronous hdlc abort sequence (pppC0x7d ;0x7e, irlapC0x7d ;0xc1) and disables the transmission of data. if the sccx async hdlc controller receives this command during frame transmission, the abort sequence is put into the fifo and the transmitter does not try to send any more data from the current tx buffer descriptor. the controller also does not advance to the next tx buffer descriptor. you determine the buffer descriptor that is terminated by examining the tbptr entry in the sccx parameter ram table. however, no new buffer descriptor is accessed for this channel. ? graceful stop transmit this command is not supported by the sccx async hdlc controller. ? restart transmit this command reenables the transmission of characters on the transmit channel and the sccx async hdlc controller expects it after a stop transmit command or transmitter error. the controller continues transmitting from the first character in the current transmitter buffer descriptor in the channels transmit buffer descriptor table. ? init tx parameters this command initializes all the transmit parameters in this serial channels parameter ram to their reset state. it must be issued before the transmitter is enabled and must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. note: unlike the other mpc823e protocols, the sccx async hdlc controller does not flush the fifo because of the stop transmit command. a maximum of 32 characters can be transmitted before an abort sequence. however, this can be avoided by programming tfl to 1 in the gsmr_h register.
communication processor module 16-278 mpc823e reference manual motorola communication 16 processor module sccs you can program the cpm command register (cpcr) with the following commands to receive data. after the hardware or software is reset and the channel is enabled by its sccmCasync hdlc register, the channel is in receive enable mode and uses the first buffer descriptor in the table. ? enter hunt mode this command is used to force the sccx async hdlc controller to close the current rx buffer descriptor (if it is being used) and enter hunt mode. the controller continues receiving after it finds a frame preceded by one or more opening flags. ? close rx bd this command is not supported by the sccx async hdlc controller. ? init rx parameters this command initializes all the receive parameters in this serial channels parameter ram to their reset state and must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters. 16.9.19.11 sccx async hdlc controller errors. the sccx async hdlc controller reports frame reception and transmission error conditions using the channel buffer descriptors and the scceCasync hdlc register. the following transmission error can be detected by the sccx async hdlc controller. ? cts lost during frame transmission errorwhen this error occurs, the channel stops transmitting the buffer, closes it, sets the ct bit in the tx buffer descriptor and the txe bit in the scceCasync hdlc. the channel continues transmitting from the next tx buffer descriptor after the restart transmit command is issued. the following reception errors can be detected by the sccx async hdlc controller. ? overrun errorthe sccx async hdlc controller maintains an internal 8-byte fifo when a serial communication controller receives data. a receive overrun occurs when the communication processor module is unable to keep up with the data rate or the sdma channel is unable to write the received data to memory. the previous data byte and the frame status are lost. the controller closes the buffer with the ov bit in the buffer descriptor set and sets the rxf bit in the scceCasync hdlc register. the receiver then searches for the next frame. ? cd lost during frame reception errorwhen this error occurs, the channel stops receiving frames, closes the buffer, and sets the cd bit in the buffer descriptor and the rxf bit in the scceCasync hdlc register. this error has the highest priority. the rest of the frame is lost and other errors are not checked in that frame. the receiver then searches for the next frame once the cd signal is reasserted. ? abort sequence errorthis error occurs when the sccx async hdlc controller receives an abort sequence. at that time, the channel closes the buffer by setting the ab bit in the rx buffer descriptor and sets the rxf bit in the scceCasync hdlc register. the crc error status condition is not checked on aborted frames. if the abort sequence is received and no frame is currently being received, the next buffer descriptor is opened and then closed with the ab bit set.
communication processor module motorola mpc823e reference manual 16-279 communication 16 processor module sccs ? crc errorwhen this error occurs, the channel writes the received cyclic redundancy check to the data buffer, closes the buffer, and sets the cr bit in the rx buffer descriptor and the rxf bit in the scceCasync hdlc register. after receiving a signal unit with this error, the receiver prepares to receive the next frame. ? break sequence received errorthis error occurs when the uart receiver finds the first character of a break sequence. the channel closes the buffer by setting the brk bit in the rx buffer descriptor and the rxf bit in the scceCasync hdlc register. the crc error status condition is not checked. the brks bit is set in the scceCasync hdlc register when the first break of a sequence is found and brke is set when an idle bit is received after a break sequence. 16.9.19.12 programming the sccx async hdlc controller. 16.9.19.12.1 scc async hdlc mode register. when a serial communication controller is in asynchronous hdlc mode, the 16-bit, memory-mapped, read/write protocol-specific mode register is referred to as the sccx async hdlc mode (psmrCscc async hdlc) register. it controls asynchronous hdlc mode-specific parameters. since each protocol has specific requirements, the psmr bits are different for each implementation. flcflow control 0 = normal operation. 1 = asynchronous flow control. when the cts pin is negated, the transmitter stops at the end of the current character. if cts is negated past the middle of the current character, the next full character can be sent and transmission stops. when cts is asserted once more, transmission continues where it left off and no cts lost error is reported. no characters, except idles, are transmitted while cts is negated. bits 1 and 4C15reserved these bits are reserved and must be set to 0. chlncharacter length for asynchronous hdlc and irlap modes, these bits must be set to 1. psmrCscc async hdlc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field flc res chln reserved reset 00 0 0 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa28
communication processor module 16-280 mpc823e reference manual motorola communication 16 processor module sccs 16.9.19.12.2 sccx async hdlc receive buffer descriptor. the sccx async hdlc controller uses the receive (rx) buffer descriptor to report information about each buffers received data. an example of the rx buffer descriptor process is illustrated in figure 16-80. the first word of the rx buffer descriptor contains control and status bits. bit 0 is set by the core when the buffer is available to the sccx async hdlc controller and it is cleared by the controller when the buffer is full. eempty 0 = the data buffer associated with this buffer descriptor is filled with data or stops receiving because an error condition occurred. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor again as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 7, and 10C11reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table are programmable and determined only by the w bit and overall space constraints of the dual-port ram. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi lf cm res brk bof res ab cr ov cd offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-281 communication 16 processor module sccs iinterrupt 0 = the rxb bit in the scceCasync hdlc register is not set after this buffer is used, but rxf operation is unaffected. 1 = the rxb or rxf bit in the scceCasync hdlc register is set when this buffer is used by the sccx async hdlc controller. llast in frame this bit is set by the sccx async hdlc controller when this buffer is the last in a frame. if a closing flag or error is received, one or more of the brk, cd, ov, and ab bits are set. the sccx async hdlc controller writes the number of frame octets to the data length field. 0 = this buffer is not the last one in a frame. 1 = this buffer is the last one in a frame. ffirst in frame this bit is set by the sccx async hdlc controller when this buffer is the first in a frame. 0 = the buffer is not the first one in a frame. 1 = the buffer is the first one in a frame. cmcontinuous mode 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the buffer descriptor is accessed by the communication processor module. however, the e bit is cleared if an error other than crc occurs during reception, regardless of how the cm bit is set. brkbreak character received this bit indicates that the current frame is closed when a break character is received. bofbeginning of frame encountered this bit indicates that the current frame is closed when a bof character is received instead of the expected eof. abrx abort sequence this bit indicates that an asynchronous hdlc abort sequence or framing error is received to terminate this frame. crrx crc error this bit indicates that this frame contains a crc error. the received crc bytes are always written to the receive buffer. ovoverrun this bit indicates that a receiver overrun has occurred during frame reception.
communication processor module 16-282 mpc823e reference manual motorola communication 16 processor module sccs cdcarrier detect lost this bit indicates that the carrier detect signal is negated during frame reception. data length this field represents the number of octets the communication processor module writes into this buffer descriptor data buffer once the buffer descriptor is closed. when this buffer descriptor is the last one in the frame, data length contains the total number of frame octets. the actual amount of memory allocated for this buffer must be greater than or equal to the contents of the mrblr. rx data buffer pointer this field always points to the first location of the associated data buffer and can reside in internal or external memory. 16.9.19.12.3 sccx async hdlc transmit buffer descriptor. data is sent to the sccx async hdlc controller for transmission on an sccx channel by arranging it in buffers referenced by the channel transmit (tx) buffer descriptor table. using the buffer descriptors, the sccx async hdlc controller confirms transmission or indicates error conditions so that the core will know the buffers have been serviced. note: if the received frame has a length that is an exact multiple of the mrblr, the buffer descriptor with the l bit set does not actually have any characters in it and the data length field contains a value equal to the sum of the data length fields of the other buffer descriptors in the frame. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi l res cm res ct offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-283 communication 16 processor module sccs rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered. 1 = the data buffer, which you have prepared for transmission, is not transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1, 5, and 7C11reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table are programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0= the txb bit in the scceCasync hdlc register is not set after this buffer is used. 1= the txb bit in the scceCasync hdlc register is set when this buffer is transmitted by the sccx async hdlc controller. llast 0= this is not the last buffer in the current frame. 1= this is the last buffer in the current frame. the proper crc and closing flag are transmitted after the last byte is transmitted. cmcontinuous mode 0 = normal operation. 1 = the r bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted the next time the communication processor module accesses this buffer descriptor. however, the r bit is cleared if an error occurs during transmission, regardless of how the cm bit is set. ctcts lost i n nmsi mode, this bit indicates that cts is lost during frame transmission. if data from more than one buffer is currently in the fifo when this error occurs, this bit is set in the currently open tx buffer descriptor. these bits are written by the sccx async hdlc controller after it finishes transmitting the associated data buffer.
communication processor module 16-284 mpc823e reference manual motorola communication 16 processor module sccs data length this field represents the number of bytes the sccx async hdlc controller must transmit from this buffer descriptor data buffer. it is never modified by the communication processor module. the value of this field must be greater than zero. these bits are written by the sccx async hdlc controller after it finishes transmitting the associated data buffer. tx data buffer pointer this field contains the address of the associated data buffer, can be even or odd, and can reside in internal or external memory. the value of this field is never modified by the communication processor module. these bits are written by the sccx async hdlc controller after it finishes transmitting the associated data buffer. 16.9.19.12.4 sccx async hdlc event register. when a serial communication controller is in asynchronous hdlc mode, the 16-bit memory-mapped sccx event register is referred to as the sccx asynchronous hdlc event (scceCasync hdlc) register. since each protocol has specific requirements, the scce bits are different for each implementation. this register is used to generate interrupts and report events recognized by the sccx async hdlc channel. when an event is recognized, the sccx async hdlc controller sets the corresponding bit in the scceCasync hdlc register. interrupts generated by this register can be masked by the sccmCasync hdlc register. a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. however, all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared at reset and can be read at any time. bits 0C2, 5C6, and 8reserved these bits are reserved and must be set to 0. glrglitch on rx if set, this bit indicates that a serial communication controller has found a glitch on the receive clock. gltglitch on tx if set, this bit indicates that a serial communication controller has found a glitch on the transmit clock. scceCasync hdlc bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt reserved idl res brke brks txe rxf bsy txb rxb reset 0 00 0 000000000 addr (immr & 0xffff0000) + 0xa30
communication processor module motorola mpc823e reference manual 16-285 communication 16 processor module sccs idlidle sequence status changed this bit indicates that a change in the status of the serial line has occurred. the real-time status of the line can be read in the sccsCasync hdlc register. txetx error this bit indicates that an error has occurred on the transmitter channel. brkebreak end this bit indicates that the end of a break sequence has been found. this indication is set when one idle bit is received after a break sequence. brksbreak start this bit indicates that a break character has been received. this is the first break of a break sequence. you will not receive multiple brks events if a long break sequence is detected. rxfrx frame this bit indicates that the sccx async hdlc channel has received a complete frame. this bit is set no sooner than two bit times after the last bit of the closing flag is received. bsybusy condition this bit indicates that a frame has been received and discarded due to a lack of buffers. txbtransmit buffer this bit indicates that a buffer with its i bit set has been transmitted on the sccx async hdlc channel. this bit is set no sooner than when the last bit of the closing flag begins its transmission if the buffer is the last one in the frame. otherwise, this bit is set after the last byte of the buffer is written to the transmit fifo. rxbrx buffer this bit indicates that a buffer (that is not the last in the frame with its i bit set) has been received over the sccx async hdlc channel.
communication processor module 16-286 mpc823e reference manual motorola communication 16 processor module sccs 16.9.19.12.5 differences between hdlc and async hdlc. there are four main differences between the hdlc and async hdlc modes of operation: ? there is no maximum received frame length counter in the async hdlc controller. therefore, the controller receives all characters between opening and closing flags and there is no way to stop the controller from writing to memory. this in no way affects the number of bytes received into a specific buffer descriptor. it just means that a frame is received into memory in its entirety. ? if an error prevents a frame from being received, the character received at the moment the error occurred is not written into memory. for example, if a cd lost error occurred, the frame is closed and the partial character is not written to memory. thus, the octet count only reflects the number of bytes written to memory. ? the automatic error counters in hdlc mode have not been implemented in asynchronous hdlc mode. ? noisy characters (those whose three samples are not the same) are not accounted for in the async hdlc controller. it is assumed that the crc catches any data integrity problems. 16.9.19.12.6 sccx async hdlc programming guide. the following is an initialization sequence guide for a serial communication controller in asynchronous hdlc mode. 1. initialize the sdcr. 2. in nmsi mode, configure the port a pins to enable rxdx and txdx. 3. configure a baud rate generator to generate appropriate channel clocking frequency. 4. program the sicr to route the baud rate generator clocking to a serial communication controller that is in asynchronous hdlc mode. 5. select whether the channel is using the time-slot assigner or the nmsi pins in the sicr. 6. write rbase and tbase in the sccx parameter ram to point to the first rx and tx buffer descriptor. 7. issue the init rx and tx params command for the serial communication controller. 8. program the rfcr and tfcr. 9. write the mrblr with the maximum receiver buffer size. 10. write c_mask and c_pres with the standard values. 11. write the zero register to 0x0000. 12. program the rfthr to the number of frames that must be received before an interrupt is generated. note: the graceful stop transmit command is not supported by the async hdlc controller.
communication processor module motorola mpc823e reference manual 16-287 communication 16 processor module sccs 13. program the transmit and receive control character tables. 14. initialize all rx buffer descriptors. 15. initialize all tx buffer descriptors. 16. clear the scceCasync hdlc register by writing 0xffff to it. 17. program the sccmCasync hdlc register with the proper mask to allow all preferred interrupts. 18. program the gsmr_h register. 19. program the gsmr_l register to asynchronous hdlc mode, but do not turn on the transmitter or receiver. 20. set the psmrCscc async hdlc appropriately. 21. turn on the transmitter and receiver in the gsmr_l register by setting the ent and enr bits. 16.9.20 the scc2 in irda mode irda is a family of specifications intended to facilitate the interconnection of computers and peripherals using a directed half duplex serial infrared physical communications medium. the infrared data association (irda) physical layer standard version 1.1 specifies three modes of operation, each one with a distinct modulation scheme and signaling rate. ? low-speed2.4kb/s to 115.2kb/s ? middle-speed0.576mb/s or 1.152mb/s ? high-speed4mb/s mpc823e figure 16-93. serial irda link note: serial communication controller 3 (scc3) does not operate in irda mode. ir transmit encoder ir receive decoder encoder/ decoder module ir transducer module output driver&led detector & receiver ir out ir in scc2 txd2 rxd2
communication processor module 16-288 mpc823e reference manual motorola communication 16 processor module sccs 16.9.20.1 low-speed irda protocol. the low-speed irda protocol consists of a data link layer and a physical layer. ? the data link layer is based on a preexisting async hdlc protocol standard. see section 16.9.19 the sccx in asynchronous hdlc mode for more details. 0xc0 is used as a start flag and 0xc1 is used as an end flag. each character is compromised out of a start bit, 8 data bits, no parity bit and ending with a stop bit, as shown in figure 16-94. ? the physical layer defines the electrical parameters of the signals between the encoder/decoder module and the infrared transducer module. the signal waveform is shown in figure 16-94. for all signaling rates up to and including 115.2kb/s, the minimum pulse duration is the same 3 / 16 of the bit duration for the 115.2kb/s signal (minus a protocol-defined tolerance). the maximum pulse duration is 3 / 16 of the bit duration (plus a protocol-defined tolerance). figure 16-94. low-speed irda data format 0 101 00 11 0 1 start bit data bits stop bit uart frame infra - red frame 3/16 bit time (a) (b)
communication processor module motorola mpc823e reference manual 16-289 communication 16 processor module sccs 16.9.20.2 middle-speed irda protocol. the middle-speed irda protocol consists of a data link layer and a physical layer. ? the data link layer is derived from the preexisting synchronous hdlc protocol standard. the frame format follows the standard hdlc format except that it requires two start flags. the frame consists of two start flags, an address field, a control field, an information field, a frame check sequence field and minimum of one ending flag. 0x7e is used for the start flag as well for the end flag. ? the physical layer defines the electrical parameters of the signals between the encoder/decoder module and the infrared transducer module. the signal waveform is shown in figure 16-96. for 0.576 and 1.152mb/s, the minimum and maximum pulse duration are the nominal 1 / 4 of the bit duration (plus or minus the protocol-defined tolerance). figure 16-95. middle speed packet format figure 16-96. middle-speed irda data format start flag 1 byte start flag 1 byte address 1 byte control 1 byte information n bytes crc 2 bytes end flag 1 byte 10100110 data bits 1/4 bit time (a) (b)
communication processor module 16-290 mpc823e reference manual motorola communication 16 processor module sccs 16.9.20.3 high-speed irda protocol. the high-speed irda protocol is derived from the preexisting sccx transparent protocol standard. 16.9.20.3.1 4ppm data encoding. pulse position modulation (ppm) encoding is achieved by defining a data symbol duration (dt) and subsequently subdividing dt into a set of equal time slices called chips. in ppm schemes, each chip position within a data symbol represents one of the possible bit combinations. each chip has a duration of ct given by ct = dt/base. in this formula base refers to the number of pulse positions or chips in each data symbol. the base for high-speed irda protocol is defined as four and the resulting modulation scheme is four-pulse position modulation (4ppm). the data rates of a irda ppm system are defined as 4.0mb/s. the resulting values for ct and dt are as follows: ? dt = 500 ns ? ct = 125 ns the figure below illustrates a data symbol field and its enclosed chip durations for a 4ppm scheme. because there are four unique chip positions within each symbol in 4ppm, four independent symbols exist in which only one chip is logically a one while other chips are logically a zero. these four unique symbols are the only legal data symbols (dd) allowed in 4ppm. each data symbol represents two bits of payload data, or a single data bit pair (dbp), so that a byte of payload data can be represented by four data symbols in sequence. the following table defines the chip pattern representation of the four unique data symbols defined for 4ppm. figure 16-97. one complete symbol data bit pair 4ppm data symbol 00 1000 01 0100 10 0010 11 0001 chip1 chip2 chip3 chip4
communication processor module motorola mpc823e reference manual 16-291 communication 16 processor module sccs logical 1 represents a chip duration when the transmitting led is emitting light, while logical 0 represents a chip duration when the led is off. data encoding for transmission is done lsb first. the 4ppm data encoding defines only the legal encoded payload data symbols. all other 4-chip combinations are by definition illegal symbols for encoded payload data. some of these illegal symbols are used in the definition of the packet envelope (preamble, start flag, stop flag) because they are unambiguously not data. 16.9.20.3.2 data link layer. the data link layer protocol defines the following packet format. the preamble (pa) field is used by the receiver to establish bit synchronization. the pa field consists of exactly sixteen repeated transmissions of the following stream of symbols. on the receive side, the pa field does not need to be valid in the received packet. after the pa field, the receiver starts searching for the start flag (sta) to establish symbol synchronization. after the start flag is received, the receiver can begin interpreting the data symbols in the link layer frame. the start flag consists of exactly one transmission of the following stream of symbols. figure 16-98. high-speed packet format figure 16-99. preamble field symbol format figure 16-100. start flag symbol format pa sta sto frame link layer 1000 0000 1010 1000 0000 1100 0000 1100 0110 0000 0110 0000
communication processor module 16-292 mpc823e reference manual motorola communication 16 processor module sccs the link layer frame generally consists of the address, control, data and crc32 fields. the irda transmitter decodes the packet bits into 4ppm format. the 4ppm encoding will be described later. the receiver is responsible to decode the incoming data frame into the regular bit format and to deliver it to the software. the receiver continues to receive and interpret data until the stop flag (sto) is recognized. a stop flag indicates the end of frame. the stop flag consists of exactly one transmission of the following stream of symbols. the physical layer defines the electrical parameters of the signals between the encoder/decoder module and the ir transducer module. all frame envelope patternspa, sta, and stoare transmitted as is. the link layer frame bits are encoded before transmission. each two bits encoded into four chips according to the 4ppm scheme. figure 16-101. stop flag symbol format figure 16-102. high-speed irda data format 0000 1100 0000 1100 0000 1100 0000 1100 00011011 data bits 1/4 bit time (a) (b)
communication processor module motorola mpc823e reference manual 16-293 communication 16 processor module sccs 16.9.20.4 serial infrared interaction pulses. to guarantee nondisruptive coexistence with slower (a maximum of 115.2kb/s) systems, once a high-speed (above 115.2kb/s) connection has been established the high-speed system must emit a serial infrared interaction pulse (sip) at least once every 500ms. this continues for the duration of the connection to quiet slower systems that might interfere with the link. the pulse is illustrated in figure 16-104. the serial infrared interaction pulse can be generated in two ways: ? by the software when you set the gs bit in irsip register. ? by the timer 2 expiration when you set the ts bit in the irsip register. you are responsible for creating the appropriate sip waveform by writing the proper values to the sll and shl fields of the irsip register. figure 16-103. serial infrared interaction pulse waveform (b) 1.6 us 8.7 us
communication processor module 16-294 mpc823e reference manual motorola communication 16 processor module sccs 16.9.20.5 programming model 16.9.20.5.1 scc2 infrared mode register. the scc2 serial infrared mode (irmode) register controls the infrared operation mode (low-, middle-, or high speed), the number of preambles, the loop mode, the full-duplex operation, and the dpll clock rate. panumber of preambles this field determines the number of preambles in a high-speed transmitter. it is valid only in high-speed mode. 0000 = 16 preambles. 0001 = 1 preamble. ? ? ? 1111 = 15 preambles. bits 4, 5 and 12reserved these bits are reserved and must be set to 0. rxprx polarity this bit determines the polarity of the received signal. 0 = active high polarity. an active high pulse is decoded as 0. 1 = active low polarity. an active low pulse is decoded as 0. txptx polarity this bit determines the polarity of the transmitted signal. 0 = active high polarity. an active high pulse is encoded as 0. 1 = active low polarity. an active low pulse is encoded as 0. irmode bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pa reserved rxp txp dcr fd loop res mod en reset 0 000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xfff0000) + 0xa38
communication processor module motorola mpc823e reference manual 16-295 communication 16 processor module sccs dcrirda dpll clock ratio this field determines the clock ratio between the irda dpll clock and the bit rate clock. this field is valid only in high-speed mode. 00 = 12x bit rate clock. 01 = reserved. 1x = reserved. fdfull duplex 0 = data reception is disabled during the transmission process. 1 = transmission and reception of data in parallel are enabled. looploop mode when set, this bit selects the local loopback operation. the transmitter output is internally connected to the receiver input. the receiver and transmitter operate normally, except the received data is ignored. 0 = normal operation. 1 = the irda is in loopback mode. modinfrared mode mode of operation. 00 = low-speed mode (up to and including 115.2kb/s). 01 = middle-speed (0.576mb/s or 1.152mb/s). 10 = high-speed (4.0mb/s). 11 = reserved. enenable irda this bit enables irda decoder/encoder operation. 0 = irda is disabled. 1 = irda is enabled. note: the fd bit must be set in loopback mode. note: changing the en bit value is allowed only when the scc2 is off (after the enr and ent bits in the gsmr_l are cleared).
communication processor module 16-296 mpc823e reference manual motorola communication 16 processor module sccs 16.9.20.5.2 scc2 infrared serial interaction pulse control register. the scc2 infrared serial interaction pulse control (irsip) register controls the initiation of the serial infrared interaction pulse. bits 0 and 3reserved these bits are reserved and must be set to 0. gsgenerate serial infrared interaction pulse 0 = writing zero to this bit has no effect. 1 = setting this bit generates a serial infrared interaction pulse, which occurs only when the channel is idle. this bit is immediately reset by the irda controller. tstimer set 0 = the timer 2 status has no effect on the serial infrared interaction pulse. 1 = the expiration of timer 2 triggers the generation of a serial infrared interaction pulse. shlserial infrared interaction pulse high-level length program this field with the width of the sip assertion part (in bit rate clock units). sllserial infrared interaction pulse low-level length program this field with the width of the sip negation part (in bit rate clock units). irsip bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res gs ts res shl sll reset 0000 0 0 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xfff0000) + 0xa3a note: reading the gs bit always returns a zero.
communication processor module motorola mpc823e reference manual 16-297 communication 16 processor module sccs 16.9.20.5.3 low-speed irda programming guide. low-speed infrared programming is very similar to scc2 async hdlc programming. the only difference is the value of eof and bof in the scc2 parameter ram and the programming of the irmode register. use the following initialization sequence for low-speed infrared. 1. initialize the sdcr with the appropriate arbitration id. 2. configure the port a and port c pins to enable rxd2 and txd2. this assumes you are using nmsi mode. if not, appropriately configure the time-slot assigner and pins. 3. configure a baud rate generator to generate the appropriate channel clocking frequency. 4. program the sicr to route the baud rate generator clocking to an scc2 in asynchronous hdlc mode. 5. select whether the channel is using the time-slot assigner or the nmsi pins in the sicr. 6. write rbase and tbase in the scc2 parameter ram to point to the first rx and tx buffer descriptors. 7. issue the init rx and tx params command to scc2. 8. program rfcr and tfcr. 9. write mrblr with the maximum receive buffer size. 10. write c_mask and c_pres with the standard values. 11. write 0xc0 to bof, 0xc1 to eof and 0x7d to esc. 12. write 0 to the zero register in the scc2 parameter ram. 13. program the rfthr to the number of frames that must be received before an interrupt is generated. 14. program the transmit and receive control character tables. 15. initialize all rx buffer descriptors. 16. initialize all tx buffer descriptors. 17. clear the scceCasync hdlc register by writing 0xffff to it. 18. program the sccmCasync hdlc register with the proper mask to allow all desired interrupts. 19. program the gsmr_h. 20. program the mode field of the gsmr_l to sccx async hdlc mode, but do not turn on the transmitter or receiver. 21. write 0x0001 to the irmode register to enable low-speed infra-red. 22. set the psmrCscc async hdlc register appropriately. 23. turn on the transmitter and receiver in the gsmr_l by setting the ent and enr bits.
communication processor module 16-298 mpc823e reference manual motorola communication 16 processor module sccs 16.9.20.5.4 middle-speed irda programming example. middle-speed infrared programming is very similar to scc2 synchronous hdlc programming. the parameter ram programming and the rx and tx buffer descriptors are the same as in the scc2 hdlc. all of the scc2 synchronous registers and the infrared registers must be initialized. the following list is an initialization sequence for a middle-speed infrared channel assuming that an external clock is provided. the clk3 pin is used for the infrared receiver and transmitter. 1. configure the port a pins to enable the txd2 and rxd2 pins. write bits 13 and 12 of the papar with ones. write bits 13 and 12 of the padir with zeros. write bits 13 and 12 of the paodr with zeros. 2. configure port a to enable the clk3 pin. write papar bit 5 with a one. write zero to bit 5 of the padir. 3. connect the clk3 pin to the scc2 using the serial interface. in the sicr, write 110 to the r2cs and t2cs fields. 4. connect the scc2 to the nmsi (its own set of pins). clear the sc2 bit in the sicr. 5. write the sdcr with the appropriate arbitration id. 6. write rbase and tbase in the scc2 parameter ram to point to the rx and tx buffer descriptors in the dual-port ram. assuming one rx buffer descriptor at the beginning of dual-port ram and one tx buffer descriptor following that rx buffer descriptor, set rbase to 0x2000 and tbase to 0x2008. 7. program the cpcr to execute the init rx and tx params command for the scc2. 8. write 0x18 to the rfcr and 0x18 to the tfcr for normal operation. 9. write the maximum number of bytes per receive buffer to the mrblr. for this case, assume 256 bytes, so mrblr equals 0x0100. the value of 256 was chosen to allow an entire receive frame to fit into one receive buffer. 10. write crc_p with 0xffffffff to comply with 16-bit crc32. 11. write crc_c with 0xdebb20e3 to comply with 16-bit crc32. 12. clear disfc, crcec, abtsc, nmarc, and retrc for the sake of clarity. 13. write mflr with 0x0100 to make the maximum frame size 256 bytes. 14. write rfthr with 0x0001 to allow interrupts after each frame. 15. write hmask with 0x0000 to allow all addresses to be recognized. 16. clear haddr1, haddr2, haddr3, and haddr4 for clarity. 17. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status. write 0x0000 to rx_bd_length (not required-done for instructional purposes only). write 0x00001000 to rx_bd_pointer. 18. initialize the tx buffer descriptor. assume the tx data frame is at 0x00002000 in main memory and contains five 8-bit characters. write 0xbc00 to tx_bd_status. write 0x0005 to tx_bd_length. write 0x00002000 to tx_bd_pointer. 19. write 0xffff to the scceChdlc to clear any previous events.
communication processor module motorola mpc823e reference manual 16-299 communication 16 processor module sccs 20. write 0x001a to the sccmChdlc to enable the txe, rxf, and txb interrupts. 21. write 0x20000000 to the cimr to allow the scc2 to generate a system interrupt. the cicr must also be initialized. 22. write 0x00000000 to the mode field of the gsmr_h to enable normal behavior of the cts and cd pins and idles between frames (as opposed to flags). 23. write 0x00028800 to the mode field of the gsmr_l to configure the cts and cd pins to automatically control transmission, reception (diag field), and hdlc mode. normal operation of the transmit clock is selected and the tci bit is cleared. the tdcr and the rdcr must be configured to 16x clock mode and the receiver decoding method must be nrzi. notice that the transmitter (ent) and receiver (enr) have not been enabled. if you want inverted infra-red operation, set the rinv and tinv bits in the gsmr_l. 24. set the psmrChdlc to 0x1000 to configure two opening and one closing flag, 16-bit ccitt-crc, and prevention of multiple frames in the fifo. 25. write 0x0108 for a 1.152mb/s infrared rate or 0x0084 for a 0.576mb/s infrared rate to the irsip register. when working with timer 2 as the sip trigger, the values must be 0x2108 for a 1.153mb/s infrared or 0x2084 for a 0.572mb/s. 26. write 0x0003 to the irmode register to enable the infrared and to set the mode of operation to middle-speed. 27. program the tmr2 register when working with timer 2 as the sip trigger. 28. write 0x00028830 to gsmr_l to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits will be enabled last. note: after 5 bytes and crc have been transmitted, the tx buffer descriptor is automatically closed. once a complete frame is received, the rx buffer descriptor is closed. any data received after 256 bytes or a single frame causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module 16-300 mpc823e reference manual motorola communication 16 processor module sccs 16.9.20.5.5 high-speed irda programming example. high-speed infrared programming is very similar to scc2 transparent programming. the parameter ram programming and the rx buffer descriptor and tx buffer descriptor are the same as in the sccx transparent mode, which is described in section 16.9.21 the sccx in transparent mode . the scc2 and infrared registers must be initialized. the following list is an initialization sequence for a high-speed infrared channel. the transmitter and receiver are both enabled. both transmit and receive clocks are provided externally to mpc823e using the clk3 pin. 1. configure the port a pins to enable the txd2 and rxd2 pins. write papar bits 13 and 12 with ones. write padir bits 13 and 12 with zeros. write paodr bits 13 and 12 with zeros. 2. configure port a to enable the clk3 pin. write papar bit 5 with a one. write padir bit 5 with a zero. 3. connect the clk3 pin to the scc2 using the serial interface. in the sicr, write 110 to the r2cs and t2cs fields. 4. connect the scc2 to the nmsi (its own set of pins). clear the sc2 bit in the sicr. 5. write the sdcr with the appropriate arbitration id. 6. write rbase and tbase in the scc2 parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of dual-port ram, and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 7. program the cpcr to execute the init rx and tx params command for the scc2. 8. write rfcr and tfcr with 0x18 for normal operation. 9. write the maximum number of bytes per receive buffer to the mrblr. for this case, assume 16 bytes, so mrblr equals 0x0010. 10. write 0xffffffff to crc_p for 32-bit crc-ccitt (crc32). for details, see section 16.9.21.5 sccx transparent parameter ram memory map . 11. write 0xdebb20e3 to crc_c for 32-bit crc-ccitt (crc32). 12. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status. write 0x0000 to rx_bd_length (not required because it is only done for instructional purposes). write 0x00001000 to rx_bd_pointer. 13. initialize the tx buffer descriptor. assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xbc00 to tx_bd_status. write 0x0005 to tx_bd_length. write 0x00002000 to tx_bd_pointer. 14. write 0xffff to the scceCtransparent to clear any previous events. 15. write 0x0013 to the sccmCtransparent to enable the txe, tx, and rx interrupts. 16. write 0x20000000 to the cimr to allow scc2 to generate a system interrupt. the cicr must also be initialized.
communication processor module motorola mpc823e reference manual 16-301 communication 16 processor module sccs 17. write 0x00009980 to the gsmr_h to configure the transparent channel. the cds and ctss bits must be set to one. the tdcr, rdcr, renc, and tenc fields must be set to zero. 18. write 0x00000000 to the gsmr_l. normal operation of the transmit clock is used (tci bit is cleared). notice that the transmitter (ent) and receiver (enr) have not been enabled yet. 19. write 0x031c to the irsip register. when working with timer 2 as the sip trigger, the value must be 0x231c. 20. write 0x0005 to the irmode register to enable the infrared and to set the mode of operation to high-speed. 21. program tmr2 register when working with timer 2 as the sip trigger. 22. write 0x00000030 to the gsmr_l to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits will be enabled last. 16.9.21 the sccx in transparent mode the sccx in transparent mode allows serial data to be transmitted and received over a serial communication controller without any modification to the datastream. transparent mode provides a clear channel on which a serial communication controller does not perform bit-level manipulation. any protocol that uses the transparent mode must have a software layer that loads the parameters. sccx in transparent mode functions as a high-speed serial-to-parallel and parallel-to-serial converter. this mode is also referred to as a totally transparent or promiscuous operation. there are several basic applications for transparent mode. first, some data needs to be moved serially, but requires no superimposed protocol. second, some board-level applications require a serial-to-parallel and parallel-to-serial conversion that allows communication between chips on the same board. third, some applications require the data to be switched without interfering with the protocol encoding itself. for instance, in a multiplexer, data from a high-speed time-multiplexed serial stream is multiplexed into multiple low-speed datastreams. the objective is to switch the data path without altering the protocol encoded on that data path. by appropriately setting the gsmr_l, the sccx channels can be configured to function in transparent mode. the mpc823e receives and transmits the entire serial bitstream transparently. this mode is configured by selecting the ttx and trx bits in the gsmr_h for the transmitter and receiver, respectively. however, both bits must be set for full-duplex transparent operation. note: after 5 bytes have been transmitted, the tx buffer descriptor is automatically closed. once a complete frame is received, the rx buffer descriptor is closed. any data received after 16 bytes or a single frame causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module 16-302 mpc823e reference manual motorola communication 16 processor module sccs if just one of the ttx or trx bits is set, the other half of a serial communication controller operates with another protocol as programmed in the mode field of the gsmr_l. this allows loopback modes to dma data from one memory location to another while converting the data to a specific serial format. the sccx in transparent mode can work with the time-slot assigner or nonmultiplexed serial interface and support modem lines with the general-purpose i/o pins. the data can be transmitted and received with the msb or lsb first in each octet. the sccx in transparent mode consists of separate transmit and receive sections whose operations are asynchronous with the core. each clock can be supplied from the internal baud rate generator bank, dpll output, or external pins. 16.9.21.1 features. the following list summarizes the main features of the sccx in transparent mode: ? flexible data buffers ? automatic sync detection on reception ? crcs can be transmitted and received ? reverse data mode ? another protocol can be performed on the other half of the sccx in transparent mode 16.9.21.2 sccx transparent channel frame transmission process. the transparent transmitter is designed to work with almost no intervention from the core and when the core enables the sccx transmitter in transparent mode, it starts transmitting idles. the serial communication controllers poll the first buffer descriptor in the channels transmit (tx) buffer descriptor table. when there is a message to transmit, the serial communication controllers fetch the data from memory, loads the transmit fifo, and waits for transmitter synchronization before transmitting the message. transmitter synchronization can be achieved with the ctsx pin or by waiting for the receiver to achieve synchronization, depending on how the txsy bit is set in the gsmr_h. once transmitter synchronization is achieved, transmission begins. when buffer descriptor data has been completely transmitted, the l bit is checked and if it is set, the serial communication controllers write the message status bits into the buffer descriptor and clear the r bit. they then start transmitting idles until the next buffer descriptor is ready and if it is ready some idles are still transmitted. the transmitter only begins transmission again after it achieves synchronization. when the end of the current buffer descriptor has been reached and the l bit is cleared, only the r bit is cleared and the transmitter moves immediately to the next buffer to begin transmission with no gap on the serial line between buffers. failure to provide the next buffer in time results in a transmit underrun, thus causing the txe bit in the scceCtransparent register to be set.
communication processor module motorola mpc823e reference manual 16-303 communication 16 processor module sccs in both cases, an interrupt is issued according to the i bit in the rx or tx buffer descriptor. by appropriately setting the i bit in each buffer descriptor, interrupts are generated after each buffer or group of buffers is transmitted. the serial communication controllers then proceed to the next buffer descriptor in the table and any whole number of bytes can be transmitted. if the revd bit in the gsmr_h is set, each data byte is reversed in its bit order before being transmitted and the most-significant bit of each octet is transmitted first. you can decrease the latency of the transmitter by decreasing the transmit fifo size. this option is enabled by the tfl bit in the gsmr_h and causes transmitter underruns at higher transmission speeds. an optional crc can be appended to each transparent frame if it is enabled in the tx buffer descriptor. the crc pattern is chosen in the tcrc field of the gsmr_h. 16.9.21.3 sccx transparent channel frame reception process. when the core enables the sccx receiver in transparent mode, it waits to achieve synchronization before data is received. the receiver can be synchronized to the data by a synchronization pulse or sync pattern. after a buffer is filled, the serial communication controllers clear the e bit in the rx buffer descriptor and generate an interrupt if the i bit is set. they then moves to the next rx buffer descriptor in the table and begin moving data to its associated buffer. if the next buffer is not available, the bsy bit in the scceCtransparent register signifies a busy signal that can generate a maskable interrupt. the receiver reverts to hunt mode when the enter hunt mode command or an error is received. if the revd bit in the gsmr_h is set, each data byte is reversed in its bit order before it is written to memory. you can decrease the latency of the receiver by decreasing the receive fifo width. this option is enabled by the rfw bit in the gsmr_h and causes receiver overruns at higher transmission speeds. the receiver always checks the crc of the received frame, according to the tcrc field in the gsmr_h. if a crc is not required, the resulting errors can be ignored. 16.9.21.4 achieving synchronization in transparent mode. once the sccx transmitter is enabled for transparent operation in the gsmr_h, the tx buffer descriptor is prepared and the transmit fifo is preloaded by the sdma channel, another process must occur before data can be transmitted. it is called transmit synchronization. once the sccx receiver is enabled for transparent operation in the gsmr_h and the rx buffer descriptor is emptied for a serial communication controller, another process (called receive synchronization ) must occur before data can be received. you can have bit-level control of the synchronization process when receiving and transmitting by using either an inline synchronization pattern or external synchronization signals.
communication processor module 16-304 mpc823e reference manual motorola communication 16 processor module sccs 16.9.21.4.1 inline synchronization pattern. the transparent channel can be programmed to transmit and receive a synchronization pattern if the synl field in the gsmr_h are not zero. this pattern is defined in the data synchronization register and the length of the sync pattern is defined in the synl field. if the synl field is 00, then the dsr is not used and an external sync signal is used instead. see section 16.9.4 data synchronization register and section 16.9.2 the general sccx mode registers for more information. dsrCscc transparent (synl = 01) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 4-bit sync x reset 0111111001111110 r/w r/w r/w addr (immr & 0xffff0000) + 0xa2e note: x = dont care. dsrCscc transparent (synl = 10) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 8-bit sync x reset 0111111001111110 r/w r/w r/w addr (immr & 0xffff0000) + 0xa2e note: x = dont care. dsrCscc transparent (synl = 11) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 16-bit sync reset 0111111001111110 r/w r/w addr (immr & 0xffff0000) + 0xa2e
communication processor module motorola mpc823e reference manual 16-305 communication 16 processor module sccs the receiver synchronizes on the synchronization pattern that is located in the dsr. for instance, if 4-bit sync is selected, reception begins as soon as these four bits are received, beginning with the first bit following the 4-bit sync field. the transmitter synchronizes on the receiver pattern if the rsyn bit of the gsmr_h is set. this effectively links the transmitter synchronization to the receiver synchronization. 16.9.21.4.2 external synchronization signals. if the synl field of the gsmr_h is programmed to 00, an external signal is used to begin the sequence. the ctsx pin is used for the transmitter and the cdx pin is used for the receiver and these pins share two options pulse and sampling. the pulse option determines whether the cdx or ctsx pins only need to be asserted once to begin reception/transmission or whether they must be asserted and stay that way for the duration of the transparent frame. in the gsmr_h, the cdp and ctsp bits control the pulse options. if you expect a continuous stream of data without interruption, then you must use the pulse operation. however, if you are trying to identify frames of transparent data, then you must use the envelope mode of these pins. the sampling option determines the delay between the cdx and ctsx signals that is asserted and the reaction of a serial communication controller. you can assume that these pins are asynchronous to the data and internally synchronized by a serial communication controller or you can assume that they are synchronous to the data for faster operation. the cds and ctcc bits of the gsmr_h control the sampling option. you can also link the transmitter synchronization to the receiver synchronization. the pulse/envelope and sampling options are described in section 16.9.10 controlling sccx timing .
communication processor module 16-306 mpc823e reference manual motorola communication 16 processor module sccs 16.9.21.4.3 transparent synchronization example. figure 16-105 illustrates an example of synchronization using the external signals. mpc823e a and b in figure 16-105 exchange transparent frames and synchronize each other using the rtsx and cdx pins. however, the ctsx pin is not required since transmission begins at any time. thus, the rtsx pin is directly connected to the other c cdx d pin. the rsyn bit in the gsmr_h is not set and transmission and reception from each mpc823e is independent. mpc823e (a) mpc823e (b) figure 16-104. sending transparent frames between each mpc823e txdx rtsx first bit of frame data last bit of frame data or crc brgox (output is clkx input) (output is rxdx input) (output is cdx input) notes: 1. ctsx should be configured as always asserted in the port c parallel i/o or externally connected to ground. 2. the required gsmr_x configurations are diag = 00, ctss = 1, ctsp is a "don't care", cds = 1, cdp = 0, ttx = 1, and trx = 1. revd and tcrc are application-dependent. 3. the transparent frame contains a crc if the tc bit is set in the tx buffer descriptor. txdx rtsx rxdx cdx cdx rtsx txdx rxdx brgox clkx notes: 1. each mpc82x generates its own transmit clocks. if the transmit and receive clocks are the same, one mpc82x can generate transmit and receive clocks for the other mpc82x. for example, clkx on mpc82x (b) could be used to clock the transmitter and receiver. brgox clkx cdx lost condition terminates reception of frame l = 1 in tx bd causes negation of rtsx
communication processor module motorola mpc823e reference manual 16-307 communication 16 processor module sccs 16.9.21.5 sccx transparent parameter ram memory map. in totally transparent mode, a serial communication controller overlays the structure used in table 16-24 with the transparent parameters described in table 16-29. ? crc_pfor the 16-bit crc-ccitt, crc_p must be initialized with 0x0000ffff. for the 32-bit crc-ccitt, crc_p must be initialized with 0xffffffff and for crc-16, crc_p must be initialized with ones (0x0000ffff) or zeros (0x00000000). ? crc_cfor the 16-bit crc-ccitt, crc_c must be initialized with 0x0000f0b8. for the 32-bit crc-ccitt, crc_c must be initialized with 0xdebb20e3 and for crc-16, which is normally used with bisync, crc_c must be initialized with 0x00000000. 16.9.21.6 sccx transparent commands. you can program the cpm command register (cpcr) with the following commands to transmit data. see section 16.2.6.1 cpm command register for additional information. ? stop transmit after the hardware or software is reset and the channel is enabled in the sccx mode register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table every 64 clocks (or immediately if the tod bit of the todr is set). this command disables the transmission of frames on the transmit channel and if the sccx transparent controller receives it during frame transmission, buffer transmission is aborted after a maximum of 64 additional bits and the transmit fifo is flushed. the tbptr is not advanced, no new buffer descriptor is accessed and no new buffers are transmitted for this channel. the transmitter will send idles. table 16-29. sccx transparent parameter ram memory map address name width description sccx base + 30 crc_p long crc preset for totally transparent mode sccx base + 34 crc_c long crc constant for totally transparent receiver note: you are only responsible for initializing the items in bold. sccx base = (immr & 0xffff0000) + 0x3d00 (scc2) and 0x3e00 (scc3). note: crc-c overlaps with the crc constant for the hdlc-based protocols. however, this overlap is not detrimental since the crc constant is only used for the receiver, so only one entry is required. you can choose an hdlc transmitter with a transparent receiver or a transparent transmitter with an hdlc receiver.
communication processor module 16-308 mpc823e reference manual motorola communication 16 processor module sccs ? graceful stop transmit this command is used to stop transmission smoothly, rather than abruptly, in much the same way that the regular stop transmit command stops. it stops transmission after the current frame finishes or immediately if there is no frame being transmitted. a transparent frame is not complete until a buffer descriptor with the l bit set has its associated buffer completely transmitted. the gra bit in the scceCtransparent register is set once transmission stops and then the transmit parameters and their buffer descriptors can be modified. the tbptr points to the next tx buffer descriptor in the table. transmission begins once the r bit of the next buffer descriptor is set and the restart transmit command is issued. ? restart transmit this command reenables the transmission of characters on the transmit channel. the sccx transparent controller expects it after a stop transmit command is issued, after a graceful stop transmit command is issued, or after a transmitter error occurs. the sccx transparent controller resumes transmission from the current tbptr in the channel tx buffer descriptor table. ? init tx parameters this command initializes all transmit parameters in the serial channel parameter ram to their reset state. it must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. you can program the cpm command register with the following commands to receive data. see section 16.2.6.1 cpm command register for additional information. ? enter hunt mode after the hardware or software is reset and the channel is enabled in the gsmr_h, the channel is in receive enable mode and uses the first buffer descriptor in the table. this command is used to force the transparent receiver to stop receiving the current frame and enter hunt mode where the sccx transparent controller is waiting for the synchronization sequence. after receiving the command, the current receive buffer is closed. further data reception uses the next buffer descriptor. ? close rx bd this command is used to force a serial communication controller to close the rx buffer descriptor if it is currently being used and to use the next buffer descriptor for any subsequently received data. if a serial communication controller is not in the process of receiving data, no action is taken by this command. ? init rx parameters this command initializes all the receive parameters in this serial channel parameter ram to their reset state and must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters.
communication processor module motorola mpc823e reference manual 16-309 communication 16 processor module sccs 16.9.21.7 sccx transparent controller errors. the serial communication controllers report message reception and transmission errors using the channel buffer descriptors, the error counters, and the scceCtransparent register. the following transmission errors can be detected by the sccx transparent controller. ? transmitter underrun when this error occurs, the channel stops transmitting the buffer, closes it, sets the un bit of the tx buffer descriptor, and generates the txe interrupt if it is enabled. the channel resumes transmission after the restart transmit command is received. underrun occurs after a transmit frame for which the l bit of the tx buffer descriptor was not set. in this case, only the txe bit is set. underrun cannot occur between transparent frames. ? cts lost during message transmission when this error occurs, the channel stops transmitting the buffer, closes it, sets the ct bit of the buffer descriptor, and generates the txe interrupt if it is enabled. the channel resumes transmission after the restart transmit command is received. the following reception errors can be detected by the sccx transparent controller. ? overrun the serial communication controllers maintain an internal fifo for receiving data. the communication processor module starts programming the sdma channel if the data buffer is in external memory and updating the crc when 8 or 32 bits are received in the fifo. if a fifo overrun occurs, the serial communication controllers write the received data byte to the internal fifo over the previously received byte. the previous character and its status bits are lost. afterwards, the channel closes the buffer, sets the ov bit of the rx buffer descriptor, and generates the rx interrupt if it is enabled. the receiver immediately enters hunt mode. ? cd lost during message reception when this error occurs, the channel stops receiving messages, closes the buffer, sets the cd bit of the rx buffer descriptor, and generates the rx interrupt if it is enabled. this error has the highest priority, the rest of the message is lost, and no other errors are checked in the message. 16.9.21.8 sccx transparent mode register. since all transparent mode selections are in the gsmr_h, the psmr is not used by the sccx transparent controller. if transparent mode is only selected for the transmitter/receiver, then the transmitter/receiver can be programmed to support another protocol. in such a case, you can use the psmr for the other protocol.
communication processor module 16-310 mpc823e reference manual motorola communication 16 processor module sccs 16.9.21.9 sccx transparent receive buffer descriptor. the communication processor module reports information about the received data for each buffer using a channels receive (rx) buffer descriptor, closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following events occurs: ? an error is detected. ? a full receive buffer is detected. ? the enter hunt mode command is issued. ? the close rx bd command is issued. eempty 0 = the data buffer associated with this rx buffer descriptor has been filled with data or has stopped receiving data because an error occurred. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor when the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 7, 9C10, and 12reserved these bits are reserved and must be set to 0. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi lf cm res de reserved no res cr ov cd offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module motorola mpc823e reference manual 16-311 communication 16 processor module sccs wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is used. 1 = when this buffer is closed by the transparent controller, the rx bit in the scceCtransparent register is set. the rx bit can cause an interrupt if it is enabled. llast in frame this bit is set by the sccx transparent controller when this buffer is the last in a frame. if cd in envelope mode is negated or an error has been received, one or more of the ov, cd, and de bits are set. the sccx transparent controller writes the number of frame octets to the data length field. 0 = this buffer is not the last one in a frame. 1 = this buffer is the last one in a frame. ffirst in frame the sccx transparent controller sets this bit when this buffer is the first in the frame: 0 = the buffer is not the first in a frame. 1 = the buffer is the first in a frame. cmcontinuous mode 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this buffer descriptor. however, the e bit is cleared if an error occurs during reception, regardless of how the cm bit is set. dedpll error this bit is set by the sccx transparent controller when a dpll error occurs while this buffer is being received. in decoding modes, where a transition occurs on every bit, the dpll error is set when a missing transition occurs. norx non-octet this bit indicates that a frame containing a number of bits not exactly divisible by eight is received.
communication processor module 16-312 mpc823e reference manual motorola communication 16 processor module sccs crcrc error indication bits this bit indicates that this frame contains a crc error. the received crc bytes are always written to the receive buffer. ovoverrun this bit indicates that a receiver overrun has occurred during buffer reception. cdcarrier detect lost this bit indicates that the cdx pin is negated during buffer reception. data length this field represents the number of octets that the communication processor module writes into this buffer descriptor data buffer. the communication processor module only writes it once as the buffer is closed. the actual amount of memory allocated for this buffer must be greater than or equal to mrblr. rx data buffer pointer this field always points to the first location of the associated data buffer and must be divisible by four, unless the rfw bit in the gsmr_h is set to 8 bits wide, even or odd. the buffer can reside in internal or external memory. 16.9.21.10 sccx transparent transmit buffer descriptor. data is sent to the communication processor module for transmission on an sccx channel by arranging it in buffers referenced by the channels transmit (tx) buffer descriptor table. using the buffer descriptors, the communication processor module confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. you must prepare the status and control bits before transmission, but they are set by the communication processor module after the buffer has been transmitted. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi ltccm reserved un ct offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-313 communication 16 processor module sccs rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered. 1 = the data buffer, which you have prepared for transmission, is not transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1 and 7C13reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = when this buffer is serviced by the communication processor module, the tx or txe bit is set in the scceCtransparent register. these bits can cause interrupts if they are enabled. llast in message 0 = the last byte in the buffer is not the last byte in the transmitted transparent frame. data from the next transmit buffer is transmitted immediately after the last byte of this buffer. 1 = the last byte in the buffer is the last byte in the transmitted transparent frame. after this buffer is transmitted, the transmitter must be synchronized before the next buffer is transmitted. tctransmit crc 0 = no crc sequence is transmitted after this buffer. 1 = a frame check sequence that is defined by the tcrc field in the gsmr_h is transmitted after the last byte of this buffer. cmcontinuous mode 0 = normal operation. 1 = the r bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor. however, the r bit is cleared if an error occurs during transmission, regardless of how the cm bit is set.
communication processor module 16-314 mpc823e reference manual motorola communication 16 processor module sccs ununderrun this bit indicates that a serial communication controller has encountered a transmitter underrun condition while transmitting the associated data buffer. ctcts lost this bit indicates the ctsx signal has been lost during frame transmission. data length this field represents the number of bytes that the communication processor module must transmit from this buffer descriptor data buffer. it must be greater than zero, even or odd. this value is never modified by the communication processor module. tx data buffer pointer this field always points to the first byte of the associated data buffer. it can be even or odd, and can reside in internal or external memory. 16.9.21.11 sccx transparent event register. when a serial communication controller is in transparent mode, the 16-bit, memory-mapped sccx event register is referred to as the sccx transparent event register (scceCtransparent). since each protocol has specific requirements, the scce bits are different for each implementation. this register is used to report events recognized by the transparent channel and to generate interrupts. when an event is recognized, the sccx transparent controller sets the corresponding bit in this register. interrupts generated by this register can be masked in the sccmCtransparent register. a bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset at a time. all unmasked bits must be reset before the communication processor module negates the internal interrupt request signal. this register is cleared at reset and can be read at any time. bits 0C2, 6C7, and 9C10reserved these bits are reserved and must be set to 0. glrglitch on rx if set, this bit indicates that a serial communication controller has found a glitch on the receive clock. scceCtransparent bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt dcc res gra res txe rch bsy tx rx reset 0 000000 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa30
communication processor module motorola mpc823e reference manual 16-315 communication 16 processor module sccs gltglitch on tx if set, this bit indicates that a serial communication controller has found a glitch on the transmit clock. dccdpll cs changed this bit indicates when the carrier sense status, which is generated by the dpll, changes state. the real-time status can be found in the sccsCtransparent register. this is not the cdx pin status that is mentioned elsewhere and it is only valid when the dpll is used. gragraceful stop complete this bit indicates when a graceful stop initiated by the graceful stop transmit command has completed. this bit is set as soon as the transmitter finishes any frame that was in progress when the command was issued. it is set immediately if no frame was in progress. txetx error this bit indicates that an error has occurred on the transmitter channel. the i bit in the transmit buffer descriptor must be set in order to get an update of this bit. rchreceive character this bit indicates that a byte or word has been received and written to the buffer, depending on the rfw bit in the gsmr_h. bsybusy condition this bit indicates that a byte or word has been received and discarded due to a lack of buffers. the receiver resumes reception after it gets an enter hunt mode command. txtx buffer this bit indicates that a buffer has been transmitted. this bit is set no sooner than when the last bit of the last byte of the buffer begins its transmission, assuming the l bit of the tx buffer descriptor is set. if it is not set, tx is set when the last byte of data is written to the transmit fifo. the i bit in the tx buffer descriptor must be set in order to get an update of this bit. rxrx buffer this bit indicates that a complete buffer has been received on the sccx channel. this bit is set no sooner than two serial clocks after the last bit of the last byte in which the buffer is received on the rxdx pin. the i bit in the receive buffer descriptor must be set in order to get an update of this bit.
communication processor module 16-316 mpc823e reference manual motorola communication 16 processor module sccs 16.9.21.12 sccx transparent mask register. when a serial communication controller is in transparent mode, the 16-bit read/write sccx mask register is referred to as the sccx transparent mask (sccmCtransparent) register. since each protocol has specific requirements, the sccm bits are different for each implementation. it has the same bit format as the scceCtransparent register. if a bit in this register is 1, the corresponding interrupt in the this register is enabled. if the bit is zero, the corresponding interrupt in this register is masked. 16.9.21.13 sccx transparent status register. when a serial communication controller is in transparent mode, the 8-bit read-only sccx status register is referred to as the sccx transparent status (sccsCtransparent) register. since each protocol has specific requirements, the sccs bits are different for each implementation. this register allows you to monitor real-time status conditions on the rxdx line. the real-time status of the ctsx and cdx pins are part of the port c parallel i/o. bits 0C5 and 7reserved these bits are reserved and must be set to 0. cscarrier sense (dpll) this bit shows the real-time internal csx signal, as determined by the dpll. 0 = the dpll does not sense a carrier. 1 = the dpll senses a carrier. sccmCtransparent bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glr glt dcc res gra res txe rch bsy tx rx reset 0 000000 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa34 sccsCtransparent bit 0 1 2 3 4 5 6 7 field reserved cs reserved reset 000 r/w rrr addr (immr & 0xffff0000) + 0xa37
communication processor module motorola mpc823e reference manual 16-317 communication 16 processor module sccs 16.9.21.14 scc2 transparent programming example. the following is an example initialization sequence for scc2 in transparent mode. the transmitter and receiver are both enabled, but operate independently of each other. they implement the connection illustrated on mpc823e (b) in figure 16-105. the transmit and receive clocks are externally provided to mpc823e (b) using the clk3 pin. the scc2 transparent controller is configured with the rts2 and cd2 pins active and cts2 is grounded internally by the configuration in port c. a 16-bit crc-ccitt is sent with each transparent frame. the fifos are configured for fast operation. 1. configure the port a pins to enable the txd2 and rxd2 pins. write papar bits 13 and 12 with ones and then padir and paodr bits 13 and 12 with zeros. 2. configure the port c pins to enable rts2 , cts2 , and cd2 . write pcpar bit 14 with one and bits 8 and 9 with zero, pcdir bits 14, 9, and 8 with zero, and pcso bits 8 and 9 with one. 3. configure port a to enable the clk3 pin. write papar bit 5 with a one and padir bit 5 with a zero. 4. connect the clk3 pin to the scc2 using the serial interface. write the r2cs and t2cs bits of the sicr to 110. 5. connect the scc2 to the nmsi and clear the sc2 bit of the sicr. 6. write the sdcr with the appropriate arbitration id. 7. write rbase and tbase in the sccx parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 8. program the cpcr to execute the init rx and tx params command for the scc2. to execute this command for scc2, write 0x0041 to the cpcr. 9. write rfcr and tfcr with 0x18 for normal operation. 10. write mrblr with the maximum number of bytes per receive buffer and assume 16 bytes, so mrblr = 0x0010. 11. write crc_p with 0x0000ffff to comply with the 16-bit crc-ccitt. 12. write crc_c with 0x0000f0b8 to comply with the 16-bit crc-ccitt. 13. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. 14. initialize the tx buffer descriptor. assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xbc00 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 15. write 0xffff to the scceCtransparent to clear any previous events. 16. write 0x0013 to the sccmCtransparent to enable the txe, tx, and rx interrupts. 17. write 0x20000000 to the cimr so the scc2 can generate a system interrupt. the cicr must also be initialized. 18. write 0x00001980 to the gsmr_h to configure the transparent channel.
communication processor module 16-318 mpc823e reference manual motorola communication 16 processor module sccs 19. write 0x00000000 to the gsmr_l to configure the cts2 and cd2 pins to automatically control transmission and reception (diag field). normal operation of the transmit clock is used. notice that the transmitter (ent) and receiver (enr) are not enabled yet. 20. write 0x00000030 to the gsmr_l to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits are enabled last. 16.9.22 the sccx in ethernet mode the ethernet ieee 802.3 protocol is a widely used lan based on the carrier-sense multiple access/collision detect (csma/cd) approach. ethernet and ieee 802.3 protocols are very similar and can coexist on the same lan. they are referred to synonymously as ethernet in this manual, unless specifically noted. ethernet and ieee 802.3 frames are based on the frame structure illustrated in figure 16-105. the frame begins with a 7-byte preamble of alternating ones and zeros. since the frame is manchester encoded, the preamble gives receiving stations a known pattern on which to lock. the start frame delimiter signifies the beginning of the frame and follows the preamble. the 48-bit destination address is next, followed by the 48-bit source address. original versions of the ieee 802.3 specification allowed 16-bit addressing. however, this addressing has never been widely used in the industry. the next field is the type field in ethernet and the length field in ieee 802.3. the type field signifies the protocol used in the rest of the frame and the length field specifies the length of the data portion of the frame. for ethernet and ieee 802.3 frames to coexist on the same lan, the length field of the frame must always be unique from any type fields used in ethernet. this has limited the length of the data portion of the frame to 1,500 bytes and the total frame length to 1,518 bytes. the last 4 bytes of the frame are the frame check sequence (fcs), which is the standard 32-bit ccitt-crc polynomial used in many other protocols. note: after 5 bytes are transmitted, the tx buffer descriptor is automatically closed. the receive buffer is automatically closed after 16 bytes are received. any data received after 16 bytes causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared. figure 16-105. ethernet frame format preamble frame check sequence start frame delimiter data 7 bytes 1 byte 46?500 bytes dest addr source addr 6 bytes 2 bytes type/ length 6 bytes 4 bytes frame length is 64?518 bytes note: the lsb of each octet is transmitted first.
communication processor module motorola mpc823e reference manual 16-319 communication 16 processor module sccs when a station needs to transmit, it checks for activity on the lan and when the lan becomes silent for a specified period, the station starts transmitting. at that time, the station continually checks for collision on the lan and if one is found, the station forces a jam of all ones on its frame and stops transmitting. collisions usually occur close to the beginning of a frame. the station waits a random period of time, called a backoff, before trying to transmit again. once the backoff is complete, the station waits for silence on the lan and then begins retransmission on the lan, which is called a retry. if the frame is not successfully transmitted within 15 retries, an error occurs. the 10mbps ethernet provides 0.8 m s per byte. the preamble plus start frame delimiter is transmitted in 6.4 m s. the minimum interframe gap is 9.6 m s and the slot time is 52 m s. therefore, you must operate the mpc823e at a minimum frequency of 20mhz to implement ethernet. 16.9.22.1 features. the following list summarizes the main features of a serial communication controller in ethernet mode: ? performs mac layer functions of ethernet and ieee 802.3 ? full-duplex operation support ? performs framing functions ? full collision support ? maximum 10mbps (10base-t) bit rate ? back-to-back frame reception ? detection of receive frames that are too long ? multibuffer data structure ? supports 48-bit addresses in three modes ? up to eight parallel i/o pins can be sampled and appended to any frame ? heartbeat indication ? transmitter network management and diagnostics ? receiver network management and diagnostics ? error counters ? internal and external loopback mode
communication processor module 16-320 mpc823e reference manual motorola communication 16 processor module sccs 16.9.22.2 ethernet on the mpc823e. when the mode field in the general sccx mode low register (gsmr_l) selects an sccx to be in ethernet mode, the serial communication controllers perform the full set of ieee 802.3/ethernet csma/cd media access control and channel interface functions. in this manual, a serial communication controller in ethernet mode is also referred to as an sccx ethernet controller. the sccx ethernet controller requires an external serial interface adaptor (sia) and transceiver function to complete the interface to the media. this function is implemented in the motorola mc68160 enhanced ethernet serial transceiver (eest). the mpc823e+eest solution provides a direct connection to the attachment unit interface (aui) or twisted-pair (10base-t). the eest provides a glueless interface to the mpc823e, manchester encoding and decoding, automatic selection of 10base-t versus aui ports, 10base-t polarity detection and correction, led drivers, and a low-power mode. for more information, refer to the mc68160 device documentation. the sccx ethernet controller also provides a number of features. although the mpc823e contains dplls that allow manchester encoding and decoding, these dplls were not designed for ethernet rates. therefore, the sccx ethernet controller bypasses the on-chip dplls and uses the external system interface adaptor on the eest instead. figure 16-106. ethernet block diagram shifter receive receiver control unit fifo shifter transmit transmitter control unit fifo slot time clock generator internal clocks control registers txdx rxdx peripheral bus u-bus data data rx clock tx clock and defer counter rts x = tena random no. cd x = rena cts x = clsn cts x = clsn cd x = rena
communication processor module motorola mpc823e reference manual 16-321 communication 16 processor module sccs 16.9.22.3 understanding ethernet on the mpc823e. you are encouraged to learn about the basic functionality of the serial communication controllers and the overall architecture of the communication processor module before delving into the functionality of the sccs in ethernet mode. it is important that first-time users of the mpc823e who plan to use ethernet read the following sections of this manual first. ? section 12.3 interrupt configuration contains an overview of the mpc823e interrupt structure and explains how to set up interrupt control. ? section 16.2 the risc microcontroller , section 16.2 the risc microcontroller , and section 16.2.6.3 dual-port ram explain how the risc microcontroller issues special commands to the ethernet channel. the dual-port ram loads ethernet parameters and initializes buffer descriptors for the ethernet channel to use. ? section 16.5 the sdma channels explains how sdma channels are used to transfer data to or from the ethernet channel and system memory. ? section 16.7.8 nonmultiplexed serial interface configuration explains how clocks are routed to an sccx through the bank of clocks. ? section 16.9.22 the sccx in ethernet mode explains how to program an sccx in ethernet mode. ? section 16.14 the parallel i/o ports explains how to configure the preferred ethernet pin functions to be active. ? section 16.15 the cpm interrupt controller defines the interrupt priority of a serial communication controller and how interrupts are generated to the core. 16.9.22.4 connecting the mpc823e to the eest. the interface to the external eest chip consists of the following ethernet pins: ? receive clock (rclk)the clk1, clk2, clk3, or clk4 pin that is routed through the bank of clocks on the mpc823e. ? transmit clock (tclk)the clk1, clk2, clk3, or clk4 pin that is routed through the bank of clocks on the mpc823e. rclk and tclk must not be connected to the same clkx pin since the eest provides a separate receive and transmit clock signal. ? transmit data (txdx)the mpc823e txd2 or txd3 pin. ? receive data (rxdx)the mpc823e rxd2 or rxd3 pin.
communication processor module 16-322 mpc823e reference manual motorola sccs communication 16 processor module figure 16-108 illustrates the basic components and pins required to make the ethernet connection between the mpc823e and eest. the following pins function differently when a serial communication controller is in ethernet mode than when it is in other protocols: ? transmit enable (tena)the rtsx pin changes to tena when a serial communication controller is in ethernet mode. the polarity of tena is active high, whereas the polarity of rtsx is active low. ? receive enable (rena)the cdx pin changes to rena when a serial communication controller is in ethernet mode. the polarity of rena is active high, whereas the polarity of cdx is active low. ? collision (clsn)the ctsx pin changes to clsn when a serial communication controller is in ethernet mode. the polarity of clsn is active high, whereas the polarity of ctsx is active low. mpc823e figure 16-107. connecting the mpc823e to ethernet note: the carrier sense signal is referenced in ethernet descriptions because it indicates when the lan is being used. carrier sense is defined as rena ored with clsn. mpc823 rj-45 sccx txdx tena (rtsx) tclk (clkx) rxdx rena (cdx) rclk (clkx) clsn (ctsx) parallel i/o tx tena tclk rx rena rclk clsn loop d-15 twisted pair aui passive passive eest mc68160 preamble frame check sequence start frame delimiter data 7 bytes 1 byte 46?500 bytes dest addr source addr 6 bytes 2 bytes type/ length 6 bytes 4 bytes stored in transmit buffer stored in receive buffer note: the mpc82x automatically pads the short transmit frames.
communication processor module motorola mpc823e reference manual 16-323 communication 16 processor module sccs the eest has similar names for its connection to the seven mpc823e pins mentioned above and contains a loopback pin so the mpc823e can perform external loopback testing. this can be controlled by any available parallel i/o pin on the mpc823e. the passive components that are needed to connect to aui or twisted-pair media are external to the eest. for more information on the eest connection circuits, refer to the mc68160 device description. using the sdma channels, the mpc823e stores every byte that is received after the start frame delimiter in system memory. when transmitting, you provide the destination address, source address, type/length field, and transmit data. the mpc823e automatically pads frames with less than 46 bytes in the data field to meet the minimum frame requirements. in addition, the mpc823e appends the frame collision support to the frame. 16.9.22.5 scc x ethernet channel frame transmission process. the ethernet transmitter is designed to work with almost no intervention from the core. when the core enables the transmitter, the sccx ethernet controller polls the first transmit (tx) buffer descriptor in the channel tx buffer descriptor table every 128 serial clocks. if you have a frame to transmit, you can set the tod bit in the todr to avoid waiting for the next poll to occur. see section 16.9.5 transmit-on-demand register for more information. to begin transmission, the sccx ethernet controller fetches the data from the data buffer, asserts tena to the eest, and starts transmitting the preamble sequence, the start frame delimiter, and frame information. however, the sccx ethernet controller defers transmission if the line is busy. before transmitting, it waits for carrier sense to become inactive and stay that way for 6.0 m s. if it does, then the sccx ethernet controller starts transmitting after waiting an additional 3.6 m s (9.6 m s after carrier sense originally became inactive). if a collision occurs during frame transmission, the sccx ethernet controller follows the specified backoff procedure and tries to retransmit the frame until the retry limit threshold is reached. the sccx ethernet controller stores the first 5 to 8 bytes of the transmit frame in internal ram, so that they do not have to be retrieved from system memory in case of a collision. this improves bus utilization and latency when the backoff timer output requires an immediate retransmission. if a collision occurs during frame transmission, the sccx ethernet controller returns to the first buffer for a retransmission. the only restriction is that the first buffer must contain at least 9 bytes. note: if an ethernet frame is made up of multiple buffers, you must not reuse the first buffer descriptor until the last buffer descriptor of the frame has had its r bit cleared by the communication processor module.
communication processor module 16-324 mpc823e reference manual motorola sccs communication 16 processor module when the end of the current buffer descriptor is reached and the l bit in the tx buffer descriptor is set, the frame collision support bytes of the ethernet frame are appended (if the tc bit is set in the tx buffer descriptor), and tena is negated. this notifies the eest that an illegal manchester encoding must be generated to signify the end of an ethernet frame. after crc transmission, the sccx ethernet controller writes the frame status bits into the buffer descriptor and clears the r bit. when the end of the current buffer descriptor is reached and the l bit is not set, only the r bit is cleared. in either mode, an interrupt can be issued, depending on how the i bit is set in the tx buffer descriptor. the sccx ethernet controller then proceeds to the next tx buffer descriptor in the table. you can be interrupted after each frame, after each buffer, or after a specific buffer is transmitted. the sccx ethernet controller can add pad characters to short frames. if the pad bit is set in the tx buffer descriptor, the frame is padded up to the value of the minimum frame length register. to rearrange the transmit queue before the communication processor module finishes transmitting all the frames, issue the graceful stop transmit command. this technique can be useful for transmitting expedited data before previously linked buffers or for error situations. when the graceful stop transmit command is issued, the sccx ethernet controller stops immediately if no transmission is in progress or it will keep transmitting until the current frame either finishes or terminates with a collision. when the sccx ethernet controller receives the restart transmit command, it resumes transmission. the sccx ethernet controller transmits bytes least-significant bit first. 16.9.22.6 sccx ethernet channel frame reception process. the sccx ethernet receiver is designed to work with almost no intervention from the core and can perform address recognition, crc checking, short frame checking, maximum dma transfer checking, and maximum frame length checking. when the core enables the sccx ethernet receiver, it enters hunt mode as soon as the rena signal is asserted if clsn is negated. in hunt mode, as data is shifted into the receive (rx) shift register one bit at a time, the contents of the register are compared to the contents of the syn1 field in the data synchronization register. this compare function becomes valid a certain number of clocks after the start of the frame (depending on the nib bits in the psmrCscc ethernet). if the two are not equal, the next bit is shifted in and the comparison is repeated. if a double zero or double one fault is detected between bits 14 to 21 from the start of the frame, it is rejected. if a double zero fault is detected after 21 bits from the start of the frame and before detection of the start frame delimiter, the frame is also rejected. when the registers match, hunt mode is terminated and character assembly begins. when the receiver detects the first bytes of the frame, the sccx ethernet controller performs address recognition functions on the frame. the receiver can receive physical (individual), group (multicast), and broadcast addresses. sccx ethernet reception frame data is not written to memory until the internal address recognition algorithm is complete, which improves bus utilization with frames not addressed to this station.
communication processor module motorola mpc823e reference manual 16-325 communication 16 processor module sccs if a match is found, the sccx ethernet controller fetches the next rx buffer descriptor and, if it is empty, starts transferring the incoming frame to the rx buffer descriptor associated data buffer. if a collision is detected during the frame, the rx buffer descriptors associated with this frame are reused. thus, there will be no collision frames presented to you except late collisions, which indicate serious lan problems. when the data buffer has been filled, the sccx ethernet controller clears the e bit in the rx buffer descriptor and generates an interrupt if the i bit is set. if the incoming frame exceeds the length of the data buffer, the ethernet controller fetches the next rx buffer descriptor in the table and, if it is empty, continues transferring the rest of the frame to this buffer descriptor associated data buffer. the rx buffer descriptor length is determined by the mrblr value in the sccx parameter ram. you must program the mrblr to be at least 64 bytes. during reception, the sccx ethernet controller checks for a frame that is either too short or too long. when the frame ends, the receive crc field is checked and written to the data buffer. the data length written to the last buffer descriptor in the ethernet frame is the length of the entire frame and it enables the software to correctly recognize the frame-too-long condition. the sccx ethernet controller then sets the l bit in the rx buffer descriptor, writes the other frame status bits into the rx buffer descriptor, and clears the e bit. then it generates a maskable interrupt, which indicates that a frame has been received and is in memory. the sccx ethernet controller then waits for a new frame. it receives serial data least-significant bit first.
communication processor module 16-326 mpc823e reference manual motorola sccs communication 16 processor module 16.9.22.7 sccx ethernet parameter ram memory map. when a serial communication controller is configured to operate in ethernet mode, it overlays the structure used in table 16-24 onto the parameters described in table 16-30. table 16-30. sccx ethernet parameter ram memory map address name width description sccx base + 30 c_pres word preset crc sccx base + 34 c_mask word constant mask for crc sccx base + 38 crcec word crc error counter sccx base + 3c alec word alignment error counter sccx base + 40 disfc word discard frame counter sccx base + 44 pads half-word short frame pad character sccx base + 46 ret_lim half-word retry limit threshold sccx base + 48 ret_cnt half-word retry limit counter sccx base + 4a mflr half-word maximum frame length register sccx base + 4c minflr half-word minimum frame length register sccx base + 4e maxd1 half-word max dma1 length register sccx base + 50 maxd2 half-word max dma2 length register sccx base + 52 maxd half-word rx max dma sccx base + 54 dma_cnt half-word rx dma counter sccx base + 56 max_b half-word max buffer descriptor byte count sccx base + 58 gaddr1 half-word group address filter 1 sccx base + 5a gaddr2 half-word group address filter 2 sccx base + 5c gaddr3 half-word group address filter 3 sccx base + 5e gaddr4 half-word group address filter 4 sccx base + 60 tbuf0_data0 word save area 0Ccurrent frame sccx base + 64 tbuf0_data1 word save area 1Ccurrent frame sccx base + 68 tbuf0_rba0 word save rbaCcurrent frame sccx base + 6c tbuf0_crc word save crcCcurrent frame sccx base + 70 tbuf0_bcnt half-word save bcntCcurrent frame sccx base + 72 paddr1_l* half-word physical address 1 (lsb) sccx base + 74 paddr1_m* half-word physical address 1 sccx base + 76 paddr1_h* half-word physical address 1 (msb) sccx base + 78 p_per half-word persistence sccx base + 7a rfbd_ptr half-word rx first buffer descriptor pointer sccx base + 7c tfbd_ptr half-word tx first buffer descriptor pointer sccx base + 7e tlbd_ptr half-word tx last buffer descriptor pointer
communication processor module motorola mpc823e reference manual 16-327 communication 16 processor module sccs ? c_presfor 32-bit crc-ccitt, c_pres must be initialized with 0xffffffff. ? c_maskfor 32-bit crc-ccitt, c_mask must be initialized with 0xdebb20e3. ? crcec, alec, and disfcthese 32-bit (modulo 2 32 ) counters are maintained by the communication processor module and you can initialize them while the channel is disabled. crcec is incremented for each received frame with a crc error, except it does not include frames not addressed to you, frames received in the out-of-buffers condition, frames with overrun errors, or frames with alignment errors. alec is incremented for frames received with dribbling bits, but does not include frames not addressed to you, frames received in the out-of-buffers condition, or frames with overrun errors. disfc is incremented for frames discarded because of the out-of-buffers condition or an overrun error. the crc does not have to be correct for this counter to be incremented. ? padsyou must write the pattern of the pad characters that must be sent when short frame padding is implemented into this 16-bit register. the byte pattern written to the register may be of any value, but both the high and low bytes must be the same. ? ret_limyou must write the number of retries that must be made to transmit a frame into this 16-bit register. this value is typically 0xf. if the frame is not transmitted after this limit is reached, an interrupt can be generated. ? ret_cnt is a temporary down-counter used to count the number of retries. sccx base + 80 tbuf1_data0 word save area 0Cnext frame sccx base + 84 tbuf1_data1 word save area 1Cnext frame sccx base + 88 tbuf1_rba0 word save rbaCnext frame sccx base + 8c tbuf1_crc word save crcCnext frame sccx base + 90 tbuf1_bcnt half-word save bcntCnext frame sccx base + 92 tx_len half-word tx frame length counter sccx base + 94 iaddr1 half-word individual address filter 1 sccx base + 96 iaddr2 half-word individual address filter 2 sccx base + 98 iaddr3 half-word individual address filter 3 sccx base + 9a iaddr4 half-word individual address filter 4 sccx base + 9c boff_cnt half-word backoff counter sccx base + 9e taddr_l half-word temp address (lsb) sccx base + a0 taddr_m half-word temp address sccx base + a2 taddr_h half-word temp address (msb) note: you are only responsible for initializing the items in bold. sccx base = (immr & 0xffff0000) + 0x3d00 (scc2) and 0x3e00 (scc3). * the bytes inside each half-word are reversed. all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register. table 16-30. sccx ethernet parameter ram memory map (continued) address name width description
communication processor module 16-328 mpc823e reference manual motorola sccs communication 16 processor module ? mflrthe sccx ethernet controller checks the length of an incoming ethernet frame against the user-defined value given in this 16-bit register. typically this register is set to 0x5ee. if this limit is exceeded, the remainder of the incoming frame is discarded and the lg bit is set in the last rx buffer descriptor belonging to that frame. the sccx ethernet controller reports the frame status and length in the last rx buffer descriptor. mflr is defined as all the in-frame bytes between the start frame delimiter and the end of the frame. ? minflrthe sccx ethernet controller checks the length of an incoming ethernet frame against the user-defined value given in this 16-bit register that is typically set to 0x40. if the received frame length is less than the register value, then this frame is discarded, unless the rsh bit in the psmrCscc ethernet is set. if rsh is set, then the sh bit is set in the last rx buffer descriptor belonging to that frame. for transmit operation when the frame is too short, the sccx ethernet controller adds pads to the transmitted frame, depending on how the pad bit is set in the tx buffer descriptor and the pad value in the parameter ram. pad characters are added to make the transmit frame minflr bytes in length. ? maxd1this parameter gives you the option to stop system bus writes from occurring after a frame has exceeded a certain size. however, the value of this register is valid only if an address match is found. the sccx ethernet controller checks the length of an incoming ethernet frame against the user-defined value given in this 16-bit register that is usually set to 0x5f0. if this limit is exceeded, the remainder of the incoming frame is discarded. the sccx ethernet controller waits until the end of the frame is reached or until the mflr bytes have been received and then it reports the frame status and length in the last rx buffer descriptor. ? maxd2this parameter also gives you the option to stop system bus writes from occurring after a frame has exceeded a certain size. however, the value of this register is valid in promiscuous mode when no address match is detected. the sccx ethernet controller checks the length of an incoming ethernet frame against the user-defined value given in this 16-bit register that is usually set to 0x5f0. if this limit is exceeded, the remainder of the incoming frame is discarded. the sccx ethernet controller waits until the end of the frame is reached or until the mflr bytes have been received and then it reports the frame status and length in the last rx buffer descriptor. in a monitor station, maxd2 can be programmed to a value much less than maxd1 to receive entire frames addressed to this station, but receives only the headers of the other frames. ? maxdfor internal use only. ? max_bfor internal use only. ? dma_cnt is a temporary down-counter used to track the frame length. ? gaddr1C4these four registers are used in the hash table function of the group addressing mode. you can write zeros to these values after reset and before the ethernet channel is enabled to disable all group hash address recognition functions. the set group address command is used to enable the hash table. ? tbuf0_data0for internal use only. ? tbuf0_data1for internal use only. ? tbuf0_rba0for internal use only.
communication processor module motorola mpc823e reference manual 16-329 communication 16 processor module sccs ? tbuf0_crcfor internal use only. ? tbuf0_bcntfor internal use only. ? paddr1you must write the 48-bit individual address of the station into this location. paddr1_l is the lowest order half-word, paddr1_h is the highest order half-word and paddr_m is the middle half-word. ? p_perthis parameter allows the sccx ethernet controller to be less aggressive after a collision. normally, this parameter is set to 0x0000. to decrease the aggressiveness of the sccx ethernet controller, you can set p_per to a value between 1 (most aggressive) and 9 (least aggressive). the p_per value is added to the retry count in the backoff algorithm to reduce the probability of transmission on the next time slot. ? rfbd_ptrfor internal use only. this register contains the first rx buffer descriptor pointer. ? tfbd_ptrfor internal use only. this register contains the first tx buffer descriptor pointer. ? tlbd_ptrfor internal use only. this register contains the last tx buffer descriptor pointer. ? tx_lenfor internal use only. ? iaddr1C4 these four registers are used in the hash table function of the individual addressing mode. you can write zeros to these values after reset and before the ethernet channel is enabled to disable all individual hash address recognition functions. the set group address command is used to enable the hash table. ? boff_cntfor internal use only. ? taddrthis parameter allows you to add and delete addresses from the individual and group hash tables. after placing an address in taddr, you must issue the set group address command. taddr_l is the lowest order half-word, taddr_h is the highest order half-word and taddr_m is the middle half-word. note: the ethernet/802.3 specification allows the use of p_per. in a heavily congested ethernet lan, a less aggressive backoff algorithm used by multiple stations on the lan increases the overall lan throughput by reducing the probability of collisions. the sbt bit in the psmrCscc ethernet offers another way to reduce the aggressiveness of the sccx ethernet controller.
communication processor module 16-330 mpc823e reference manual motorola sccs communication 16 processor module 16.9.22.8 configuring the sccx ethernet parameters. you can configure a serial communication controller to operate in ethernet mode by setting the mode field in the general sccx mode low register (gsmr_l). the receive errors are reported in the rx buffer descriptor and the transmit errors are reported in the tx buffer descriptor. several fields in the gsmr_h and gsmr_l must be programmed to special values for ethernet. you must program the data synchronization register (dsr) using the table below. the gsmr_l programs the first six bytes of the preamble and the syn1 field of the dsr programs the seventh byte (0x55) of the preamble. program the 1-byte start delimiter with the value 0xd5 in the syn2 field of the dsr. refer to section 16.9.2 the general sccx mode registers for more information. syn2synchronization 2 this field represents the start frame delimiter for an ethernet frame. you must set this field to 0xd5. syn1synchronization 1 this field represents the seventh byte of the preamble for the ethernet frame. you must set this field to 0x55. 16.9.22.9 sccx ethernet commands. you can program the cpm command register (cpcr) with the following commands to transmit data. see section 16.2.6.1 cpm command register for additional information. ? stop transmit when used with the sccx ethernet controller, this command violates a specific behavior of an ethernet/ieee 802.3 station. it must not be used. dsr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field syn2 syn1 reset 0111111001111110 r/w r/w r/w addr (immr & 0xffff0000) + 0xa2e note: before issuing a cpm reset (rst bit in the cpcr), configure the tena pin as an input.
communication processor module motorola mpc823e reference manual 16-331 communication 16 processor module sccs ? graceful stop transmit this command is used to ensure that transmission stops smoothly after the current frame finishes or undergoes a collision. the gra bit in the scceCethernet register is set once transmission stops. then you can modify the ethernet transmit parameters and their buffer descriptors. the tbptr points to the next tx buffer descriptor in the table. transmission begins once the r bit of the next buffer descriptor is set and the restart transmit command is issued. ? restart transmit this command enables the transmission of characters on the transmit channel. the sccx ethernet controller expects it after a graceful stop transmit command is issued or a transmitter error occurs. the sccx ethernet controller resumes transmission from the current tbptr in the channel tx buffer descriptor table. ? init tx parameters this command initializes all the transmit parameters in this serial channel parameter ram to their reset state. it must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. you can program the cpm command register with the following commands to receive data. see section 16.2.6.1 cpm command register for additional information. ? enter hunt mode after the hardware or software is reset and the channel in the sccmCethernet register is enabled, the channel is in receive enable mode and uses the first buffer descriptor in the table. this command is generally used to force the ethernet receiver to stop receiving the current frame and enter hunt mode. in this mode, the sccx ethernet controller continually scans the input datastream for a transition of carrier sense from inactive to active and then a preamble sequence followed by the start frame delimiter. after receiving the command, the current receive buffer is closed and the crc calculation is reset. the next rx buffer descriptor is used to receive more frames. ? close rx bd this command must not be used when a serial communication controller is in ethernet mode. ? init rx parameters this command initializes all the receive parameters in this serial channel parameter ram to their reset state and must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters. note: if the graceful stop transmit command is issued and the current transmit frame ends in a collision, the tbptr points to the beginning of the collided frame with the r bit still set in the tx buffer descriptor. the frame will look as if it was never transmitted.
communication processor module 16-332 mpc823e reference manual motorola sccs communication 16 processor module ? set group address this command is used to set a bit in one of the 64 bits of the four individual/group address hash filter registers. the individual or group address to be added to the hash table must be written to taddr_l, taddr_m, and taddr_h in the parameter ram before executing this command. the risc microcontroller checks the i/g bit in the address stored in taddr to determine whether to use the individual hash table or the group hash table. a zero in the i/g bit implies an individual address and a 1 in the i/g bit implies a group address. this command can be executed at any time, regardless of whether the ethernet channel is enabled. if you need to delete an address from the hash table, disable the ethernet channel, clear the hash table registers, and execute this command for the remaining addresses. you must do this because the hash table might have mapped multiple addresses to the same hash table bit. 16.9.22.10 sccx ethernet address recognition. the sccx ethernet controller can filter the received frames based on different addressing typesphysical (individual), group (multicast), broadcast (all-ones group address), and promiscuous. you can set the promiscuous address type in the psmrCscc ethernet register. the difference between an individual address and a group address is determined by the i/g bit in the destination address field, which is part of the standard ethernet protocol. a flowchart for address recognition on received frames is illustrated in figure 16-108. in the physical type of address recognition, the sccx ethernet controller compares the destination address field of the received frame with the physical address that you program in paddr1_h, paddr1_m, and paddr1_l. you can also perform address recognition on multiple individual addresses using the iaddr1C4 hash table.
communication processor module motorola mpc823e reference manual 16-333 communication 16 processor module sccs figure 16-108. ethernet address recognition flowchart i/g address broadcast addr multiple ind g i t f f t match ? hash search t match ? hash_search use indicated table t match ? t f t f f f t f use group table multiple individual addresses receive frame ignore rrjct pin check address enabled broadcast single address promisc ? start receive discard frame if rrjct pin is asserted discard frame receive frame ignore rrjct pin receive frame ignore rrjct pin
communication processor module 16-334 mpc823e reference manual motorola sccs communication 16 processor module in group address recognition, the sccx ethernet controller determines whether or not the group address is a broadcast address. if broadcast addresses are enabled, then the frame is accepted, but if the group address is not a broadcast address, then you can perform address recognition on multiple group addresses using the gaddr1C4 hash table. in promiscuous mode, the sccx ethernet controller receives all incoming frames, regardless of their address. 16.9.22.11 hash table algorithm. for individual and group hash filtering, the sccx ethernet controller maps any 48-bit address into one of 64 bins, which are represented by 64 bits stored in gaddr1C4 or iaddr1C4. when the set group address command is executed, the sccx ethernet controller maps the selected 48-bit address into one of the 64 bits by passing the 48-bit address through the on-chip 32-bit crc generator and selecting 6 bits of the crc-encoded result to generate a number between 1 and 64. bits 31C 30 of the crc result select one of the four gaddrs or iaddrs and bits 29C26 of the crc result select the bit within the selected register. when the sccx ethernet controller receives a frame, the same process is used. if the crc generator selects a bit that is set in the group/individual hash table, the frame is accepted. otherwise, it is rejected. the result is that if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. those that reach memory must be further filtered by the processor to determine if they truly contain one of the eight preferred addresses. better performance is achieved by using the group and individual hash tables simultaneously. for instance, if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames are prevented from reaching memory. the effectiveness of the hash table declines as the number of addresses increases. for instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the hash table bits are set, thus preventing a small fraction of the frames from reaching memory. note: the hash tables cannot be used to reject frames that match a set of entered addresses because unintended addresses are matched to the same bit in the hash table.
communication processor module motorola mpc823e reference manual 16-335 communication 16 processor module sccs 16.9.22.12 interpacket gap time. the minimum interpacket gap time for back-to-back transmission is 9.6 m s. the receiver receives back-to-back frames with this minimum spacing. in addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated before retransmitting the frame. retransmission begins 9.6 m s after carrier sense is negated, but only if it remains negated for at least 6.4 m s. 16.9.22.13 handling collisions. if a collision occurs while a frame is being transmitted, the sccx ethernet controller continues transmitting for at least 32 bit times, thus transmitting a jam pattern that consists of 32 ones. if the collision occurs during the preamble sequence, the jam pattern will be sent at the end of the preamble sequence. if a collision occurs within 64 byte times, the retry process is initiated. the transmitter waits a random number of slot times (512 bit times or 52 m s). if a collision occurs after 64 byte times, then no retransmission is performed and the buffer is closed with an lc error indication. if a collision occurs while a frame is being received, reception stops. this error is only reported in the buffer descriptor if the length of this frame is greater than or equal to the minflr or if the rsh mode is enabled in the psmrCscc ethernet register. 16.9.22.14 loopback and full-duplex operation. both internal and external loopback is supported by the sccx ethernet controller. in loopback mode, both sccx fifos are used and the channel operates in a full-duplex fashion. both internal and external loopback are configured using combinations of the lpb bit in the psmrCscc ethernet and the diag field in the gsmr_l. internal loopback disconnects a serial communication controllers from the serial interface. the receive data is connected to the transmit data and the receive clock is connected to the transmit clock. both fifos are used. the transmitted data from the transmit fifo is received immediately into the receive fifo. there is no heartbeat check in this mode. tena must be configured as a general-purpose output and the hbc bit in the psmrCscc ethernet must be zero. in external loopback operation, the sccx ethernet controller listens for data received from the eest at the same time that it is transmitting.
communication processor module 16-336 mpc823e reference manual motorola sccs communication 16 processor module 16.9.22.15 sccx ethernet controller errors. the sccx ethernet controller reports frame reception and transmission error conditions using the channel buffer descriptors, the error counters, and the scceCethernet register. the following transmission errors can be detected by the sccx ethernet controller. ? transmitter underrun errorif this error occurs, the channel sends 32 bits to ensure a crc error, stops transmitting the buffer, closes it, sets the un bit in the tx buffer descriptor, and sets txe in the scceCethernet register. the channel resumes transmission after it receives the restart transmit command. ? carrier sense lost during frame transmission error when this error occurs and no collision is found in the frame, the channel sets the csl bit in the tx buffer descriptor, sets the txe bit in the scceCethernet register, and continues the buffer transmission as normal. no retries are performed after this error occurs. ? retransmission attempts limit expired error when this error occurs, the channel stops transmitting the buffer, closes it, sets the rl bit in the tx buffer descriptor, and sets the txe bit. the channel resumes transmission after it receives the restart transmit command. ? late collision error when this error occurs, the channel stops transmitting the buffer, closes it, sets the lc bit in the tx buffer descriptor, and sets the txe bit. the channel resumes transmission after it receives the restart transmit command. this error is discussed further in the definition of the lcw bit in the psmrCscc ethernet. ? heartbeat error some transceivers have a self-test feature called heartbeat or signal quality error. to signify a good self-test, the transceiver indicates a collision to the mpc823e within 20 clocks after the ethernet controller transmits a frame. this indication does not imply a real collision error on the network, but is rather an indication that the transceiver is still functioning properly. this is called the heartbeat condition. if the hbc bit is set in the psmrCscc ethernet and the mpc823e does not detect a heartbeat condition after transmitting a frame, then a heartbeat error occurs. in which case, the channel closes the buffer, sets the hb bit in the tx buffer descriptor, and generates a txe interrupt if it is enabled. the following reception errors can be detected by the sccx ethernet controller: ? overrun errorthe sccx ethernet controller maintains an internal fifo for receiving data. if a receiver fifo overrun occurs, the channel writes the received data byte to the internal fifo over the previously received byte. the previous data byte and frame status are lost. the channel closes the buffer, sets the ov bit in the rx buffer descriptor, rxf in the scceCethernet register, and increments the discarded frame counter. the receiver then enters hunt mode. ? busy errorthis error occurs when a frame has been received and discarded because of a lack of buffers. the channel sets the bsy bit in the scceCethernet register and increments the discarded frame counter.
communication processor module motorola mpc823e reference manual 16-337 communication 16 processor module sccs ? non-octet error (dribbling bits) the sccx ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet aligned and it checks the crc of the frame on the last octet boundary. if there is a crc error, then the frame nonoctet aligned error is reported, the rxf bit is set, and the alignment error counter is incremented. if there is no crc error, then no error is reported. ? crc errorwhen a crc error occurs, the channel closes the buffer, sets the cr bit in the rx buffer descriptor, and the rxf bit in the scceCethernet register. the channel also increments the crc error counter (crcec). after receiving a frame with a crc error, the receiver enters hunt mode. crc checking cannot be disabled, but the crc error can be ignored if checking is not required. 16.9.23 programming the sccx ethernet controller 16.9.23.1 sccx ethernet mode register. when a serial communication controller is in ethernet mode, the 16-bit, memory-mapped, read/write protocol-specific mode register is referred to as the sccx ethernet mode register (psmrCscc ethernet). since each protocol has specific requirements, the psmr bits are different for each implementation. hbcheartbeat checking 0 = no heartbeat checking is performed. do not wait for a collision after transmission. 1 = wait 20 transmit clocks or 2 m s for a collision asserted by the transceiver after transmission. the hb bit in the tx buffer descriptor is set if the heartbeat is not heard within 20 transmit clocks. fcforce collision 0 = normal operation. 1 = the channel forces a collision when each frame is transmitted. the mpc823e must be configured in loopback operation when using this feature so that you can test the collision logic. in the end, the retry limit for each transmit frame is exceeded. rshreceive short frames 0 = discard short frames that are not as long as minflr. 1 = receive short frames. psmrCscc ethernet bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field hbc fc rsh iam crc pro bro sbt lpb res lcw nib fde reset 0000 0 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa28
communication processor module 16-338 mpc823e reference manual motorola sccs communication 16 processor module iamindividual address mode 0 = normal operation. a single 48-bit physical address that is stored in paddr1_x is checked when it is received. 1 = the individual hash table is used to check all individual addresses that are received. crccrc selection 00 = reserved. 01 = reserved. 10 = 32-bit ccitt-crc (ethernet). x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1. select this to comply with ethernet specifications. 11 = reserved. propromiscuous 0 = check the destination address of the incoming frames. 1 = receive the frame regardless of its address. brobroadcast address 0 = receive all frames containing the broadcast address. 1 = reject all frames containing the broadcast address, unless the pro bit = 1. sbtstop backoff timer 0 = the backoff timer is functioning normally. 1 = the backoff timer for the random wait after a collision is stopped when carrier sense is active. this method makes the retransmission less aggressive than the maximum allowed in the ieee 802.3 standard. the persistence (p_per) parameter in the parameter ram can be used in combination with, or in place of, the sbt bit. lpbloopback operation 0 = normal operation. 1 = the channel is configured into internal or external loopback operation as determined by the diag field of the gsmr_l. for external loopback, the diag field must be configured for normal operation and for internal loopback they must be configured for loopback operation. bit 10reserved this bit is reserved and must be set to 0. lcwlate collision window 0 = a late collision is any collision that occurs at least 64 bytes from the preamble. 1 = a late collision is any collision that occurs at least 56 bytes from the preamble.
communication processor module motorola mpc823e reference manual 16-339 communication 16 processor module sccs nibnumber of ignored bits this parameter determines how soon after rena assertion the sccx ethernet controller must begin looking for the start frame delimiter. in most situations, it is recommended that you select 22 bits. 000 = begin searching for the sfd 13 bits after the assertion of rena. 001 = begin searching for the sfd 14 bits after the assertion of rena. 010 = begin searching for the sfd 15 bits after the assertion of rena. 011 = begin searching for the sfd 16 bits after the assertion of rena. 100 = begin searching for the sfd 21 bits after the assertion of rena. 101 = begin searching for the sfd 22 bits after the assertion of rena. 110 = begin searching for the sfd 23 bits after the assertion of rena. 111 = begin searching for the sfd 24 bits after the assertion of rena. fdefull-duplex ethernet 0 = disable full-duplex ethernet mode. 1 = enable full-duplex ethernet mode. note: when this bit is set to 1, you must also set the lpb bit to 1.
communication processor module 16-340 mpc823e reference manual motorola sccs communication 16 processor module 16.9.23.2 sccx ethernet receive buffer descriptor. the sccx ethernet controller uses the receive (rx) buffer descriptor to report information about the received data for each buffer. figure 16-109 illustrates an ethernet receive buffer descriptor example. figure 16-109. ethernet receive buffer descriptor example mrblr = 64 bytes for this scc buffer 64 bytes time buffer buffer buffer full e length receive bd 0 status 0040 pointer 0 e length receive bd 1 status 0045 pointer 0 1 0 l e length receive bd 2 status pointer 1 e length receive bd 3 status xxxx pointer 1 buffer present time 1 f 0 lf non-collided ethernet frame 1 two frames received in ethernet line idle old data from collided frame will be overwritten. crc bytes (4) tag byte (1) dest address (6) source address (6) type/length (2) data bytes (50) collision 32-bit buffer pointer 32-bit buffer pointer 32-bit buffer pointer 32-bit buffer pointer frame 2 64 bytes 64 bytes 64 bytes xxxx buffer closed after crc received. optional tag byte appended collision causes buffer to be reused buffer still empty empty empty empty
communication processor module motorola mpc823e reference manual 16-341 communication 16 processor module sccs eempty 0 = the data buffer associated with this rx buffer descriptor has been filled with data or has stopped receiving data because an error occurred. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor as long as the e bit is zero. 1 = the data buffer associated with this rx buffer descriptor is empty or is currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 6, and 8C9reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is used. 1 = the rxb or rxf bit of the scceCethernet register is set when this buffer is used by the sccx ethernet controller. these two bits can cause interrupts if they are enabled. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi l f res m res lg no sh cr ov cl offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-342 mpc823e reference manual motorola sccs communication 16 processor module llast in frame the ethernet controller sets this bit when this buffer is the last one in a frame. if the end of a frame is reached or an error is received, one or more of the cl, ov, cr, sh, no, and lg bits are set. the sccx ethernet controller writes the number of frame octets to the data length field. 0 = the buffer is not the last one in a frame. 1 = the buffer is the last one in a frame. ffirst in frame the sccx ethernet controller sets this bit when this buffer is the first one in a frame. 0 = the buffer is not the first one in a frame. 1 = the buffer is the first one in a frame. mmiss the sccx ethernet controller sets this bit for frames that are accepted in promiscuous mode, but are flagged as a miss by the internal address recognition. thus, while in promiscuous mode, you can use this bit to determine whether the frame is destined to this station. this bit is valid only if the l bit is set. 0 = the frame is received because of an address recognition hit. 1 = the frame is received because of promiscuous mode. lgrx frame length violation this bit indicates that a frame length greater than the maximum defined for this channel has been recognized. only the maximum-allowed number of bytes is written to the data buffer. norx nonoctet aligned frame this bit indicates that a frame containing a number of bits not divisible by eight is received. also, the crc check that occurs at the preceding byte boundary has generated an error. shshort frame this bit indicates that a frame length less than the minimum defined for this channel has been recognized. this can only happen if the rsh bit is set in the psmrCscc ethernet. crrx crc error this bit indicates that this frame contains a crc error. ovoverrun this bit indicates that a receiver overrun has occurred during frame reception. clcollision this bit indicates that this frame is closed because a collision has occurred during frame reception. this bit is only set if a late collision occurs or if the rsh bit is enabled in the psmrCscc ethernet. late collisions are better defined in the lcw bit of the same register.
communication processor module motorola mpc823e reference manual 16-343 communication 16 processor module sccs data length this field represents the number of octets the communication processor module writes into this buffer descriptor data buffer. it is written by the communication processor module once the buffer is closed. when this buffer descriptor is the last buffer descriptor in the frame, the data length contains the total number of frame octets (including four bytes for crc). rx data buffer pointer this field always points to the first location of the associated data buffer, can reside in internal or external memory, and must be divisible by four. 16.9.23.3 sccx ethernet transmit buffer descriptor. data is sent to the sccx ethernet controller for transmission on an sccx channel by arranging it in buffers referenced by the channels transmit (tx) buffer descriptor table. using the buffer descriptors, the sccx ethernet controller confirms transmission or indicates error conditions so that the core knows the buffers have been serviced. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission and you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 = the data buffer, which you have prepared for transmission, has not been transmitted or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. note: the actual amount of memory allocated for this buffer must be greater than or equal to the contents of the mrblr. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r pad w i l tc def hb lc rl rc un csl offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-344 mpc823e reference manual motorola sccs communication 16 processor module padshort frame padding this bit is only valid when the l bit is set. otherwise, it is ignored. 0 = do not add pads to short frames. 1 = add pads to short frames. pad bytes are inserted until the length of the transmitted frame equals the minflr and they are stored in pads in the parameter ram. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the txb or txe bit is set in the scceCethernet register after this buffer is serviced. these bits can cause interrupts if they are enabled. llast 0 = this is not the last buffer in the transmit frame. 1 = this is the last buffer in the transmit frame. tctx crc this bit is valid only when the l bit is set. otherwise, it is ignored. 0 = end transmission immediately after the last data byte. 1 = transmit the crc sequence after the last data byte. defdefer indication this bit indicates that this frame had a collision before it was sent. it is useful for channel statistics. the sccx ethernet controller writes this bit after it finishes transmitting the associated data buffer. hbheartbeat this bit indicates the collision input was not asserted within 20 transmit clocks after transmission. it cannot be set unless the hbc bit is set in the psmrCscc ethernet. the sccx ethernet controller writes this bit after it finishes transmitting the associated data buffer. note: the tx buffer descriptor table must contain more than one buffer descriptor in sccx ethernet mode.
communication processor module motorola mpc823e reference manual 16-345 communication 16 processor module sccs lclate collision this bit indicates that a collision occurred after the number of bytes defined for the lcw bit in the psmrCscc ethernet are transmitted. the sccx ethernet controller stops transmitting and writes this bit after it finishes transmitting the associated data buffer. rlretransmission limit this bit indicates when the transmitter fails a retry limit + 1 attempt to successfully transmit a message because of repeated collisions on the medium. the sccx ethernet controller writes this bit after it finishes transmitting the associated data buffer. rcretry count this field indicates the number of retries required before this frame is successfully transmitted. if rc = 0, then the frame is transmitted correctly the first time. if rc = 15 and ret_lim = 15 in the parameter ram, then 15 retries are required. if rc = 15 and ret_lim > 15 in the parameter ram, then 15 or more retries are required. the sccx ethernet controller writes these bits after it finishes transmitting the associated data buffer. ununderrun this bit indicates that the sccx ethernet controller has encountered a transmitter underrun condition while transmitting the associated data buffer. the sccx ethernet controller writes this bit after it finishes transmitting the associated data buffer. cslcarrier sense lost this bit indicates that the carrier sense was lost during frame transmission. the sccx ethernet controller writes this bit after it finishes transmitting the associated data buffer. data length this field represents the number of octets the sccx ethernet controller must transmit from this buffer descriptor data buffer. it is never modified by the communication processor module. the value of this field must be greater than zero. the sccx ethernet controller writes these bits after it finishes transmitting the associated data buffer. tx data buffer pointer this field contains the address of the associated data buffer, can be even or odd, and reside in internal or external memory. this value is never modified by the communication processor module. the sccx ethernet controller writes these bits after it finishes transmitting the associated data buffer.
communication processor module 16-346 mpc823e reference manual motorola sccs communication 16 processor module 16.9.23.4 sccx ethernet event register. when a serial communication controller is in ethernet mode, the 16-bit memory-mapped sccx event register is referred to as the sccx ethernet event register (scceCethernet). since each protocol has specific requirements, the scce bits are different for each implementation. this register is used to generate interrupts and report events recognized by the ethernet channel. when an event is recognized, the sccx ethernet controller sets the corresponding bit in the scceC ethernet register. interrupts generated by this register can be masked in the sccmC ethernet register. an example of interrupts that can be generated in the ethernet protocol is illustrated in figure 16-111. a bit is cleared by writing a 1(writing a zero has no effect) and more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared at reset and can be read at any time. bits 0C7 and 9C10reserved these bits are reserved and must be set to 0. gragraceful stop complete if set, this bit indicates that a graceful stop, initiated by the graceful stop transmit command, is now complete. this bit is set as soon the transmitter finishes any frame in progress when the command is issued. it is set immediately if no frame is in progress when the command is issued. txetx error this bit indicates that an error has occurred on the transmitter channel. rxfrx frame this bit indicates that a complete frame has been received on the ethernet channel. bsybusy condition this bit indicates when a frame is received and discarded due to a lack of buffers. scceCethernet bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved gra reserved txe rxf bsy txb rxb reset 0 0 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa30
communication processor module motorola mpc823e reference manual 16-347 communication 16 processor module sccs txbtx buffer this bit indicates that a buffer has been transmitted on the ethernet channel. rxbrx buffer this bit indicates that a buffer that was not a complete frame was received on the ethernet channel. figure 16-110. ethernet interrupt events example line idle stored in rx buffer frame received in ethernet time rxd line idle line idle stored in tx buffer clsn line idle txd tena rxb txb notes: 1. rxb event assumes receive buffers are 64 bytes each. 2. the rena events, if required, must be programmed in the port c parallel i/o, not in the scc itself. 3. the rxf interrupt may occur later than rena due to receive fifo latency. legend: p = preamble, sfd = start frame delimiter, da and sa = source/destination address, t/l = type/length, d = data, and cr = crc bytes. notes: 1. txb events assume the frame required two transmit buffers. 2. the gra event assumes a graceful stop transmit command was issued during frame transmission. 3. the tena or clsn events, if required, must be programmed in the port c parallel i/o, not in the scc itself. ethernet scce events hdlc scce events frame transmitted by ethernet da sa t/l cr d rxf p rena sfd da sa t/l cr d p txb gra sfd
communication processor module 16-348 mpc823e reference manual motorola sccs communication 16 processor module 16.9.23.5 sccx ethernet mask register. when a serial communication controller is in ethernet mode, the 16-bit read/write sccx mask register is referred to as the sccx ethernet mask register (sccmCethernet). since each protocol has specific requirements, the sccm bits are different for each implementation. this register has the same bit formats as the scceCethernet register. if a bit in the sccmCethernet register is a 1, the corresponding interrupt in the scceCethernet register is enabled. if the bit is zero, the corresponding interrupt in the scceCethernet register is masked. 16.9.23.6 sccx ethernet status register. since all ethernet mode selections are in the gsmr_x and psmr registers, the sccx ethernet status register (sccsCethernet) is not used when an sccx is in ethernet mode. the current state of the rena and clsn signals can be found in port c, which is described in section 16.14.9 port c registers . 16.9.23.7 scc2 ethernet programming example. the following is an example initialization sequence for the scc2 in ethernet mode. the clk1 pin is used for the ethernet receiver and the clk2 pin is used for the transmitter. 1. configure the port a pins to enable the txd1 and rxd1 pins. write papar bits 12 and 13 with ones, padir bits 12 and 13 with zeros, and paodr bit 13 with zero. 2. configure the port c pins to enable cts2 (clsn) and cd2 (rena). write pcpar and pcdir bits 9 and 8 with zeros and pcso bits 9 and 8 with ones. 3. do not enable the rts2 (tena) pin yet because the pin is still functioning as rts and transmission on the lan could accidentally begin. 4. configure port a to enable the clk1 and clk2 pins. write papar bits 7 and 6 with ones and padir bits 7 and 6 with zeros. 5. connect the clk1 and clk2 pins to scc2 using the serial interface. write the r2cs field in the sicr to 101 and the t2cs field to 100. 6. connect the scc2 to the nmsi and clear the sc2 bit in the sicr. 7. initialize the sdma configuration register (sdcr) to 0x0001. 8. write rbase and tbase in the scc2 parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of the dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. sccmCethernet bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved gra reserved txe rxf bsy txb rxb reset 0 0 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa34
communication processor module motorola mpc823e reference manual 16-349 communication 16 processor module sccs 9. program the cpcr to execute the init rx bd parameter command for this channel. 10. write rfcr and tfcr with 0x18 for normal operation. 11. write mrblr with the maximum number of bytes per receive buffer. for this case, assume 1,520 bytes, so mrblr = 0x05f0. in this example, the user wants to receive an entire frame into one buffer, so the mrblr value is chosen to be the first value larger than 1,518 that is evenly divisible by four. 12. write c_pres with 0xffffffff to comply with 32-bit ccitt-crc. 13. write c_mask with 0xdebb20e3 to comply with 32-bit ccitt-crc. 14. clear crcec, alec, and disfc for clarity. 15. write pad with 0x8888 for the pad value. 16. write ret_lim with 0x000f. 17. write mflr with 0x05ee to make the maximum frame size 1,518 bytes. 18. write minflr with 0x0040 to make the minimum frame size 64 bytes. 19. write maxd1 and maxd2 with 0x05ee to make the maximum dma count 1,518 bytes. 20. clear gaddr1Cgaddr4. the group hash table is not used. 21. write paddr1_h with 0x0380, paddr1_m with 0x12e0, and paddr1_l with 0x5634 to configure the physical address 8003e0123456. 22. write p_per with 0x0000. it is not used. 23. clear iaddr1Ciaddr4. the individual hash table is not used. 24. clear taddr_h, taddr_m, and taddr_l for clarity. 25. initialize the rx buffer descriptor and assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. 26. initialize the tx buffer descriptor and assume the tx data frame is at 0x00002000 in main memory and contains fourteen 8-bit characters (destination and source addresses plus the type field). write 0xfc00 to tx_bd_status, add pad to the frame and generate a crc. then write 0x000d to tx_bd_length and 0x00002000 to tx_bd_pointer. 27. write 0xffff to the scceCethernet to clear any previous events. 28. write 0x001a to the sccmCethernet to enable the txe, rxf, and txb interrupts. 29. write 0x20000000 to the cimr so that scc2 can generate a system interrupt. the cicr must also be initialized. 30. write 0x00000000 to the gsmr_h to enable normal operation of all modes.
communication processor module 16-350 mpc823e reference manual motorola usb communication 16 processor module 31. write 0x1088000c to the gsmr_l to configure the cts2 (clsn) and cd2 (rena) pins to automatically control transmission and reception (diag field) and the ethernet mode. tci is set to allow more setup time for the eest to receive the mpc82e transmit data. tpl and tpp are set for ethernet requirements. the dpll is not used with ethernet. notice that the transmitter (ent) and receiver (enr) have not been enabled yet. 32. write 0xd555 to the dsr. 33. set the psmrCscc ethernet to 0x0a0a to configure 32-bit crc, promiscuous mode and begin searching for the start frame delimiter 22 bits after rena. 34. enable the tena pin (rts2 ). since the mode field of the gsmr_l is written to ethernet, the tena signal is low. write pcpar bit 14 with a one and pcdir bit 14 with a zero. 35. write 0x1088003c to the gsmr_l register to enable the scc2 transmitter and receiver. this additional write ensures that the ent and enr bits are enabled last. 16.10 universal serial bus controller the universal serial bus (usb) is an industry standard extension to the pc architecture. the usb controller allows the mpc823e to exchange data with a pc host. it supports data exchanges between a host computer and a wide range of simultaneously accessible peripherals. the attached peripherals share usb bandwidth through a host scheduled token-based protocol. the usb physical interconnect is a tiered star topology. a hub is at the center of each star. each wire segment is a point-to-point connection between the host and a hub or function or a hub connected to another hub/function. there is only one host in any usb system. the usb transfers signals and power over a four-wire cable. the signalling occurs over two wires and point-to-point segments. the usb full-speed signalling bit rate is 12mbps. a limited capability low-speed signalling mode is also defined at 1.5mbps. the mpc823e usb controller consists of a transmitter module, receiver module, and two protocol state machines. the protocol state machines control the receiver and transmitter modules. one state machine implements the function state diagram and the other implements the host state diagram. the mpc823e usb controller is capable of implementing a usb function endpoint, a usb host, or both for testing purposes (loop-back diagnostics). figure 16-111 illustrates the usb controller block diagram. for usb implementation, it is recommended that you get a copy of the usb specification as a supplement to this manual. you can download a copy from http://www.usb.org . note: after 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of crc) are transmitted, the tx buffer descriptor is closed. additionally, the receive buffer is closed after a frame is received. any data received after 1,520 bytes or a single frame causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module motorola mpc823e reference manual 16-351 usb communication 16 processor module the usb transmitter contains four independent fifos, each containing 16 bytes. there is a dedicated fifo for each of the four supported endpoints. the usb receiver has a single 16-byte fifo. when the usb controller is not enabled in the usb mode register, it consumes minimal power. figure 16-111. usb controller block diagram mode register peripheral bus u-bus command register port control transmitter receiver usb function endpoint dpll/ bus rx fifo tx data fifo tx data fifo tx data fifo tx data fifo endpoint registers address register port configuration external transceiver interface and host state machines
communication processor module 16-352 mpc823e reference manual motorola usb communication 16 processor module 16.10.1 features the following list summarizes the usb slave mode features: ? supports usb slave mode ? four independent endpoints support control, bulk, interrupt and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decoding with bit stuffing ? 12 or 1.5mbps data rate ? flexible data buffers with multiple buffers per frame ? automatic retransmission upon transmit error the following list summarizes the usb host controller features: ? supports control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decoding with bit stuffing ? 12 and 1.5mbps data rates (automatic generation of pre token and data rate configuration) ? flexible data buffers with multiple buffers per frame ? supports local loopback mode for diagnostics (12mbps only) 16.10.2 controller limitations the following tasks are not supported by the hardware and must be implemented by software: ? crc5 generation for token packets. since crc5 is calculated on 11 bits, this must not impose a large cpu overhead. ? retransmission after an error and error recovery. ? generation and transmission of sof token every 1ms. ? scheduling the various transfers within frame and between frames. ? the mpc823e usb host controller does not integrate the root hub. an external hub is required when more than one device is connected to the host. ? the host controller programming model is very similar to the function endpoint programming model and does not conform to the open host controller interface (ohci). although motorola plans to support full host functionality, our implementation will not be ohci or uhci (universal host controller interface) compatible. those standards define the software programming model so that software drivers can be hardware-independent. our implementation has a much more simplified software interface.
communication processor module motorola mpc823e reference manual 16-353 usb communication 16 processor module 16.10.3 usb controller pin functions and clocking the usb controller interfaces to the usb through a differential line driver and receiver. the oe signal enables the line driver when the usb controller transmits on the bus. there are six i/o port pins associated with the usb port and their functionality is described in table 16-31 . some transceivers may need additional control lines (speed select or low-power control), which can be supported by the general-purpose output lines. mpc823e figure 16-112. usb interface usbtxp usbrxd d+ d- usboe usbtxn usbrxp usbrxn + C usb transceiver
communication processor module 16-354 mpc823e reference manual motorola usb communication 16 processor module the usb controller accepts a reference clock that is four times the usb bit rate. this clock is programmed in the r1cs field of the serial interface clock register (sicr) and used by the dpll circuitry to recover the bit rate clock. refer to section 16.7.5.3 serial interface clock route register for more information. a system clock frequency of at least 40mhz is necessary for operating the usb controller in high-speed mode using an externally supplied 48mhz reference clock. alternatively, a system clock frequency of an exact integral multiple of 48mhz is necessary for operating the usb controller in high-speed mode using an internal brg to supply the 48mhz reference clock. table 16-31. usb pin functionality pin symbol i/o function usbtxn, usbtxp o outputs from the usb transmitter, inputs to the differential driver. usboe o output enable. active low, enables the transceiver to transmit data on the bus. usbrxd i receive data. input the usb receiver from the differential line receiver. ubrxp, usbrxn i gated version of d+ and d-. used to detect single-ended zero, and interconnect speed. note: the mpc823e can run at different frequencies, but the usb reference clock must be four times the usb bit rate. the reference clock must be 48mhz for a 12mb full-speed transfer or 6mhz for a 1.5mb low-speed transfer. tp tn result 0 0 single ended 0 0 1 logic 0 1 0 logic 1 1 1 n/a rp rn result 0 0 single ended 0 1 0 full speed 0 1 low speed 1 1 n/a
communication processor module motorola mpc823e reference manual 16-355 usb communication 16 processor module 16.10.4 transmission and reception process after reset, the usb controller is addressable at the default address (0x00). during the enumeration process, the host assigns a unique address to the usb controller. the software must program the usb address register with the assigned address. the usb controller supports four independent endpoints, which can each be configured to support control, interrupt, bulk, or isochronous transfers modes when you program the usb endpoint registers. once enabled, the usb controller looks for valid token packets. tokens that are not valid (the pid or crc check fails or the packet length is not 3 bytes) are ignored. note: you must configure endpoint 0 as a control transfer type. this endpoint is used by the usb system software as a control pipe and any additional control pipes may be provided by other endpoints. figure 16-113. usb controller operating modes reset unenumerated idle setup transmit receive sof setup token in token out token sof token enumeration process
communication processor module 16-356 mpc823e reference manual motorola usb communication 16 processor module 16.10.4.1 out token. when the usb controller receives an out token, data reception begins. the usb controller fetches the next buffer descriptor associated with the endpoint and if it is empty, it starts transferring the incoming packet to the buffer descriptors associated data buffer. when the data buffer has been filled, the usb controller clears the e bit in the rx buffer descriptor and generates an interrupt if the i bit in the buffer descriptor is set. if the incoming packet exceeds the length of the data buffer, the usb controller fetches the next buffer descriptor in the table and, if it is empty, continues transferring the rest of the packet to this buffer descriptors associated buffer. otherwise, if it is full, an error occurs. the entire data packet, including the data0/data1 packet id (pid), is written to the receive buffers and the pid is reflected in the pid field of the receive buffer descriptor. it is your responsibility to program the driver software to check data packet synchronization by monitoring the data0/data1 pid sequence toggle. if the packet was received error-free (no crc errors and no bit stuff error), depending on the endpoint transfer mode configuration, an ack handshake will be transmitted to the host. if a reception error occurred, no handshake packet is returned, and the error status bits will be set in the last buffer descriptor associated with this packet. if the rhs field in the endpoints configuration register is programmed to respond with nak, a nak handshake is returned instead of ack. if the rhs field is programmed to respond with stall, a stall handshake is returned. in both cases, the buffer will receive the data packet if the buffer descriptors are available. table 16-32. usb out token reception data packet corrupted usep x rhs field handshake sent to host yes n/a none (data discarded) no 00 (normal) ack no 01 (ignore) none no 10 (nak) nak no 11 (stall) stall
communication processor module motorola mpc823e reference manual 16-357 usb communication 16 processor module 16.10.4.2 in token. to guarantee data transfer, the control software must preload the endpoint fifo with a data packet prior to receiving an in token. the software must set up the endpoint transmit buffer descriptor table and set the str bit in the usb command register. the usb controller will fill the transmit fifo and wait until it receives the in token. once it is received and the fifo is loaded with the last byte of the data (or at least 4 bytes), transmission begins. if data is not ready in the transmit fifo or if the ths field in the endpoints configuration register is set to respond with nak, a nak handshake is returned. if the ths field in the endpoints configuration register is set to respond with stall, a stall handshake is returned. when the end of the current buffer descriptor has been reached and the last buffer in the packet bit is set, the crc is appended. following the transmission of a frame, the usb controller waits for a handshake packet, depending on the configuration of the endpoint. if the host fails to acknowledge the packet, the timeout status bit will be set in the buffer descriptor. it is your responsibility to program the driver software to set the proper data0/data1 pid in the transmitted packet. 16.10.4.3 setup token. setup transactions are similar in format to an out token, but you must use a setup rather than an out pid. a setup token is only recognized by an endpoint that is configured as a control endpoint. once the setup token is received, setup data reception begins. the usb controller fetches the next buffer descriptor associated with the endpoint, and if it is empty, starts transferring the incoming packet to the buffer descriptors associated data buffer. when the data buffer has been filled, the usb controller clears the e bit in the rx buffer descriptor and generates an interrupt if the i bit in the buffer descriptor is set. if the incoming packet exceeds the length of the data buffer, the usb controller fetches the next buffer descriptor in the table and, if it is empty, continues transferring the rest of the packet to this buffer descriptors associated buffer. if it is full, an error occurs. the entire data packet including the data0 pid are written to the receive buffers. if the packet was received error-free (no crc errors and no bit stuff error) an ack handshake will be transmitted to the host. if a reception error occurred, no handshake packet will be returned and the error status bits will be set in the last buffer descriptor associated with this packet. table 16-33. usb in token reception fifo loaded with data usep x ths field handshake sent to host no 00 (normal) nak yes 00 (normal) ack n/a 01 (ignore) none n/a 10 (nak) nak n/a 11 (stall) stall
communication processor module 16-358 mpc823e reference manual motorola usb communication 16 processor module 16.10.4.4 sof token. when a start of frame (sof) token packet is received, the usb controller issues a sof maskable interrupt and the frame number entry in the parameter ram is updated. 16.10.4.5 pre token. the pre token signals the hub that a low-speed transaction is about to occur. the pre token is only read by the hub. the usb controller ignores the pre token in slave mode. in host mode, the usb controller generates a full-speed pre token before any packet is sent to a low-speed peripheral. 16.10.5 usb controller parameter ram memory map the usb controller parameter ram area begins at the usb base address. the area is used for the general usb parameters. notice that it is similar to the sccx general-purpose parameter ram. table 16-34. usb parameter ram memory map address name width description usb base + 00 ep0ptr half word endpoint 0 register usb base + 02 ep1ptr half word endpoint 1 register usb base + 04 ep2ptr half-word endpoint 2 register usb base + 06 ep3ptr half word endpoint 3 register usb base + 08 rstate word rx internal state usb base + 0c rptr word rx internal data pointer usb base + 10 frame_n half word frame number usb base + 12 rbcnt half-word rx internal byte count usb base + 14 rtemp word rx temp note: you are only responsible for initializing the items in bold. usb base = (immr & 0xffff0000) + 0x3c00. all references to registers in the parameter ram table are actually implemented in the dual-port ram area as a memory-based register.
communication processor module motorola mpc823e reference manual 16-359 usb communication 16 processor module you must initialize certain parameter ram values before the usb controller is enabled. other values are initialized by the communication processor module. once initialized, the parameter ram values do not need to be accessed by your software. they must only be modified when there is no usb activity. ? epxptrthe endpoint parameters block pointers are index pointers to the endpoints parameter block. the parameter block can be allocated to any address divisible by 32 in the dual-port ram. the format of the endpoint parameter block is shown in table 16-35. ? frame_nthe frame number entry is updated by the usb controller when a sof token is received. the entry contains 11 bits representing the frame number. an sof interrupt is issued when this entry is updated . you must initialize this parameter to zero before operating the usb controller. ep x ptr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field endpoint index pointer 00000 r/w r/w r/w r/w r/w r/w r/w reset 0 00000 addr usb base + 0x00 (ep0ptr), 0x02 (ep1ptr), 0x04 (ep2ptr), 0x06 (ep3ptr) frame_n bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field v reserved frame number r/w r/w r/w r/w reset 00 0 addr usb base + 0x10
communication processor module 16-360 mpc823e reference manual motorola usb communication 16 processor module the v bit is set if the sof token was received error-free. ? rbase and tbasethe receive and transmit buffer descriptor base address entries define the starting point in the dual-port ram for the set of buffer descriptors to receive and transmit data. this provides a great deal of flexibility in partitioning the buffer descriptors for the usb controller. by setting the w bit in the last buffer descriptor in each list, you can select how many buffer descriptors to allocate for the transmit and receive side of the usb controller. however, you must initialize these entries before enabling the usb controller. furthermore, you must not configure buffer descriptor tables of the usb to overlap any other serial channels buffer descriptors or erratic operation will occur. table 16-35. endpoint parameters block address name width description base + 00 rbase half word rx buffer descriptor base address base + 02 tbase half word tx buffer descriptor base address base + 04 rfcr byte rx function code base + 05 tfcr byte tx function code base + 06 mrblr half word maximum receive buffer length base + 08 rbptr half word rx buffer descriptor pointer base + 0a tbptr half word tx buffer descriptor pointer base + 0c tstate word tx internal state base + 10 tptr word tx internal data pointer base + 14 tcrc half word tx temp crc base + 16 tbcnt half word tx internal byte count base + 18 res 8 bytes reserved note: you are only responsible for initializing the items in bold. also, base = (ep x ptr). note: rbase and tbase must contain a value that is divisible by eight.
communication processor module motorola mpc823e reference manual 16-361 usb communication 16 processor module ? rfcr and tfcrthe usb function code registers control the value that you want to appear on the at pins when the associated sdma channel accesses memory. it also controls the byte-ordering convention to be used in the transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering set this field to select the required byte ordering for the data buffer. if this field is modified on-the-fly, it will take effect at the beginning of the next frame. 00 = the dec/intel convention is used for byte ordering (swapped operation). it is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed as compared to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double word. 1x = motorola byte ordering (normal operation). it is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type 1C3 this field contains the function code value used during this sdma channels memory accesses. at0 will be driven with a one to identify this sdma channel access as a dma-type access. ? mrblrthe maximum receive buffer length register defines the maximum number of bytes that the mpc823e will write to the usb receive buffer before moving to the next buffer. mrblr must be divisible by four. the mpc823e can write fewer bytes to the buffer than the mrblr value if a condition such as an error or end-of-packet occurs, but it will never write more bytes than the mrblr value. your receive buffers must always be at least as long as mrblr+2 bytes. the two additional bytes allow for a 6-bit crc. the transmit buffers for the usb channel are not affected by the value programmed into mrblr. transmit buffers may be individually chosen to have varying lengths, as needed. the number of bytes to be transmitted is chosen by programming the data length field in the tx buffer descriptor. rfcr and tfcr bit 0 1 2 3 4 5 6 7 field reserved bo at
communication processor module 16-362 mpc823e reference manual motorola usb communication 16 processor module ? rbptrthe receive buffer descriptor pointer points to the next buffer descriptor that the receiver will transfer data to when it is in an idle state or to the current buffer descriptor while processing a frame. rbptr must be initialized by the software after reset. when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the rbase entry. although you never need to write rbptr in most applications (except initialization), you can modify it when the receiver is disabled or when you are sure that no receive buffer is currently in use. ? tbptrthe transmit buffer descriptor pointer for each usb endpoint points to the next buffer descriptor that the transmitter will transfer data from when it is in an idle state or to the current buffer descriptor during frame transmission. tbptr must be initialized by the software after reset. when the end of buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the tbase entry. although you never need to write tbptr in most applications (except initialization), you can modify it when the transmitter is disabled or when you are sure that no transmit buffer is currently in use. ? tstatethe transmit internal state entry must be initilaized to zero before enabling the usb controller. ? other general parametersthese are the additional parameters listed in table 16-34 and table 16-35. you do not need to access these parameters for normal operation and they are only listed because they provide helpful information for debugging purposes. the rx and tx internal data pointers (rptr and tptr) are updated by the sdma channels to indicate the next address in the buffer to be accessed. tx internal byte count (tbcnt) is a down-count value that is initialized with the tx buffer descriptors data length field and decremented with every byte read by the sdma channels. rx internal byte count (rbcnt) is a down-count value that is initialized with the mrblr value and decremented with every byte written by the sdma channels. rstate, tstate, rtemp, ttemp, and the reserved areas are only used by the risc microcontroller. note: mrblr is not intended to be dynamically changed while the usb channel is operating. however, if it is modified in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back), then a dynamic change in the receive buffer length can be successfully achieved. this occurs when the communication processor module transfers control to the next rx buffer descriptor in the table. thus, a change to mrblr will not have an immediate effect. to guarantee the exact rx buffer descriptor on which the change will occur, you must change mrblr only while the usb receiver is disabled.
communication processor module motorola mpc823e reference manual 16-363 usb communication 16 processor module 16.10.6 usb commands you can program the cpm command register (cpcr) with the following commands to transmit data. ? rstthe reset bit is set by the core and cleared by the communication processor module and when this command is executed, rst and flg are cleared within two general system clocks. the risc microcontroller reset routine is approximately 60 clocks long, but you can start initializing the communication processor module immediately after this command is issued. rst is useful when the core wants to reset the registers and parameters for all the channels as well as the risc microprocessor and timer tables. however, this bit does not affect the serial interface or parallel i/o registers. ? usbcmdthis field contains the usb command. 001 = the stop tx endpoint command disable the transmission of data on the selected endpoint. after you issue the command, flush the corresponding endpoint fifo. no further transmissions will occur until the restart tx endpoint command is issued. 010 = the restart tx endpoint command enables the transmission of data from the corresponding endpoint on the usb. this command is expected by the usb controller after a stop tx endpoint command is issued or after a transmission error (underrun or timeout) occurs. 000 = reserved. 011 = reserved. 100 = reserved. 101 = reserved. 110 = reserved. 111 = reserved. ? endpointthis bit is the logical pipe number. 00 = endpoint 0. 01 = endpoint 1. 10 = endpoint 2. 11 = endpoint 3. usb command format (cpcr) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rst usbcmd 11110000 endpoint res flg reset 0 0 00000000 0 00 r/w r/w rw/ r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x9c0
communication processor module 16-364 mpc823e reference manual motorola usb communication 16 processor module ? flgthe bit is set by the core and cleared by the communication processor module. 0 = the communication processor module is ready to receive a new command. 1 = the cpcr contains a command that the communication processor module is currently processing. the communication processor module clears this bit when the command finishes executing or after reset. for additional opcode information, see table 16-2. 16.10.7 usb controller errors the usb controller reports frame reception and transmission error conditions using the channel buffer descriptors and the usb event register. the following transmission errors can be detected by the usb controller. ? transmit underrun errorif this error occurs, the channel forces a bit-stuffing violation, terminates buffer transmission, closes the buffer, sets the un bit in the tx buffer descriptor, and sets the corresponding txex bit in the usb event register. the endpoint resumes transmission after the restart tx endpoint command is received. ? transmit timeout errorif this error occurs, the channel tries to retransmit if the rte bit is set in the usb endpoint configuration registers. if the rte bit is not set or the second attempt fails, the channel closes the buffer, sets the to bit in the tx buffer descriptor, and sets the corresponding txex bit in the usb event register. the endpoint resumes transmission after the restart tx endpoint command is received. the following reception errors can be detected by the usb controller. ? overrun errorthe usb controller maintains an internal fifo for receiving data. if a receive overrun occurs, the channel writes the received data byte to the internal fifo over the previously received byte. the channel closes the buffer, sets the ov bit in the rx buffer descriptor, and sets the rxb bit in the usb event register. the nak handshake is transmitted at the end of the received packet if the packet was error-free. ? busy errora frame was received and discarded due to a lack of buffers. the channel sets the bsy bit in the usb event register. ? non octet aligned packet errorif this error occurs, the channel writes the received data to the data buffer, closes the buffer, sets the no bit in the rx buffer descriptor, and generates a rxb interrupt. ? crc errorwhen a crc error occurs, the channel closes the buffer, and sets the cr bit in the rx buffer descriptor and the rxb bit in the usb event register. in isochronous mode, the usb controller reports a crc error, however, there are no handshake packets (ack) and the transfer continues normally when an error occurs.
communication processor module motorola mpc823e reference manual 16-365 usb communication 16 processor module 16.10.8 usb controller programming model 16.10.8.1 usb mode register. the read/write usb mode (usmod) register controls the usb controllers operation mode. lsslow-speed signaling when set, this bit selects low-speed (1.5mbps) signaling. the actual bit rate depends on the usb clock source. 0 = full-speed (12mbps) signaling. normal operation mode. 1 = low-speed (1.5mbps) signaling. this mode can be used for a point-to-point connection to a low-speed device or in local loopback mode. resumegenerate resume condition when set, this bit generates a resume condition on the usb. this bit must be used if the function wants to exit suspend mode. bits 2C4reserved these bits are reserved and must be set to zero. testtest mode 0 = normal operation. 1 = local loopback mode. in this mode, if the host bit is set, endpoint 0 operates as host and endpoints 1C3 can be used as function endpoints. hosthost mode 0 = the usb controller implements a usb function. 1 = the usb controller implements a usb host. endpoint 0 operates as the host. the other endpoints are not used, unless the test bit is set. usmod bit 0 1 2 3 4 5 6 7 field lss resume reserved test host en reset 00 0 000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa00
communication processor module 16-366 mpc823e reference manual motorola usb communication 16 processor module enenable usb this bit enables usb operation. when the en bit is cleared, the usb is in a reset state and consumes minimal power. 0 = usb is disabled. 1 = usb is enabled. 16.10.8.2 usb receive buffer descriptor. the usb controller reports information about each buffer of received data using (rx) buffer descriptors. the usb controller closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current buffer is full. additionally, it will close the buffer under the following conditions: ? when an end of packet is detected ? when an overrun error occurs ? when a bit stuff violation is detected the first word of the rx buffer descriptor contains status and control bits. it is recommended that you prepare these bits before reception because they are set by the usb controller after the buffer has been closed. the second word contains the data length (in bytes) that was received. the third and fourth words contain a pointer that always points to the beginning of the received data buffer. note: you must not modify any other bits of the usmod register while the en bit is set. note: the buffer descriptors status bits are sticky. applications that operate on those bits may need to be reset after every relevant cpm transaction. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi l f res pid res no ab cr ov res offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module motorola mpc823e reference manual 16-367 usb communication 16 processor module eempty 0 = the data buffer associated with this rx buffer descriptor has been filled with received data or data reception has been aborted due to an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module will not use this buffer descriptor again when the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or reception is currently in progress. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core cannot write any fields to this rx buffer descriptor. bits 6C7, 10 and 15reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor in the table (the buffer descriptor pointed to by rbase). the number of rx buffer descriptors in this table is programmable and determined only by the w bit and the overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer has been filled. 1 = the rxb bit in the usb event register will be set when this buffer has been completely filled by the communication processor module, thus indicating the need for the core to process the buffer. the rxb bit can cause an interrupt if it is enabled. this bit is written by the usb controller after the received data has been placed into the associated data buffer. llast this bit is set by the usb controller when the buffer is closed due to the detection of an end-of-packet condition on the bus or as the result of an error. this bit is written by the usb controller after the received data has been placed into the associated data buffer. 0 = this buffer does not contain the last character of the message. 1 = this buffer contains the last character of the message. ffirst this bit is set by the usb controller when the buffer contains the first byte of a packet. this bit is written by the usb controller after the received data has been placed into the associated data buffer. 0 = this buffer does not contain the first byte of the message. 1 = this buffer contains the first byte of the message.
communication processor module 16-368 mpc823e reference manual motorola usb communication 16 processor module pidpacket id this field is set by the usb controller to indicate the type of the packet. it is only valid if the f bit is set. this field is written by the usb controller after the received data has been placed into the associated data buffer. 00 = this buffer contains a data0 packet. 01 = this buffer contains a data1 packet. 10 = this buffer contains a setup packet (data0). 11 = reserved. norx non octet aligned packet this bit indicates that a packet containing a number of bits not exactly divisible by eight has been received. this bit is written by the usb controller after the received data has been placed into the associated data buffer. abframe aborted this bit indicates that a bit stuff error has occurred during reception. this bit is written by the usb controller after the received data has been placed into the associated data buffer. crcrc error this bit indicates that a frame contains a crc error. the received crc bytes are always written to the receive buffer. this bit is written by the usb controller after the received data has been placed into the associated data buffer. ovoverrun this bit indicates that a receiver overrun has occurred during reception. this bit is written by the usb controller after the received data has been placed into the associated data buffer. data length this field represents the number of octets that the communication processor module has written into this buffer descriptors data buffer. the communication processor module writes to this field when the buffer descriptor is closed. rx data buffer pointer this field always points to the first location of the associated data buffer and must be divisible by four. the buffer may reside in either internal or external memory. note: the actual amount of memory allocated for this buffer must be equal to the contents of the mrblr, plus two crc bytes that are included in the rx buffer. the usb device driver may strip out these two bytes before the data is sent to your application.
communication processor module motorola mpc823e reference manual 16-369 usb communication 16 processor module 16.10.8.3 usb transmit buffer descriptor. data to be transmitted with the usb is presented to the communication processor module by arranging it in buffers referenced by the transmit (tx) buffer descriptor ring. the first word of the tx buffer descriptor contains status and control bits. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 = the data buffer, which you have prepared for transmission, has not been transmitted or is currently being transmitted. you cannot write to the fields of this buffer descriptor once this bit is set. bits 1, 10 and 15reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer has been used, the communication processor module will transmit incoming data from the first buffer descriptor in the table (the buffer descriptor pointed to by tbasex). the number of tx buffer descriptors in this table is programmable and is determined only by the w bit and the overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer has been serviced. 1 = the txb or txex bit in the usb event register is set when this buffer is serviced. txb and txex can cause interrupts if they are enabled. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res w i l tc cnf lsp pid res nak stal to un res offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-370 mpc823e reference manual motorola usb communication 16 processor module llast 0 = this buffer does not contain the last character of the message. 1 = this buffer contains the last character of the message. tctransmit crc this bit is only valid when the l bit is set. otherwise, it is ignored. 0 = transmit end-of-packet after the last data byte. this setting can be used for testing purposes to send a bad crc after the data. 1 = transmit the crc sequence after the last data byte. cnftransmit confirmation (host) this bit is only valid when the l bit is set. otherwise, it is ignored. it only affects endpoints that have the mf bit set in the endpoint configuration register. 0 = continue to load the transmitter fifo with the next packet. no handshake or response is expected from the function for this packet. 1 = wait for handshake or response from the function before starting the next packet or if this is the last packet. lsplow-speed transaction (host) 0 = the following transaction is with the host or a full-speed device. 1 = the following transaction is with a low-speed device (required only for data buffers containing a token).. pidpacket id this field is set by the software to indicate the packet type. it is only valid for the first buffer descriptor of a packet. 0x = do not append pid to the data. 10 = transmit data0 pid before sending the data. 11 = transmit data1 pid before sending the data. naknak handshake received (host) this bit indicates that the endpoint has responded with a nak handshake. the packet was received error-free, however, the endpoint could not accept it. this bit is written by the usb controller after it has finished transmitting the associated data buffer. note: you cannot set cnf to 0 for a token that must be followed by a data packet if the data packet buffer descriptor is not ready. note: you must always set lsp to 0 in slave mode.
communication processor module motorola mpc823e reference manual 16-371 usb communication 16 processor module stalstall handshake received (host) this bit indicates that the endpoint has responded with a stall handshake. the endpoint needs attention through the control pipe. this bit is written by the usb controller after it has finished transmitting the associated data buffer. totime-out this bit indicates that the endpoint has failed to acknowledge this packet. this bit is written by the usb controller after it has finished transmitting the associated data buffer. ununderrun this bit indicates that the usb controller has encountered a transmitter underrun condition while transmitting the associated data buffer. this bit is written by the usb controller after it has finished transmitting the associated data buffer. data length this field represents the number of octets that the communication processor module must transmit from this buffer descriptors data buffer. it is never modified by the communication processor module. this value must normally be greater than zero. tx data buffer pointer this field always points to the first location of the associated data buffer and can be even or odd. the buffer can reside in either internal or external memory. 16.10.8.4 usb slave address register. the 8-bit, memory-mapped, read/write usb address register (usadr) holds the address for this usb port in slave mode. bit 0reserved this bit is reserved and must be set to 0. sadslave address 0C6 this field contains the slave address for the usb port. usadr bit 0 1 2 3 4 5 6 7 field reserved sad reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0xa01
communication processor module 16-372 mpc823e reference manual motorola usb communication 16 processor module 16.10.8.5 usb command register. the 8-bit, read/write usb command (uscom) register is used to start usb transmit operation. strstart fifo fill when set, this bit causes the usb controller to start filling the corresponding endpoint transmit fifo with data. actual transmission will begin once the in token for this endpoint is received. the str bit is always read as a zero. flushflush fifo when set, this bit causes the usb controller to flush the corresponding endpoint transmit fifo. before flushing the fifo, you must issue the stop tx endpoint command. after you flush the fifo, issue the restart tx endpoint command (see section 16.10.6 usb commands for more information). the flush bit is always read as a zero. bits 2C5reserved these bits are reserved and must be set to zero. ependpoint this field selects one of the four supported endpoints. uscom bit 0 1 2 3 4 5 6 7 field str flush reserved ep reset 00 0 0 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa02
communication processor module motorola mpc823e reference manual 16-373 usb communication 16 processor module 16.10.8.6 usb endpoint configuration registers 0C3. there are four 16-bit, memory-mapped, read/write usb endpoint configuration (usepx) registers. epn endpoint number this field defines the supported endpoint number. it is used in slave mode and ignored in host mode. bits 4C5 and 8C9reserved these bits are reserved and must be set to 0. tmtransfer mode 00 = control. 01 = interrupt. 10 = bulk. 11 = isochronous. mfenable multi-frame this bit allows loading of the next transmit packet into the fifo before the previous packet finishes transmitting. this bit must be set to zero, unless the endpoint is configured for isochronous transfer mode or the endpoint is configured as a host (endpoint 0 only). 0 = the transmit fifo can hold only one packet. 1 = the transmit fifo can hold more than one packet. rteretransmit enable this bit must be set to zero for an endpoint configured for isochronous transfer mode. 0 = no retransmission. 1 = automatic frame retransmission is enabled. the frame is retransmitted if a transmit an error occurred (time-out). usep0Cusep3 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field epn reserved tm reserved mf rte ths rhs reset 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa04 (usep0), 0xa06 (usep1), 0xa08 (usep2), 0xa0a (usep3) note: the rte bit can only be set if the transmit packet is contained in a single buffer. otherwise, retransmission must be handled by software intervention.
communication processor module 16-374 mpc823e reference manual motorola usb communication 16 processor module thstransmit handshake (slave mode only) 00 = normal handshake. 01 = ignore in token. 10 = force nak handshake. not allowed for control endpoint. 11 = force stall handshake. not allowed for control endpoint. rhsreceive handshake (slave mode only) 00 = normal handshake. 01 = ignore out token. 10 = force nak handshake. not allowed for control endpoint. 11 = force stall handshake. not allowed for control endpoint. 16.10.8.7 usb buffer descriptor ring. the data associated with the usb channel is stored in buffers that are referenced by buffer descriptors organized in buffer descriptor rings located in the dual-port ram. these rings have the same basic configuration as those used by the serial communication controllers and serial management controllers. there are four separate transmit buffer descriptor rings and four separate receive buffer descriptor rings for each endpoint, as illustrated in figure 16-114. the buffer descriptor ring allows you to define buffers for transmission and reception. each buffer descriptor ring forms a circular queue. the communication processor module confirms reception and transmission or indicates error conditions using the buffer descriptors to inform the processor that the buffers have been serviced. the actual buffers can reside in either external or internal memory. data buffers can reside in the parameter ram of a serial communication controller if it is not enabled.
communication processor module motorola mpc823e reference manual 16-375 usb communication 16 processor module figure 16-114. usb buffer descriptor ring frame status data length data pointer usb endpoint 1 dual- port ram external memory tx buffer descriptors tx data buffer rx data buffer ep0 rx bd table pointer ep0 tx bd table pointer frame status data length data pointer tx buffer descriptors tx data buffer endpoint 3 tx bd table endpoint 0 tx bd table endpoint 0 rx bd table endpoint 3 rx bd table ep3 rx bd table pointer ep3 tx bd table pointer frame status data length data pointer rx buffer descriptors frame status data length data pointer rx buffer descriptors rx data buffer
communication processor module 16-376 mpc823e reference manual motorola usb communication 16 processor module 16.10.8.8 usb event register. the 16-bit, memory-mapped usb event register (usber) is used to generate interrupt events and report events recognized by the usb channel. when an event is recognized, the usb sets the corresponding bit in the usber. interrupts generated by this register may be masked in the usb mask register. a bit is cleared by writing a one (writing a zero has no effect) and more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module will clear the internal interrupt request. bits 0C5reserved these bits are reserved and must be set to 0. resetreset condition detected this bit indicates that the usb reset condition has been asserted. idleidle status changed this bit indicates that a change in the status of the serial line was detected. the real time idle status is reflected in the usb status register. txextx error 0C3 this bit indicates that an error occurred during transmission for endpoint x (packet not acknowledged (function), nak/stall handshake received (host) or transmit underrun). sofstart of frame this bit indicates that a start-of-frame packet was received. the packet is stored in the frame_n parameter ram entry. bsybusy condition this bit indicates that received data has been discarded due to a lack of buffers. this bit is set after the first character with no receive buffer is received. txbtx buffer this bit indicates that a buffer has been transmitted. it is set once the transmit data of the last character in the buffer was written to the transmit fifo (the l bit in the tx buffer descriptor is set to 0) or after the last character was transmitted on the line ( l is set to 1). rxbrx buffer this bit indicates that a buffer has been received. it is set after the last character has been written to the receive buffer and the rx buffer descriptor is closed. usber bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset idle txe3 txe2 txe1 txe0 sof bsy txb rxb reset 0 0000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0 x ffff0000) + 0 x a10
communication processor module motorola mpc823e reference manual 16-377 usb communication 16 processor module 16.10.8.9 usb mask register. the 16-bit read/write usb mask register (usbmr) has the same bit formats as the usb event register. if a bit in the usbmr is one, the corresponding interrupt in the usber is enabled. if the bit is zero, the corresponding interrupt in the usber will be masked. 16.10.8.10 usb status register. the 8-bit read-only usb status (usbs) register allows you to monitor real-time status condition on the usb lines. bits 0C6reserved these bits are reserved and must be set to 0. idleidle status when set, this bit indicates that an idle condition has been detected on the usb lines. it is cleared when the bus is not idle. software has to set up a timer to detect the idle state that occurs after 3ms. usbmr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset idle txe3 txe2 txe1 txe0 sof bsy txb rxb reset 0 0000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0 x ffff0000) + 0 x a14 usbs bit 0 1 2 3 4 5 6 7 field reserved idle reset 00 r/w rr addr (immr & 0xffff0000) + 0xa17
communication processor module 16-378 mpc823e reference manual motorola usb communication 16 processor module 16.10.8.11 usb controller initialization example (function mode). the following is an example initialization sequence for the usb controller operating in function mode. it can be used to set up four function endpoints (0C3) that fill up transmit fifos, so that data is ready for transmission when an in token is received from the usb. you can generate the token by using a usb traffic generator. 1. write 0x00010000 to the brgc1 register for division factor 1 to produce 48mhz, assuming the system clock is 48mhz. 2. clear the dr14 and dr15 bits of the padir. set the dd14 and dd15 bits of the papar to select the usbrxd and usboe pins. 3. clear the dr10 and dr11 bits of the pcdir. set the dd10 and dd11 bits of the pcpar and the cd1 and cts1 bits of the pcso to select the usbrxp and usbrxn pins. 4. set the dr6 and dr7 bits of the pcdir and the dd6 and dd7 bits of the pcpar to select the usbtxp and usbtxn pins. 5. write 0x0000 to initialize the frame_n parameter. 6. write dpram+500 to the ep0ptr and dpram+520 to the ep1ptr to set up the endpoint 0 and 1 pointers. 7. write dpram+540 to the ep2ptr and dpram+560 to the ep3ptr to set up the endpoint 2 and 3 pointers. 8. write 0xbc800004 to dpram+20 to set up the various status and data length fields of the endpoint 0 tx buffer descriptor. 9. write dpram+200 to dpram+24 to set up the tx data buffer pointer field of the endpoint 0 tx buffer descriptor. 10. write bcc00004 to dpram +28 to set up the status and data length fields of the endpoint 1 tx buffer descriptor. 11. write dpram+210 to dpram+2c to set up the data buffer pointer field of the endpoint 1 tx buffer descriptor. 12. write bc80004 to dpram+30 to set up the status and data length fields of the endpoint 2 tx buffer descriptor. 13. write dpram +220 to dpram+34 to set up the data buffer pointer field of the endpoint 2 tx buffer descriptor. 14. write bcc00004 to dpram+30 to set up the status and data length fields of the endpoint 3 tx buffer descriptor. 15. write dpram+30 to dpram+3c to set up the data buffer pointer field of the endpoint 3 tx buffer descriptor. 16. write cafecafe to dpram+200 to set up the endpoint 0 tx data pattern. 17. write faceface to dpram+210 to set up the endpoint 1 tx data pattern. 18. write bacebace to dpram+220 to set up the endpoint 2 tx data pattern. 19. write cacecace to dpram+230 to set up the endpoint 3 tx data pattern.
communication processor module motorola mpc823e reference manual 16-379 usb communication 16 processor module 20. write 20002020 to dpram+500 to set up the rbase and tbase fields of the endpoint 0 parameter ram. 21. write 18180100 to dpram+504 to set up the rfcr, tfcr and mrblr fields of the endpoint 0 parameter ram. 22. write 20002020 to dpram+508 to set up the rbptr and tbptr fields of the endpoint 0 parameter ram. 23. clear the tstate field of the endpoint 0 parameter ram. 24. write 20082028 to dpram+520 to set up the rbase and tbase fields of the endpoint 1 parameter ram. 25. write 18180100 to dpram+524 to set up the rfcr, tfcr and mrblr fields of the endpoint 1 parameter ram. 26. write 20082028 to dpram+528 to set up the rbptr and tbptr fields of the endpoint 1 parameter ram. 27. clear the tstate field of the endpoint 1 parameter ram. 28. write 0x0200 to the usep0 for endpoint 0, bulk transfer, one packet only, and manual handshake. 29. write 0x1200 to the usep1 for endpoint 1, bulk transfer, one packet only, and manual handshake. 30. write 0x2200 to the usep2 for endpoint 2, bulk transfer, one packet only, and manual handshake. 31. write 0x3200 to the usep3 for endpoint 3, bulk transfer, one packet only, and manual handshake. 32. write 0x00 to the usmod for full-speed 12mps function endpoint mode and disable the usb. 33. write 0x05 to the usadr for slave address 5. 34. clear the uscom register. 35. set the en bit in the usmod register to enable the usb controller. 36. write 0x80 to the uscom to start filling the tx fifo with endpoint 0 data ready for transmission when in token is received. 37. write 0x81 to the uscom to start filling the tx fifo with endpoint 1 data ready for transmission when in token is received. 38. write 0x82 to the uscom to start filling the tx fifo with endpoint 2 data ready for transmission when in token is received. 39. write 0x83 to the uscom to start filling the tx fifo with endpoint 3 data ready for transmission when in token is received.
communication processor module 16-380 mpc823e reference manual motorola usb communication 16 processor module 16.10.9 using the usb controller as a host this section describes the full implementation of host mode, which is available for revision b (and later) of the mpc823e silicon. earlier revisions of the mpc823e only support high-speed (12mbs) host mode operation. to configure the usb controller as a host, the host bit in the usb mode register must be set. in this mode, the registers and memory structures associated with endpoint 0 are used to control host transmission and reception. the other endpoints are typically unused, except for testing purposes (loop-back). the programming model for the host controller is similar to the one used in function mode. you must set the mf bit in the endpoint 0 configuration register to allow setup/out tokens and data0/data1 packets to be transmitted back-to-back. the tokens must be prepared in a separate buffer descriptor. the software must append the crc5 as part of the transmitted data because the cpm currently does not support it. the usb host controller must be clocked as a high-speed function (48mhz reference clock). the lsp bit in the transmit buffer descriptor indicates whether or not the following transaction is with a low-speed function. if it is set, the usb controller will automatically generate the pre token before each transmitted packet and change the transmit rate to low speed. after the transaction is completed, the host returns to full-speed operation. the lsp bit must be set only for buffer descriptors associated with tokens. 16.10.9.1 usb controller initialization example (host mode). the following is an local loopback example initialization sequence for the usb controller operating in host mode. it can be used to set up endpoints 0 and 1 to fill up transmit fifos to demonstrate an in token transaction. 1. write 0x00010000 to the brgc1 register for division factor 1 to produce 48mhz, assuming the system clock is 48mhz. 2. clear the dr14 and dr15 bits of the padir. set the dd14 and dd15 bits of the papar to select the usbrxd and usboe pins. 3. clear the dr10 and dr11 bits of the pcdir, the dd10 and dd11 bits of the pcpar, and set the cd1 and cts1 bits of the pcso to select the usbrxp and usbrxn pins. 4. set the dr6 and dr7 bits of the pcdir and the dd6 and dd7 bits of the pcpar to select the usbtxp and usbtxn pins. 5. write 0x0000 to initialize the frame_n parameter. 6. write dpram+500 to the ep0ptr and dpram+520 to the ep1ptr to set up the endpoint 0 and 1 pointers. 7. write 0xb8000003 to dpram+20 to set up the various status and data length fields of the endpoint 0 tx buffer descriptor. 8. write dpram+200 to dpram+24 to set up the tx data buffer pointer field of the endpoint 0 tx buffer descriptor. 9. write bc800003 to dpram +28 to set up the status and data length fields of the endpoint 1 tx buffer descriptor.
communication processor module motorola mpc823e reference manual 16-381 usb communication 16 processor module 10. write dpram+210 to dpram+2c to set up the tx data buffer pointer field of the endpoint 1 tx buffer descriptor. 11. write 0x698560 to dpram+200 to set up the endpoint 0 tx data pattern. this pattern consists of the in token and the crc5. 12. write abcd1234 to dpram+210 to set up the endpoint 1 tx data pattern. 13. write 20002020 to dpram+500 to set up the rbase and tbase fields of the endpoint 0 parameter ram. 14. write 18180100 to dpram+504 to set up the rfcr, tfcr, and mrblr fields of the endpoint 0 parameter ram. 15. write 20002020 to dpram+508 to set up the rbptr and tbptr fields of the endpoint 0 parameter ram. 16. clear the tstate field of the endpoint 0 parameter ram. 17. write 20082028 to dpram+520 to set up the rbase and tbase fields of the endpoint 1 parameter ram. 18. write 18180100 to dpram+524 to set up the rfcr, tfcr, and mrblr fields of the endpoint 1 parameter ram. 19. write 20082028 to dpram+528 to set up the rbptr and tbptr fields of the endpoint 1 parameter ram. 20. clear the tstate field of the endpoint 1 parameter ram. 21. write 0x0000 to the usep0 for endpoint 0, control transfer, one packet only. 22. write 0x1100 to the usep1 for endpoint 1, control transfer, one packet only. 23. write 0x2200 to the usep2 for endpoint 2, bulk transfer, one packet only. 24. write 0x3300 to the usep3 for endpoint 3, isochronous transfer, one packet only. 25. write 0x06 to the usmod for full-speed 12mps signaling, local loopback configuration (test and host modes set), and disable the usb. 26. write 0x05 to the usad for slave address 5. 27. clear the uscom register. 28. set the en bit in the usmod register to enable the usb controller. 29. write 0x80 to the uscom to start filling the tx fifo with endpoint 0 data ready for transmission when in token is received. 30. write 0x81 to the uscom to start filling the tx fifo with endpoint 1 data ready for transmission when in token is received.
communication processor module 16-382 mpc823e reference manual motorola smc communication 16 processor module the expected results are as follows: ? the tx buffer descriptor (ep0) control/status field must contain 0x3800. ? the tx buffer descriptor (ep0) data length field must contain 0x0003. ? the tx buffer descriptor (ep1) control/status field must contain 0x3c80. ? the tx buffer descriptor (ep1) data length field must contain 0x0003. ? the rx buffer descriptor (ep0) control/status field must contain 0x3c00. ? the rx buffer descriptor (ep0) data length field must contain 0x0005. ? the rx buffer descriptor (ep0) data buffer field must contain 0xabcd122b, 0x42xxxxxx. 16.11 the serial management controllers the serial management controllers (smcs) consist of two full-duplex ports that can be independently configured to support any one of three protocols or modesuart, transparent, or general-circuit interface (gci). simple uart operation is used to provide a debug/monitor port in an application, which allows a serial communication controller (sccx) to be free for other purposes. the serial management controller clock can be derived from one of the four internal baud rate generators or from a 16 external clock pin. the functionality and performance provided by the smcx in uart mode is generally less than that provided by an sccx in uart mode. the smcx implementation does not support such features as special character recognition and detection. in totally transparent mode, a serial management controller can use a tdm channel to connect to a t1 line or directly to the smcs set of pins. however, smc2 does not have its own set of dedicated pins, so the time-slot assigner pins are its only option. the receive and transmit clocks are derived from the time-division multiplex (tdm) channels, the internal baud rate generators, or from an external 1 clock. the transparent protocol allows the transmitter and receiver to use the external synchronization pin.
communication processor module motorola mpc823e reference manual 16-383 smc communication 16 processor module each serial management controller supports the circuit interface and monitor channels of the gci bus. in which case, the serial management controller is connected to a tdm channel in the serial interface. for testing purposes, the serial management controllers support loopback and echo modes. the smcx receiver and transmitter are double-buffered, which provides an effective fifo size (latency) of two characters. refer to section 16.7 the serial interface with time-slot assigner for details about configuring the gci interfaces. the receive data source for the two serial management controller channels have different pin options for each channel. smc1 can either use the l1rxdx pin of the serial interface or the smrxd1 pin if it is connected to the nmsi. smc2 can also use the l1rxdx pin of the serial interface, but if you use the smrxd2 pin the serial interface time-slot assigner function is not available. likewise, the transmit data source for smc1 can be the l1txdx pin if a serial management controller is connected to a tdm or the smtxd1 pin if it is connected to the nmsi. smc2 transmit data source can also be l1txdx pin if the serial management controller is connected to a tdm, but if you use the smtxd2 pin, the serial interface time-slot assigner function is not available. if the serial management controllers are connected to a tdm, the smcx receive and transmit clocks can be independent from each other, as defined in the crtx bit of the simode register. refer to section 16.7.5.2 serial interface mode register for more information. however, if a serial management controller is connected to the nmsi, the smcx receive and transmit clocks must be connected to a single clock source called smclk, which is an internal signal name for a clock that is generated from the bank of clocks. smclk originates from an external pin or one of the two internal baud rate generators. refer to section 16.7.8 nonmultiplexed serial interface configuration for more details. figure 16-115. serial management controller block diagram control registers u-bus rx data register tx data register shifter shifter control logic peripheral bus txdx rxdx sync clock
communication processor module 16-384 mpc823e reference manual motorola smc communication 16 processor module if the serial management controllers are connected to a tdm, it gets its synchronization pulse from the time-slot assigner. otherwise, if a serial management controller is connected to the nmsi and the transparent protocol is selected, the serial management controller can use the smsynx pin as a synchronization pin to determine when it must start transmitting and receiving. the smsynx pin is not used, however, when a serial communication controller is in uart mode. 16.11.1 features the following is a list of the serial management controllers main features: ? each serial management controller can implement the uart protocol on its own pins ? each serial management controller can implement a totally transparent protocol on a multiplexed or nonmultiplexed line. if smc2 uses a nonmultiplexed line, a serial interface time-slot assigner is not available. ? each smcx channel fully supports the circuit interface and monitor channels of the gci (iom-2) in isdn applications ? two serial management controllers support the two sets of circuit interface and monitor channels in the scit channels 0 and 1 ? full-duplex operation ? local loopback and echo capability for testing 16.11.2 general smcx mode register the operating mode of each serial management controller port is defined by the 16-bit, memory-mapped, read/write general smcx mode register (smcmr). refer to each specific smcx protocol section for information about this register and table 16-2 (page 16-11) for specific commands. 16.11.3 smcx buffer descriptor operation when the serial management controllers are configured to operate in gci mode, their memory structure is predefined as one half-word long for transmit and one half-word long for receive. for more information on these half-word structures, refer to section 16.11.8 the smcx in gci mode .
communication processor module motorola mpc823e reference manual 16-385 smc communication 16 processor module in uart and transparent modes, the serial management controllers have a memory structure that is similar to the serial communication controllers. each buffer is referenced by a buffer descriptor and organized in a buffer descriptor ring located in the dual-port ram, as illustrated in figure 16-116. the buffer descriptor ring allows you to define buffers for transmission and reception and each ring forms a circular queue. using the buffer descriptors, the communication processor module confirms reception and transmission so that the microprocessor knows the buffers have been serviced. the data buffers can reside in external or internal memory and the data buffers reside in the parameter area of an sccx or smcx if that channel is not enabled. 16.11.4 smc general parameter ram memory map each smcx parameter ram area begins at the same offset from each base. the protocol-specific portions of the smcx parameter ram are discussed in each mode. the smcx general parameter ram shared by the uart and transparent protocols is described in table 16-36. the gci protocol has its own parameter ram. you must initialize certain parameter ram values before a serial management controller is enabled. other values are initialized or written by the communication processor module. once initialized, most parameter ram values do not need to be accessed in your software since most of the activity is centered around the transmit and receive buffer descriptors and not the parameter ram. however, if you access the parameter ram, note the following restrictions. figure 16-116. smcx memory format frame status data pointer frame status data length data pointer pointer to smcx tx bd ring rx data buffer dual- port ram external memory tx bd ring rx bd ring tx data buffer pointer to smcx rx bd ring smcx tx bd ring smcx rx bd ring data length
communication processor module 16-386 mpc823e reference manual motorola smc communication 16 processor module ? the parameter ram values that pertain to the smcx transmitter can only be written when the ten bit in the smcmr is zero or after the stop transmit command is issued, but before the restart transmit command is issued. ? the parameter ram values that pertain to the smcx receiver can only be written when: o the ren bit in the smcmr is zero. o the receiver is previously enabled after the enter hunt mode command is issued. o the close rx bd command is issued before the ren bit is set. table 16-36. smcx (uart and transparent) parameter ram memory map address name width description smcx base + 00 rbase half-word rx buffer descriptor base address smcx base + 02 tbase half-word tx buffer descriptor base address smcx base + 04 rfcr byte rx function code smcx base + 05 tfcr byte tx function code smcx base + 06 mrblr half-word maximum receive buffer length smcx base + 08 rstate word rx internal state smcx base + 0c rptr word rx internal data pointer smcx base + 10 rbptr half-word rx buffer descriptor pointer smcx base + 12 rcnt half-word rx internal byte count smcx base + 14 rtmp word rx temp smcx base + 18 tstate word tx internal state smcx base + 1c tptr word tx internal data pointer smcx base + 20 tbptr half-word tx buffer descriptor pointer smcx base + 22 tcnt half-word tx internal byte count smcx base + 24 ttmp word tx temp smcx base + 28 first word of protocol-specific area smcx base + 36 last word of protocol-specific area note: you are only responsible for initializing the items in bold. smcx base = (immr & 0xffff0000) + 0x3e80 (smc1) and 0x3f80 (smc2).
communication processor module motorola mpc823e reference manual 16-387 smc communication 16 processor module ? rbase and tbasethese entries are used by the dual-port ram starts the smcx receive and transmit buffer descriptors. they provide a great deal of flexibility for partitioning the buffer descriptors for a serial management controller. by selecting rbase and tbase entries for a serial management controller and by setting the w bit in the last buffer descriptor in each buffer descriptor list, you can select the number of buffer descriptors to allocate for the transmit and receive side of the serial management controller. however, you must initialize these entries before enabling the corresponding channel. furthermore, you must not configure buffer descriptor tables of two enabled serial management controllers to overlap or erratic operation will occur. ? rfcr and tfcrthere are separate function code registers for the two smcx channels. one for receive data buffers (rfcr) and one for transmit data buffers (tfcr). the function code entry contains the value that you want to appear on the at pins when the associated sdma channel accesses memory. it also controls the byte-ordering convention that is used in the transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering set these bits to select the required byte ordering of the data buffer. if this field is modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. note: rbase and tbase must contain a value that is divisible by eight. rfcr bit 0 1 2 3 4 5 6 7 field reserved bo at1-at3 reset 000 r/w r/w r/w r/w addr smc1 and smc2 base + 0x04
communication processor module 16-388 mpc823e reference manual motorola smc communication 16 processor module 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type 1C3 these bits contain the function code value used during the sdma channel memory access. the at0 pin is driven with a 1 to identify this sdma channel access as a dma type. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering set these bits to select the required byte ordering of the data buffer. if this field is modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. tfcr bit 0 1 2 3 4 5 6 7 field reserved bo at1Cat3 reset 000 r/w r/w r/w r/w addr smc1 and smc2 base + 0x05
communication processor module motorola mpc823e reference manual 16-389 smc communication 16 processor module ataddress type 1C3 these bits contain the function code value used during this sdma channel memory access. the at0 pin is driven with a 1 to identify this sdma channel access as a dma type. ? mrblreach serial management controller has one maximum receive buffer length register that defines the length of the receive buffer. the mrblr defines the maximum number of bytes that the mpc823e writes to a receive buffer on a serial management controller before it moves on to the next buffer. the mpc823e can write fewer bytes to the buffer than mrblr if a condition, such as an error or end-of-frame occurs, but it never writes more bytes than the mrblr value. it follows then, that the buffers you supply must always be at least as long as the mrblr. the transmit buffers for a serial management controller are not affected in any way by the value programmed into the mrblr. each transmit buffer can have a different length. you can choose the number of bytes to be transmitted by programming the data length field in the tx buffer descriptor. ? rbptrthe receiver buffer descriptor pointer for each smcx channel points to the next buffer descriptor the receiver transfers data to when it is idle or to the current buffer descriptor during frame processing. after a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the rbase entry. although you will not usually need to write the rbptr in most applications, you can modify it when the receiver is disabled or when you are sure no receive buffer is currently being used. ? tbptrthe transmitter buffer descriptor pointer for each smcx channel points to the next buffer descriptor the transmitter transfers data from when it is idle or to the current buffer descriptor during frame transmission. after a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the tbase register. although you will not usually need to write tbptr in most applications, you can modify it when the receiver is disabled or when you are sure no receive buffer is currently being used. note: the mrblr is not intended to be dynamically changed while a serial management controller is operating. however, if it is modified in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back), then a dynamic change in the receive buffer length can be successfully achieved. this occurs when the communication processor module transfers control to the next rx buffer descriptor in the table. thus, a change to mrblr does not have an immediate effect. to guarantee that the change occurs on a particular rx buffer descriptor, you must only change the mrblr while the smcx receiver is disabled. the value of mrblr must be greater than zero and it must be even if the character length of the data is greater than 8 bits.
communication processor module 16-390 mpc823e reference manual motorola smc communication 16 processor module ? other general parametersyou do not need to access these parameters during normal operation. they are only listed because they provide helpful debugging information. additional parameters are listed in table 16-33 (page 16-357). the rx and tx internal data pointers are updated by the sdma channels to show the next address in the buffer to be accessed. tcnt is a down-count value that is initialized with the data length field of the tx buffer descriptor and decremented with every byte read by the sdma channels. rcnt is a down-count value that is initialized with the mrblr value and decremented with every byte written by the sdma channels. rstate, tstate, rtemp, ttemp, and the reserved areas are only used by the risc microcontroller. 16.11.5 disabling the smcs on-the-fly if you do not need a serial management controller, it can be disabled and reenabled later. in which case, you must follow a particular sequence of steps to ensure that the buffers are properly closed and that new data is transferred to or from a new buffer. this sequence is required if the parameters you want to change are not dynamic. if the register or bit description states that dynamic or on-the-fly changes are allowed, you do not have to follow the sequence and the register or bit can can be changed immediately. note: to extract data from a partially full receive buffer, use the close rx bd command. note: a serial management controller does not have to be fully disabled for you to modify the parameter ram. refer to the parameter ram description for details about modifying the parameter ram values. if you want to disable the sccs, usb, smcs, spi, and i 2 c, use the cpm command register (described in section 16.2.6.1 cpm command register ) to reset the communication processor module with a single command.
communication processor module motorola mpc823e reference manual 16-391 smc communication 16 processor module 16.11.5.1 disabling the entire smcx transmitter. follow these steps to fully enable or disable the smcx transmitter: 1. issue the stop transmit command. this command is recommended when a serial management controller is transmitting data since it stops transmission smoothly. this command is not required if a serial management controller is not transmitting, if you overwrite the tbptr or if you execute the init tx parameters command. 2. clear the ten bit in the smcmr. this disables the smcx transmitter and puts it in a reset state. 3. modify the smcx transmit parameters, including the parameter ram. if you prefer to switch protocols or restore the smcx transmit parameters to their initial state, issue the init tx parameters command. 4. issue the restart transmit command. you must do this if you did not issue the init tx parameters command in step 3. 5. set the ten bit in the smcmr. when the r bit is set in the tx buffer descriptor, transmission begins using the tx buffer descriptor indicated by the tbptr value. 16.11.5.2 disabling part of the smcx transmitter. follow this shorter sequence if you prefer to reinitialize the transmit parameters to the state they were in after reset. 1. clear the ten bit in the smcmr. 2. issue the init tx parameters command and make any additional modifications. 3. set the ten bit in the smcmr. 16.11.5.3 disabling the entire smcx receiver. follow these steps to fully enable or disable the receiver: 1. clear the ren bit in the smcmr. reception is aborted immediately, which disables the smcx receiver and puts it in a reset state. 2. modify the smcx receive parameters, including the parameter ram. if you prefer to switch protocols or restore the smcx receive parameters to their initial state, issue the init rx parameters command. 3. issue the close rx bd command. you must do this if you did not issue the init rx parameters command in step 2. 4. set the ren bit in the smcmr. when the e bit is set in the rx buffer descriptor, reception begins immediately using the rx buffer descriptor indicated by the rbptr.
communication processor module 16-392 mpc823e reference manual motorola smc communication 16 processor module 16.11.5.4 disabling part of the smcx receiver. follow this shorter sequence to reinitialize the receive parameters to the state they were in after reset. 1. clear the ren bit in the smcmr. 2. init rx parameters command and make any additional modifications. 3. set the ren bit in the smcmr. 16.11.5.5 switching protocols. to switch a protocol that is being executed by a serial management controller without resetting the board or affecting any other serial management controller: 1. clear the ten and ren bits in the smcmr. 2. issue the init tx and rx params command to initialize the transmit and receive parameters. make any additional modifications in the smcmr. 3. set the ten and ren bits in the smcmr. the serial management controller is now enabled with the new protocol. 16.11.6 the smcx in uart mode compared to an sccx in uart mode, the serial management controllers are designed to support simple debug/monitor ports instead of full-featured uart controllers. the following is a list of the features that the smcx in uart mode does not support. ? rtsx , ctsx , and cdx pins ? receive and transmit sections clocked at different rates ? fractional stop bits ? built-in multidrop modes ? freeze mode for implementing flow control ? isochronous operation (1 clock ) ? interrupts on special control character reception ? ability to transmit data on demand using the transmit on demand register tip: you can save power by clearing the ten and ren bits of a serial management controller.
communication processor module motorola mpc823e reference manual 16-393 smc communication 16 processor module a serial management controller in uart mode has one feature that an sccx in uart mode does not. data length on an smcx can be a maximum of 14 bits, whereas, a serial communication controller only allows 8 bits. a serial management controller in uart mode is also referred to as a smcx uart controller. 16.11.6.1 features. the following list summarizes the main features of the smcx in uart mode: ? flexible message-oriented data structure ? programmable data length (5C14 bits) ? programmable 1 or 2 stop bits ? even/odd/no parity generation and checking ? frame error, break, and idle detection ? transmit preamble and break sequences ? received break character length indication ? continuous receive and transmit modes 16.11.6.2 smcx uart channel transmission process. the uart transmitter is designed to work with almost no intervention from the core. when the core enables the smcx transmitter, it starts transmitting idles. the smcx uart controller immediately polls the first buffer descriptor in the transmit channel buffer descriptor ring and once every character time after that, depending on the character length. when there is a message to transmit, the smcx uart controller fetches the data from memory and starts transmitting the message. figure 16-117. smcx uart frame format smtxd smclk 16 start bit 5 to 14 data bits with the least-significant bit first par. bit optional 1 or 2 stop bits ( clock not to scale )
communication processor module 16-394 mpc823e reference manual motorola smc communication 16 processor module when the buffer descriptor data is completely written to the transmit fifo, the smcx uart controller writes the message status bits into the buffer descriptor and clears the r bit. an interrupt is issued if the i bit in the buffer descriptor is set. if the next tx buffer descriptor is ready, the data from its data buffer is appended to the previous data and transmitted out on the transmit pin, without any gaps between the buffers. if the next tx buffer descriptor is not ready, the smcx uart controller starts transmitting idles and waits for the next tx buffer descriptor to be ready. by appropriately setting the i bit in each buffer descriptor, interrupts can be generated after the transmission of each buffer, a specific buffer, or each block. the smcx uart controller then proceeds to the next buffer descriptor in the table. if the cm bit is set in the tx buffer descriptor, the r bit is not cleared, allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this data buffer. for instance, if a single tx buffer descriptor is initialized with the cm and w bits set, the data buffer is continuously transmitted until you clear the r bit of the buffer descriptor. 16.11.6.3 smcx uart channel reception process. when the core enables the smcx receiver in uart mode, it enters hunt mode and waits for the first character to arrive. once the first character arrives, the communication processor module checks the first receive buffer descriptor to see if it is empty and then starts storing characters in the associated data buffer. when the data buffer is filled or the max_idl timer expires (if it is enabled) the smcx uart controller clears the e bit in the buffer descriptor and generates an interrupt if the i bit in the buffer descriptor is set. if the incoming data exceeds the length of the data buffer, the smcx uart controller fetches the next buffer descriptor in the table and, if it is empty, continues transferring data to the associated data buffer. if the cm bit is set in the receive buffer descriptor, the e bit is not cleared, which allows the associated data buffer to be automatically overwritten next time the communication processor module accesses this data buffer. 16.11.6.4 smcx uart parameter ram memory map. when a serial management controller is configured to operate in uart mode, the smcx uart controller overlays the structure used in table 16-36 with the parameters described in table 16-37. table 16-37. smcx uart parameter ram memory map address name width description smcx base + 28 max_idl half-word maximum idle characters smcx base + 2a idlc half-word temporary idle counter smcx base + 2c brkln half-word last received break length smcx base + 2e brkec half-word receive break condition counter smcx base +30 brkcr half-word break count register (transmit) smcx base +32 r_mask half-word temporary bit mask note: you are only responsible for initializing the items in bold. smcx base = (immr & 0xffff0000) + 0x3e80 (smc1) and 0x3f80 (smc2).
communication processor module motorola mpc823e reference manual 16-395 smc communication 16 processor module ? max_idlonce a character of data is received on the line, the smcx uart controller starts counting any idle characters received. if a max_idl number of idle characters is received before the next data character, an idle timeout occurs and the buffer closes. this, in turn, produces an interrupt request to the core to receive the data from the buffer. max_idl provides a convenient way to demarcate frames in smcx uart mode. but if you do not want to use max_idl, you must program max_idl to 0x0000 and the buffer will never close, regardless of the number of idle characters received. the number of bits in an idle character is calculated as follows1 + character data length (5 to 14) + 1 (if parity bit is used) + number of stop bits (1 or 2). for example, for a character data length of 8, no parity, and 1 stop bit, the idle character length is 10 bits. ? idlcthis value is used by the risc microcontroller to store the current idle counter value in the max_idl timeout process. idlc is a down-counter that you do not need to initialize or access. ? brklnthis value is used to store the length of the last break character received and is the bit length of that character. for example, if the receive pin is low for 257 bit times, brkln shows the value 0x0101 and its accuracy comes within one character unit of bits. for 8 data bits, no parity, 1 stop bit, and 1 start bit, brkln is accurate within 10 bits. ? brkecthis counter counts the number of break conditions that occur on the line. one break condition can last for hundreds of bit times, yet this counter is only incremented once during that period. ? brkcrthis value indicates when the smcx uart controller sends a break character sequence after a stop transmit command is issued. the number of break characters sent by the smcx uart controller is determined by the value in brkcr. for 8 data bits, no parity, 1 stop bit, and 1 start bit, each break character is 10 bits long and consists of all zeros. ? r_maskthis value is a temporary bit mask used internally by the smcx uart controller. 16.11.6.5 programming the smcx uart controller. the smcx uart controllers data structure supports multibuffer operation and allows you to transmit break and preamble sequences. overrun, parity, and framing errors are reported via the buffer descriptors. in its simplest form, the smcx uart controller functions in a character-oriented environment. each character is transmitted with the stop bits and parity that you configure. characters are received into separate 1-byte buffers. a maskable interrupt can be generated when each buffer is filled. many applications may want to take advantage of the message-oriented capabilities that the smcx uart controller supports through linked buffers for reception or transmission. you can handle data in a message-oriented environment and work on entire messages rather than on a character-by-character basis. a message can span several linked buffers and each one can be transmitted and received as a linked list of buffers without any intervention from the core, which makes it easy to program and saves processor overhead. in a message-oriented environment, the idle sequence is used as the message delimiter. the transmitter can generate an idle sequence before starting a new message and the receiver can close a buffer when an idle sequence is found.
communication processor module 16-396 mpc823e reference manual motorola smc communication 16 processor module 16.11.6.6 smcx uart commands. you can program the cpm command register (cpcr) with the following commands to transmit data. ? stop transmit this command disables the transmission of characters on the transmit channel. if the smcx uart controller receives this command while transmitting a message, it stops transmitting. the smcx uart controller finishes transmitting any data that has already been transferred to its fifo and shift register and then stops transmitting data. the tbptr is not advanced when this command is issued. the smcx uart controller transmits a programmable number of break sequences and then transmits idles. the number of break sequences, which can be zero, must be written to the brkcr entry before this command is issued to the smcx uart controller. ? restart transmit this command enables characters to be transmitted on the transmit channel. the smcx uart controller expects it after disabling the channel in its smcmr and after issuing the stop transmit command. the smcx uart controller resumes transmission from the current tbptr in the channels transmit buffer descriptor table. ? init tx parameters this command initializes all the transmit parameters in this serial channels parameter ram to their reset state and must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. you can program the cpcr with the following commands to receive data. ? enter hunt mode this command cannot be used for an smcx uart channel. issue the close rx bd command instead. ? close rx bd this command is used to force a serial management controller to close the current receive buffer descriptor if it is currently being used and to use the next buffer descriptor in the list for any subsequently received data. if a serial management controller is not in the process of receiving data, no action is taken by this command. ? init rx parameters this command initializes all the receive parameters in this serial channel parameter ram to their reset state. this command must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters. 16.11.6.7 sending a break. a break is an all-zeros character without stop bits and it is sent by issuing the stop transmit command. the smcx uart controller finishes transmitting any outstanding data and then sends a character with consecutive zeros. the number of zero bits in this character is the sum of the character length, plus the number of start, parity, and stop bits. the smcx uart controller transmits a programmable number of break characters according to the brkcr entry and then reverts to idle or sends data if the restart transmit command was issued before completion. when the break is completed, the transmitter sends at least one idle character before transmitting any data to guarantee recognition of a valid start bit.
communication processor module motorola mpc823e reference manual 16-397 smc communication 16 processor module 16.11.6.8 sending a preamble. a preamble sequence provides a convenient way for you to ensure that the line is idle before you start a new message. the preamble sequence is constructed of consecutive ones that are one character long. if the preamble bit in a buffer descriptor is set, a serial management controller sends a preamble sequence before transmitting that data buffer. for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones would be sent before the first character in the buffer. if no preamble sequence is sent, data from two ready transmit buffers can be transmitted without causing a delay on the transmit pin between the two transmit buffers. 16.11.6.9 smcx uart controller errors. the smcx uart controller reports character reception error conditions via the channel buffer descriptors and the smcx uart event register. the smcx uart controller has no transmission errors, which means you cannot stop the transmission of characters in smcx uart mode. ? overrun error the smcx uart controller maintains a two-character length fifo for receiving data. the data is moved to the buffer after the first character is received into the fifo and if a receiver fifo overrun occurs, the channel writes the received character into the internal fifo. then the channel writes the received character to the buffer, closes it, sets the ov bit in the receive buffer descriptor, and generates a receive interrupt if it is enabled. reception then continues as normal. ? parity error when this error occurs, the channel writes the received character to the buffer, closes it, sets the pr bit in the buffer descriptor, and generates the receive interrupt if it is enabled. reception then continues as normal. ? idle sequence receive erroran idle is detected when one character consisting of all ones is received. once an idle is received, the channel counts the number of consecutive idle characters. if the count reaches the max_idl value, the buffer is closed, and an receive interrupt is generated. if no receive buffer is open, this event does not generate an interrupt or any status information. the idle counter is reset every time a character is received. ? framing error the smcx uart controller receives this error when it receives a character with no stop bit. when this error occurs, the channel writes the received character to the buffer, closes the buffer, sets the fr bit in the buffer descriptor, and generates the receive interrupt if it is enabled. when this error occurs, parity is not checked for the character. ? break sequence errorthis error occurs when the smcx uart receiver receives an all-zero character with a framing error. when it occurs, the channel increments the brkec entry and generates a maskable brk interrupt in the smceCuart register. the channel also measures the length of the break sequence and stores this value in the brkln counter. if the channel was in the middle of buffer processing when the break was received, the buffer is closed with the br bit in the receive buffer descriptor set and the receive interrupt is generated if it is enabled. note: the smcx uart controller may occasionally get an overrun error when the line is idle, in which case, ignore the error.
communication processor module 16-398 mpc823e reference manual motorola smc communication 16 processor module 16.11.6.10 smcx uart mode register. when a serial management controller is in uart mode, the 16-bit, memory-mapped, read/write smcx mode register is referred to as the smcx uart mode register (smcmrCuart). the functionality of bits 8-15 is common to each smcx protocol, but bits 0-7 vary according to the protocol selected by the sm field. this register is cleared by reset. bits 0 and 8C9reserved these bits are reserved and must be set to 0. clencharacter length this field must be programmed with the total number of bits in the character minus one. the total number of bits in the character is calculated as the sum of 1 (start bit always present) + number of data bits (5 to 14) + number of parity bits (0 or 1) + number of stop bits (1 or 2). for example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the character is 1 + 8 + 0 + 1 = 10. in this case, clen must be programmed to 9. the number of data bits in the character ranges from 5 to 14 bits. if the data bit length is less than 8 bits, the most-significant bits of each byte in memory are not used on transmission and are written with zeros on reception. on the other hand, if the data bit length is more than 8 bits, the most-significant bits of each 16-bit word in memory are not used on transmit and are written with zeros on receive. slstop length 0 = one stop bit. 1 = two stop bits. penparity enable 0 = no parity. 1 = parity is enabled for the transmitter and receiver, depending on the pm bit setting. smcmrCuart bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res clen sl pen pm res sm dm ten ren reset 0 0 000 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa82 (smc1), 0xa92 (smc2) note: the total number of bits in the character must never exceed 16. thus, if you choose a 14-bit data length, set sl to one stop bit and disable parity. if you choose a 13-bit data length and parity is enabled, set sl to one stop bit. to prevent erratic behavior, do not write the values 0-3 to clen.
communication processor module motorola mpc823e reference manual 16-399 smc communication 16 processor module pmparity mode 0 = odd parity. 1 = even parity. smsmcx mode 00 = gci or scit support. 01 = reserved. 10 = uart mode (must be selected for smcx uart operation). 11 = totally transparent mode. dmdiagnostic mode 00 = normal mode. 01 = local loopback mode. 10 = echo mode. 11 = reserved. tensmcx transmit enable 0 = smcx transmitter disabled. 1 = smcx transmitter enabled. rensmcx receive enable 0 = smcx receiver disabled. 1 = smcx receiver enabled. 16.11.6.11 smcx uart receive buffer descriptor. using the buffer descriptors, the communication processor module reports information about the received data on a per-buffer basis. it then closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer when one of the following events occurs: ? an error is received while a message is being processed. ? a full receive (rx) buffer is detected. ? a programmable number of consecutive idle characters are received. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi reserved cm id reserved br fr pr res ov res offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module 16-400 mpc823e reference manual motorola smc communication 16 processor module eempty 0 = the data buffer associated with this rx buffer descriptor is filled with received data or data reception is aborted due to an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or reception is currently in progress. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 4C5, 8C9, 13, and 15reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is filled. 1 = the rx bit in the event register is set when this buffer is completely filled by the communication processor module, indicating the need for the core to process the buffer. the rx bit can cause an interrupt if it is enabled. cmcontinuous mode 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this buffer descriptor. however, the e bit is cleared if an error occurs during reception, regardless of how the cm bit is set. idbuffer closed on reception of idles this bit indicates that the buffer has closed because a programmable number of consecutive idle sequences have been received. the communication processor module writes this bit after the received data is in the associated data buffer. brbuffer closed on reception of break this bit indicates that the buffer has closed because a break sequence has been received. the communication processor module writes this bit after the received data is in the associated data buffer. 0 = no break sequence is received. 1 = a break sequence is received and the buffer closes.
communication processor module motorola mpc823e reference manual 16-401 smc communication 16 processor module frframing error this bit indicates that a character with a framing error has been received and is located in the last byte of this buffer. a framing error is a character without a stop bit. a new receive buffer is used to receive additional data. the communication processor module writes this bit after the received data is in the associated data buffer. prparity error this bit indicates that a character with a parity error has been received and is located in the last byte of this buffer. a new receive buffer is used to receive additional data. the communication processor module writes this bit after the received data is in the associated data buffer. ovoverrun this bit indicates that a receiver overrun has occurred during message reception. the communication processor module writes this bit after the received data is in the associated data buffer. data length this field represents the number of octets the communication processor module writes into this buffer descriptor data buffer. after the data is received in the associated data buffer, the communication processor module writes this field once the buffer descriptor closes. rx data buffer pointer this field always points to the first location of the associated data buffer and must be even. the buffer can reside in internal or external memory. the communication processor module writes this bit after the received data is in the associated data buffer. note: the actual amount of memory allocated for this buffer must be greater than or equal to the mrblr entry.
communication processor module 16-402 mpc823e reference manual motorola smc communication 16 processor module figure 16-118 illustrates an example of the rx buffer descriptor process. it shows the resulting state of the rx buffer descriptors after they receive 10 characters, an idle period, and five characters (one with a framing error). the example assumes that mrblr = 8 in the smcx parameter ram. figure 16-118. smcx uart receive buffer descriptor example mrblr = 8 bytes for this smc buffer byte 1 byte 2 byte 8 etc. 8 bytes long idle period fourth character has framing error! 5 chars 10 chars characters received by uart time buffer byte 9 byte 10 8 bytes buffer byte 1 byte 2 8 bytes byte 4 has framing error buffer full byte 3 byte 4 error! e length 32-bit buffer pointer receive bd 0 status 0008 pointer 0 e length 32-bit buffer pointer receive bd 1 status 0002 pointer 0 1 id 0 id e length 32-bit buffer pointer receive bd 2 status 0004 pointer 0 id 0 fr 1 e length 32-bit buffer pointer receive bd 3 status xxxx pointer 1 buffer byte 5 8 bytes reception still in progress with this buffer present time idle timeout occurred empty empty additional bytes will be stored unless idle count expires (max_idl)
communication processor module motorola mpc823e reference manual 16-403 smc communication 16 processor module 16.11.6.12 smcx uart transmit buffer descriptor. data is sent to the communication processor module for transmission on an smcx channel by arranging it in buffers referenced by the channels transmit (tx) buffer descriptor ring. using the buffer descriptors, the communication processor module confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission, but you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer has been transmitted or an error condition is encountered. 1 = the data buffer, which you prepare for transmission, is not transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1, 4C5, and 8C15reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the tx bit in the smceCuart register is set when this buffer is serviced. transmission can cause an interrupt if it is enabled. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi reserved cm p reserved offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-404 mpc823e reference manual motorola smc communication 16 processor module cmcontinuous mode 0 = normal operation. 1 = the r bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor. ppreamble 0 = no preamble sequence is sent. 1 = the smcx uart controller sends one all-ones character before it sends the data so that the other end detects an idle line before the data is received. if this bit is set and the data length of this buffer descriptor is zero, only a preamble is sent. data length this field represents the number of octets that the communication processor module must transmit from this buffer descriptor data buffer. however, it is never modified by the communication processor module. normally, this value must be greater than zero, but it can be equal to zero with the p bit set if only a preamble is sent. if the number of data bits in the smcx uart character is greater than 8, then the data length must be even. for example, to transmit three uart characters of 8-bit data, 1 start, and 1 stop, the data length field must be initialized to 3. however, to transmit three smcx uart characters of 9-bit data, 1 start, and 1 stop, the data length field must be initialized to 6, since the three 9-bit data fields occupy three half-words in memory (the 9 least-significant bits of each half-word). tx data buffer pointer this field always points to the first location of the associated data buffer. it can be even or odd, unless the number of actual data bits in the smcx uart character is greater than 8 bits, in which this field is even. for instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. the buffer can reside in internal or external memory.
communication processor module motorola mpc823e reference manual 16-405 smc communication 16 processor module 16.11.6.13 smcx uart event register. when a serial management controller is in uart mode, the 8-bit memory-mapped smcx event register is referred to as the smcx uart event (smceCuart) register. it is used to generate interrupts and report events recognized by the smcx uart channel. when an event is recognized, the smcx uart controller sets the corresponding bit in this register. a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared by reset and can be read at any time. an example of the timing of various events in the smceCuart register is illustrated in figure 16-119. bit 0, 2, and 4reserved these bits are reserved and must be set to 0. brkebreak end this bit indicates that an end of break sequence has been detected. it occurs after one idle bit is received after a break sequence. brkbreak character received this bit indicates that a break character has been received. if a very long break sequence occurs, this interrupt only occurs once after the first all-zeros character is received. bsybusy condition this bit indicates that a character has been received and discarded due to a lack of buffers. it is be set in the middle of the last stop bit of the first receive character for which there is no available buffer. reception continues when an empty buffer is provided. txtx buffer this bit indicates that a buffer has been transmitted over the smcx uart channel. it is set once the transmit data of the last character in the buffer is written to the transmit fifo. you must wait two character times to be sure that the data is completely sent over the transmit pin. smce Cuart bit 0 1 2 3 4 5 6 7 field reserved brke reserved brk reserved bsy tx rx reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa86 (smc1), 0xa96 (smc2)
communication processor module 16-406 mpc823e reference manual motorola smc communication 16 processor module rxreceive buffer this bit indicates that a buffer has been received and its associated rx buffer descriptor is now closed. it is set in the middle of the last stop bit of the last character that is written to the receive buffer. figure 16-119. smcx uart interrupt example line idle 10 characters characters received by smc uart time rxd line idle line idle 7 characters line idle txd rx rx tx break brk notes: 1. the first rx event assumes receive buffers are six bytes each. 2. the second rx event position is programmable based on the max_idl value. 3. the brk event occurs after the first break character is received. note: the tx event assumes all seven characters were put into a single buffer, and the tx event occurred when the seventh character was written to the smc transmit fifo. smc uart smce events characters transmitted by smc uart smc uart smce events brke
communication processor module motorola mpc823e reference manual 16-407 smc communication 16 processor module 16.11.6.14 smcx uart mask register. when a serial management controller is in uart mode, the 8-bit read/write smcx mask register is referred to as the smcx uart mask (smcmCuart) register. it has the same bit format as the smceCuart register. if a bit in this register is a 1, the corresponding interrupt in the smceCuart register is enabled. if the bit is zero, the corresponding interrupt in the smceCuart register is masked. 16.11.6.15 smc1 uart controller programming example. the following is an initialization sequence for 9,600 baud, 8 data bits, no parity, and 1 stop bit operation of an smc1 uart controller assuming a 25mhz system frequency. brg1 and smc1 are used. 1. configure the port b pins to enable smtxd1 and smrxd1. write pbpar bits 25 and 24 with ones and then pbdir and pbodr bits 25 and 24 with zeros. 2. configure the brg1. write 0x010144 to brgc1. the div16 bit is not used and the divider is 162 (decimal). the resulting brg1 clock is 16 the preferred bit rate of the smc1 uart controller. 3. connect the brg1 clock to smc1 using the serial interface. write the smc1 bit in simode with a 0 and the smc1cs field in simode register with 0x000. 4. write rbase and tbase in the smc1 parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 5. program the cpcr to execute the init rx and tx params command. write 0x0091 to the cpcr. 6. write 0x0001 to the sdcr to initialize the sdma configuration register. 7. write 0x18 to the rfcr and tfcr for normal operation. 8. write mrblr with the maximum number of bytes per receive buffer. assume 16 bytes, so mrblr = 0x0010. 9. write max_idl with 0x0000 in the smc1 uart parameter ram to disable the max_idl functionality for this example. 10. clear brkln and brkec in the smc1 uart parameter ram for the clarity. 11. set brkcr to 0x0001, so that if a stop transmit command is issued, one break character is sent. smcmCuart bit 0 1 2 3 4 5 6 7 field reserved brke reserved brk reserved bsy tx rx reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa8a (smc1), 0xa94 (smc2)
communication processor module 16-408 mpc823e reference manual motorola smc communication 16 processor module 12. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (not required), and 0x00001000 to rx_bd_pointer. 13. initialize the tx buffer descriptor. assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. then write 0xb000 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 14. write 0xff to the smceCuart register to clear any previous events. 15. write 0x17 to the smcmCuart register to enable all possible serial management controller interrupts. 16. write 0x00000010 to the cimr so smc1 can generate a system interrupt. the cicr must also be initialized. 17. write 0x4820 to smcmr to configure normal operation (not loopback), 8-bit characters, no parity, 1 stop bit. notice that the transmitter and receiver are not enabled yet. 18. write 0x4823 to smcmr to enable the smc1 transmitter and receiver. this additional write ensures that the ten and ren bits are enabled last. 16.11.6.16 handling interrupts in the smcx uart controller. follow these steps to handle an interrupt in a serial management controller: 1. once an interrupt occurs, read the smceCuart register to discover the cause of the interrupt. to clear the smce bits, write ones to them. 2. process the tx buffer descriptor to reuse it if the tx bit is set in the smceCuart register. extract data from the rx buffer descriptor if the rx bit is set in the smceCuart. to transmit another buffer, set the r bit in the tx buffer descriptor. 3. clear the smcx bit in the cisr. 4. execute the rfi instruction. note: after 5 bytes are transmitted, the tx buffer descriptor is closed. the receive buffer is closed after 16 bytes are received. any data received after 16 bytes causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module motorola mpc823e reference manual 16-409 smc communication 16 processor module 16.11.7 the smcx in transparent mode a serial managment controller in transparent mode is also referred to as the smcx transparent controller. the following is a list of the features that the smcx transparent controller does not support: ? independent transmit and receive clocks, unless it is connected to a tdm channel of the serial interface ? crc generation and checking ? full rtsx , ctsx , and cdx pins. instead, there is a smsyn pin for each smc. ? ability to transmit data on demand using the transmit on demand register ? receiver/transmitter in transparent mode while executing another protocol ? 4-, 8-, or 16-bit sync recognition ? internal dpll support an smcx in transparent mode has one feature that an sccx in transparent mode does not. the serial management controllers allow a data character length option of 4 to 16 bits, whereas the sccs allow 8 or 32 bits, depending on how the rfw bit is set in the gsmr_h (described in section 16.9.2 the general sccx mode registers ). 16.11.7.1 features. the following list summarizes the features of a serial management controller in transparent mode: ? flexible data buffers ? connects to a tdm bus using the time-slot assigner in the serial interface ? transmits and receives transparently on its own set of pins using a sync pin to synchronize the beginning of transmission and reception to an external event ? programmable 4-16 character length ? reverse data mode ? continuous transmission and reception modes ? four available commands 16.11.7.2 smcx transparent channel transmission process. the smcx transparent transmitter is designed to work with almost no intervention from the core. when the core enables the smcx transmitter in transparent mode, it starts transmitting idles. the serial management controllers immediately poll the first buffer descriptor in the transmit channel buffer descriptor ring once every character time, depending on the character length (every 4 to 16 serial clocks). when there is a message to transmit, a serial management controller fetches the data from memory and starts transmitting the message after synchronization is achieved.
communication processor module 16-410 mpc823e reference manual motorola smc communication 16 processor module synchronization can be achieved in two ways. first, when the transmitter is connected to a tdm channel, it can be synchronized to a time-slot. once the frame sync is received, the transmitter waits for the first bit of its time-slot to occur before it starts transmitting. data is only transmitted during the time-slots defined by the time-slot assigner. secondly, when working with its own set of pins, the transmitter starts transmitting when the smsynx signal is asserted. when buffer descriptor data is completely written to the transmit fifo, the l bit is checked and if it is set, a serial management controller writes the message status bits into the buffer descriptor and clears the r bit. it then starts transmitting idles. when the end of the current buffer descriptor is reached and the l bit is not set, only the r bit is cleared. in both cases, an interrupt is issued according to the i bit in the buffer descriptor. by appropriately setting the i bit in each buffer descriptor, interrupts can be generated after each buffer, a specific buffer, or each block is transmitted. the serial management controller then proceeds to the next buffer descriptor in the table. if no additional buffers have been presented to the serial management controller for transmission and the l bit was cleared, an underrun is detected and the serial management controller begins transmitting idles. if the cm bit is set in the transmit buffer descriptor, the r bit is not cleared, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this data buffer. for instance, if a single transmit buffer descriptor is initialized with the cm bit and the w bit set, the data buffer is continuously transmitted until you clear the r bit of the buffer descriptor. 16.11.7.3 smcx transparent channel reception process. when the core enables the smcx receiver in transparent mode, it waits for synchronization before receiving data. once synchronization is achieved, the receiver transfers incoming data into memory according to the first receive buffer descriptor in the ring. synchronization can be achieved in two ways. first, when the receiver is connected to a tdm channel, it can be synchronized to a time-slot. once the frame sync is received, the receiver waits for the first bit of its time-slot to occur before reception begins. data is only received during the time-slots defined by the time-slot assigner. secondly, when working with its own set of pins, the receiver starts receiving when the smsynx signal is asserted. when the data buffer is filled, a smcx transparent controller clears the e bit in the buffer descriptor and generates an interrupt if the i bit in the buffer descriptor is set. if the incoming data exceeds the length of the data buffer, a serial management controller fetches the next buffer descriptor in the table and, if it is empty, continues transferring data to the associated data buffer. if the cm bit is set in the receive buffer descriptor, the e bit is not cleared, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this data buffer.
communication processor module motorola mpc823e reference manual 16-411 smc communication 16 processor module 16.11.7.4 using the smsyn x pin for synchronization. the smsynx pin offers a method to externally synchronize a smcx transparent channel. this method differs somewhat from the synchronization options available in the serial communication controllers and must be studied carefully. see figure 16-120 for an example. once the ren bit is set in the smcmr, the first rising edge of the smclk signal that finds the smsynx pin low causes the smcx receiver to achieve synchronization. data starts being received or latched on the same rising edge of smclk that latched smsynx . this is the first bit of data received. the receiver never loses synchronization again, regardless of the state of smsynx , until you clear the ren bit. once the ten bit is set in the smcmr, the first rising edge of the smclk signal that finds the smsynx pin low causes the smcx transmitter to achieve synchronization. the smcx transmitter begins transmitting ones asynchronously from the falling edge of smsynx . after one character of ones is transmitted, if the transmit fifo is loaded (the transmit buffer descriptor is ready with data), data starts being transmitted on the next falling edge of smclk after some multiple of all-ones (preamble) characters are transmitted. if the transmit fifo is loaded at some later time, the data starts transmitting after some multiple number of all-ones characters is transmitted. the transmitter never loses synchronization again, regardless of the state of smsynx , until you clear the ten bit or issue the enter hunt mode command. note: regardless of whether the transmitter or receiver uses the smsynx signal, it must make glitch-free transitions from high to low or low to high. glitches on smsynx can cause a serial management controller to behave erratically.
communication processor module 16-412 mpc823e reference manual motorola smc communication 16 processor module if both the ren and ten bits are set in the smcmr, the first falling edge of the smsynx pin causes both the transmitter and receiver to achieve synchronization. to resynchronize the transmitter or receiver, the smcx transmitter/receiver can be disabled and reenabled and the smsynx pin can be used again to resynchronize the transmitter or receiver. refer to section 16.11.5 disabling the smcs on-the-fly for a description of how to safely disable and reenable a serial management controller. simply clearing and setting the ten bit may not be sufficient. figure 16-120. smsynx pin synchronization smrxd smc1 receive data smtxd smsynx smclk ten set here tx fifo loaded appx. here smsynx detected low here smclk smsynx ren set here or enter hunt mode command issued first bit of receive data (lsb) 1s are sent smsynx detected low here smc1 transmit data first bit of first 5-bit transmit character (lsb) notes: 1. smclk is an internal clock derived from an external clock pin or a baud rate generator. 2. this example shows the smc receiver and transmitter enabled separately. if the ren and ten bits were set at the same time, a single falling edge of smsynx would synchronize both. five 1s assume character length equals 5 transmission could begin here if tx fifo not loaded in time five 1s are sent
communication processor module motorola mpc823e reference manual 16-413 smc communication 16 processor module 16.11.7.5 using the time-slot assigner for synchronization. the time-slot assigner offers a method to internally synchronize a smcx transparent channel without using the smsynx pin. this method is similar to that of the smsynx pin, except that the synchronization event is not the falling edge of the smsynx signal, but the first time-slot for this smcx receiver/transmitter after the frame sync indication. refer to section 16.7 the serial interface with time-slot assigner for further information about configuring time-slots for the smcs and sccs. the time-slot assigner allows the smcx receiver and transmitter to be enabled simultaneously and synchronized, a capability that the smsynx pin does not provide. refer to figure 16-121 for an example of synchronization using the time-slot assigner. figure 16-121. time-slot assigner synchronization tdm rx smc1 smc1 tdm tx smc1 tdm txsync tdm tx clock smc1 tdm rx sync tdm rx clock after ten is set, transmission begins here if smc runs out of tx buffers and new ones are provided later, transmission begins at the beginning of either time-slot after ren is set or after enter hunt mode command, reception begins here
communication processor module 16-414 mpc823e reference manual motorola smc communication 16 processor module once the ren bit is set in the smcmr, the first time-slot after frame sync causes the smcx receiver to achieve synchronization. data is received immediately, but only during the defined receive time-slots. the receiver continues receiving data during its defined time-slots until you clear the ren bit. if the enter hunt mode command is issued, the receiver loses synchronization, closes the current buffer, and resynchronizes to the first time-slot after the frame sync. once the ten bit is set in the smcmr, an smcx transparent controller waits for the transmit fifo to be loaded before trying to achieve synchronization. once the transmit fifo is loaded, synchronization and transmission begins, depending on the following situations: ? if a buffer is made ready when an smcx transparent controller is enabled, then the first byte will be placed in time-slot 1 if the clen field in smcmr is set to 8 and slot 2 if clen is set to 16. ? if a buffer has an smcx transparent controller enabled, then the first byte in the next buffer can appear in any time-slot associated with this channel. ? if a buffer is ended with the l bit set, then the next buffer can appear in any time-slot associated with this channel. if an smcx transparent controller runs out of transmit buffers and a new transmit buffer is provided later, idles are transmitted during the gap between data buffers. data transmission from the later data buffer begins at the beginning of an smcx transparent controller time-slot, but not necessarily the first time-slot after the frame sync. so if you want to maintain a certain bit alignment beginning with the first time-slot, make sure that at least one tx buffer descriptor is always ready and that no underrun occurs. otherwise, the smcx transparent transmitter must be disabled and reenabled. refer to section 16.11.5 disabling the smcs on-the-fly for a description of how to safely disable and reenable the smcx transparent controller. simply clearing and setting ten may not be sufficient.
communication processor module motorola mpc823e reference manual 16-415 smc communication 16 processor module 16.11.7.6 smcx transparent controller parameter ram memory map. there is no protocol-specific parameter ram for the smcx transparent controller. only the general smcx parameter ram is used. see section 16.11.4 smc general parameter ram memory map for more information. 16.11.7.7 smcx transparent commands. you can program the cpcr (described in section 16.2.6.1 cpm command register ) with the following commands to transmit data. ? stop transmit after the hardware or software is reset and the channel is enabled in the smcmCtransparent register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table. this command disables the transmission of frames on the transmit channel. if the transparent controller receives this command while transmitting a frame, it stops after the contents of the fifo are transmitted (up to 2 characters). the tbptr is not advanced to the next buffer descriptor, no new buffer descriptor is accessed, and no new buffers are transmitted for this channel. the transmitter sends idles until the restart transmit command is issued. ? restart transmit this command is used to begin or continue transmission from the current tbptr in the channels tx buffer descriptor table. when the channel receives this command, it starts polling the r bit in the tx buffer descriptor. a serial management controller expects this command after a stop transmit command is issued and the channel in the smcmr is disabled or after a transmitter error occurs. ? init tx parameters this command initializes all the transmit parameters in this serial channel parameter ram to their reset state and must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. you can program the cpcr with the following commands to receive data. ? enter hunt mode this command forces a serial management controller to close the current receive buffer descriptor if it is currently being used and to use the next buffer descriptor in the list for any subsequently received data. if a serial management controller is not in the process of receiving data, the buffer is not closed. additionally, this command causes the receiver to wait for a resynchronization before further reception continues. ? close rx bd this command is used to force a serial management controller to close the current receive buffer descriptor if it is being used and to use the next buffer descriptor in the list for any subsequently received data. if a serial management controller is not in the process of receiving data, no action is taken by this command. ? init rx parameters this command initializes all the receive parameters in this serial channels parameter ram to their reset state. it must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters.
communication processor module 16-416 mpc823e reference manual motorola smc communication 16 processor module 16.11.7.8 smcx transparent controller errors. the serial management controllers report message reception and transmission error conditions using the channel buffer descriptors and the smceCtransparent register. the following transmission errors can be detected by the smcx transparent controller. ? underrun error when this error occurs, the channel stops transmitting the buffer, closes it, sets the un bit in the buffer descriptor, sets the txe bit in the event register and causes an interrupt if the txe bit is set in the mask register. the channel resumes transmission after it receives the restart transmit command. underrun cannot occur between frames. ? overrun error a serial management controller maintains an internal fifo for receiving data. the communication processor module begins programming the sdma channel if the data buffer is in external memory when the first character is received into the fifo. if a fifo overrun occurs, a serial management controller writes the received data character to the internal fifo over the previously received character. the previous character and its status bits are lost. then the channel closes the buffer, sets the ov bit in the receive buffer descriptor, and generates the receive interrupt if it is enabled. reception then continues as normal. 16.11.7.9 smcx transparent mode register. when a serial management controller is in transparent mode, the 16-bit, memory-mapped, read/write smcx mode register is referred to as the smcx transparent mode register (smcmrCtransparent). the function of bits 8-15 is common to each smcx protocol, but bits 0-7 vary according to the protocol selected by the sm bits of this register. bits 0, 5, and 8C9reserved these bits are reserved and must be set to 0. smcmrCtransparent bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res clen res bs revd reserved sm dm ten ren reset 0 0 000 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa82 (smc1), 0xa92 (smc2)
communication processor module motorola mpc823e reference manual 16-417 smc communication 16 processor module clencharacter length this field is programmed with a value between 3 and 15 to obtain 4 to 16 bits per character. if the character length is less than 8 bits, the msbs of the byte in buffer memory are not used on transmit and are written with zeros on receive. on the other hand, if the character length is more than 8 bits but less than 16 bits, the msbs of the half-word in buffer memory are not used on transmit and are written with zeros on receive. bsbyte sequence this bit controls the sequence of byte transmission if the revd bit is set for a character length greater than 8 bits. it must be set to zero to maintain behavior compatibility with the mc68360 quicc microprocessor. 0 = normal mode. this must be selected if the character length is less than or equal to 8 bits. 1 = transmit lower address byte first. revdreverse data 0 = normal mode. 1 = reverse the character bit order. the msb is transmitted first. smsmcx mode 00 = gci or scit mode. 01 = reserved. 10 = uart mode. 11 = totally transparent mode. this must be selected for smcx transparent operation. dmdiagnostic mode 00 = normal mode. 01 = local loopback mode. 10 = echo mode. 11 = reserved. tensmcx transmit enable 0 = smcx transmitter disabled. 1 = smcx transmitter enabled. note: erratic behavior will occur if you do not write the values 0 to 2 to clen. larger character lengths increase the potential performance of the smcx channel and lower the performance impact of other channels. for instance, using 16-bit characters, rather than 8-bit characters is recommended if 16-bit characters are acceptable in the final application. note: once the ten bit is cleared, it must not be reenabled for at least three serial clocks.
communication processor module 16-418 mpc823e reference manual motorola smc communication 16 processor module rensmcx receive enable 0 = smcx receiver disabled. 1 = smcx receiver enabled. 16.11.7.10 smcx transparent receive buffer descriptor. using receive (rx) buffer descriptors, the communication processor module reports information about the received data for each buffer and closes the current buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the following events occurs: ? an overrun error occurs ? a full receive buffer is detected ? the enter hunt mode command is issued eempty 0 = the data buffer associated with this rx buffer descriptor is filled with received data or data reception has been aborted due to an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or is currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 4C5, 7C13, and 15reserved these bits are reserved and must be set to 0. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi reserved cm reserved ov res offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module motorola mpc823e reference manual 16-419 smc communication 16 processor module wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is filled. 1 = the rx bit in the smceCtransparent register is set when this buffer is completely filled by the communication processor module, thus indicating that the core needs to process the buffer. the rx bit can cause an interrupt if it is enabled. cmcontinuous mode 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this buffer descriptor. however, the e bit is cleared if an error occurs during reception, regardless of how the cm bit is set. ovoverrun this bit indicates that a receiver overrun has occurred during message reception. the communication processor module writes this bit after the received data is placed into the associated data buffer. data length this field represents the number of octets that the communication processor module writes into this data buffer. it is only written once by the communication processor module as the buffer is closed. the communication processor module writes this field after the received data is placed into the associated data buffer. rx data buffer pointer this field always points to the first location of the associated data buffer, must be even, and can reside in internal or external memory. the communication processor module writes these bits after the received data is placed into the associated data buffer. note: the actual amount of memory allocated for this buffer must be greater than or equal to the mrblr entry.
communication processor module 16-420 mpc823e reference manual motorola smc communication 16 processor module 16.11.7.11 smcx transparent transmit buffer descriptor. data is sent to the communication processor module for transmission on an smcx channel by arranging it in buffers referenced by the channels transmit (tx) buffer descriptor table. using the buffer descriptors, the communication processor module confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission and you are free to manipulate it or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered. 1 = the data buffer, which you prepare for transmission, is not transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1, 5, 7C13, and 15reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table is programmable and determined by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the tx and txe bits in the smceCtransparent register are set when this buffer is serviced. tx and txe can cause interrupts if they are enabled. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi l res cm reserved un res offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module motorola mpc823e reference manual 16-421 smc communication 16 processor module l last in message 0 = the last byte in the buffer is not the last byte in the transmitted transparent frame. data from the next transmit buffer (if ready) is transmitted immediately following the last byte of this buffer. 1 = the last byte in this buffer is the last byte in the transmitted transparent frame. after this buffer is transmitted, the transmitter requires synchronization before the next buffer is transmitted. cmcontinuous mode 0 = normal operation. 1 = the communication processor module does not clear the r bit after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor. however, the r bit will be cleared if an error occurs during transmission, regardless of how the cm bit is set. ununderrun this bit indicates that a serial management controller has encountered a transmitter underrun condition while transmitting the associated data buffer. data length this field represents the number of octets that the communication processor module must transmit from this data buffer and it is never modified by the communication processor module. this field can be even or odd, but if the number of bits in the transparent character is greater than 8, this field must be even. for example, to transmit three transparent 8-bit characters, this field must be initialized to 3. however, to transmit three transparent 9-bit characters, this field must be initialized to 6 since the three 9-bit characters occupy three half-words in memory. tx data buffer pointer this field always points to the first byte of the associated data buffer. they can be even or odd, unless the character length is greater than 8 bits, in which case this field must be even. for instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. the buffer can reside in internal or external memory.
communication processor module 16-422 mpc823e reference manual motorola smc communication 16 processor module 16.11.7.12 smcx transparent event register. when a serial management controller is in transparent mode, the 8-bit memory-mapped smcx event register is referred to as the smcx transparent event (smceCtransparent) register. it is used to generate interrupts and report events recognized by the smcx channel. when an event is recognized, the serial management controller sets the corresponding bit in this register. interrupts generated by this register can be masked in the smcmCtransparent register. a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared at reset and can be read at any time. bits 0C2 and 4reserved these bits are reserved and must be set to 0. txetx error this bit indicates that an underrun error has occurred on the transmitter channel. bsybusy condition this bit indicates that a character has been received and discarded due to a lack of buffers. reception begins after a new buffer is provided. you can execute an enter hunt mode command to make the receiver wait for resynchronization. txtx buffer this bit indicates that a buffer has been transmitted. if the l bit of the tx buffer descriptor is set, this bit is set when the last data character starts being transmitted and you must wait one character time to be sure that the data is completely sent over the transmit pin. if the l bit of the tx buffer descriptor is cleared, this bit is set when the last data character is written to the transmit fifo and you must wait two character times to be sure that the data is completely sent over the transmit pin. rxrx buffer this bit indicates that a data buffer has been received on the smcx channel and its associated rx buffer descriptor is now closed. this bit is set after the last character is written to the buffer. smceCtransparent bit 0 1 2 3 4 5 6 7 field reserved txe res bsy tx rx reset 0 00000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa86 (smc1), 0xa96 (smc2)
communication processor module motorola mpc823e reference manual 16-423 smc communication 16 processor module 16.11.7.13 smcx transparent mask register. when a serial management controller is in transparent mode, the 8-bit read/write smcx mask register is referred to as the smcx transparent mask (smcmCtransparent) register. it has the same bit format as the smceCtransparent register. if a bit in this register is a 1, the corresponding interrupt in the smceCtransparent register is enabled. if the bit is zero, the corresponding interrupt is masked. 16.11.7.14 smcx transparent nmsi programming example. the following is an example initialization sequence for an smc1 transparent channel over its own set of pins. the transmit and receive clocks are provided by the clk3 pin and the smsyn1 pin is used to obtain synchronization. 1. configure the port b pins to enable the smtxd1, smrxd1, and smsyn1 pins. write pbpar bits 25, 24, and 23 with ones and then pbdir and pbodr bits 25, 24, and 23 with zeros. 2. configure the port a pins to enable clk3. write papar bit 5 with a one and padir bit 5 with a zero. the other functions of this pin are the timers or the time-slot assigner. these alternate functions cannot be used on this pin. 3. connect the clk3 clock to smc1 using the serial interface. write the smc1 bit in the simode register with a 0 and the smc1cs field in the simode register with 110. 4. write rbase and tbase in the smcx parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of the dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 5. program the cpcr to execute the init rx and tx params command. write 0x0091 to the cpcr. 6. write 0x0001 to the sdcr to initialize the sdma configuration register. 7. write 0x18 to rfcr and tfcr for normal operation. 8. write mrblr with the maximum number of bytes per receive buffer. assume 16 bytes, so mrblr = 0x0010. 9. initialize the rx buffer descriptor and assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. smcmCtransparent bit 0 1 2 3 4 5 6 7 field reserved txe res bsy tx rx reset 0 00000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa8a (smc1), 0xa9a (smc2)
communication processor module 16-424 mpc823e reference manual motorola smc communication 16 processor module 10. initialize the tx buffer descriptor and assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xb000 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 11. write 0xff to the smceCtransparent register to clear any previous events. 12. write 0x13 to the smcmCtransparent register to enable all possible serial management controller interrupts. 13. write 0x00000010 to the cimr to allow smc1 to generate a system interrupt. the cicr must also be initialized. 14. write 0x3830 to the smcmr to configure 8-bit characters, unreversed data, and normal operation (not loopback). notice that the transmitter and receiver have not been enabled yet. 15. write 0x3833 to the smcmr to enable the smcx transmitter and receiver. this additional write ensures that the ten and ren bits are enabled last. 16.11.7.15 smc1 transparent tsa programming example. the following is an example initialization sequence for the smc1 transparent channel over the time-slot assigner. it is assumed that the time-slot assigner and tdm pins have already been set up to route time-slot data to the smc1 transmitter and receiver. refer to section 16.7 the serial interface with time-slot assigner for examples of how to configure the time-slot assigner. the transmit and receive clocks and synchronization signals are provided internally from the time-slot assigner. 1. write rbase and tbase in the smc1 parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of the dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 2. program the cpcr to execute the init tx and rx params command. write 0x0091 to the cpcr. 3. write 0x0001 to the sdcr to initialize the sdma configuration register. 4. write 0x18 to rfcr and tfcr for normal operation. 5. write mrblr with the maximum number of bytes per receive buffer. assume 16 bytes, so mrblr = 0x0010. 6. initialize the rx buffer descriptor and assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. note: after 5 bytes are transmitted, the tx buffer descriptor is closed and after 16 bytes are received the receive buffer is closed too. any data received after 16 bytes causes a busy (out-of-buffers) condition since only one rx buffer descriptor is prepared.
communication processor module motorola mpc823e reference manual 16-425 smc communication 16 processor module 7. initialize the tx buffer descriptor and assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xb000 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 8. write 0xff to the smceCtransparent register to clear any previous events. 9. write 0x13 to the smcmCtransparent register to enable all possible serial management controller interrupts. 10. write 0x00000010 to the cimr so that smc1 can generate a system interrupt. the cicr must also be initialized. 11. write 0x3830 to the smcmrCtransparent to configure 8-bit characters, unreversed data, and normal operation (not loopback). notice that the transmitter and receiver are not enabled yet. 12. write 0x3833 to the smcmrCtransparent to enable the smc1 transmitter and receiver. this additional write ensures that the ten and ren bits are enabled last. 16.11.7.16 handling interrupts in the smcx. follow these steps to handle an interrupt in the serial management controller: 1. once an interrupt occurs, read the smce register to discover the cause of the interrupts. the smce bits are usually cleared at this time. 2. process the tx buffer descriptor to reuse it if the tx bit is set in the smceC transparent register. extract data from the rx buffer descriptor if the rx bit is set in the smceCtransparent register. to transmit another buffer, simply set the r bit in the rx buffer descriptor. 3. clear the smc1 bit in the cisr. 4. execute the rfi instruction. 16.11.8 the smcx in gci mode the serial management controllers can be used to control the circuit interface and monitor channels of the general circuit interface (gci) frame. when using the scit configuration of a general circuit interface, one serial management controller can handle scit channel 0, and the other serial management controller can handle scit channel 1. the main features of a serial management controller in gci mode are as follows: ? each smcx channel supports the circuit interface and monitor channels of the gci (iom-2) in isdn applications ? two serial management controllers support the two sets of circuit interface and monitor channels in scit channels 0 and 1 ? full-duplex operation ? local loopback and echo capability for testing
communication processor module 16-426 mpc823e reference manual motorola smc communication 16 processor module to use the smcx gci channels properly, the time-slot assigner in the serial interface must be configured to route the monitor and circuit interface channels to the serial management controller you prefer. refer to section 16.7 the serial interface with time-slot assigner for more details on how to program this configuration. a serial management controller in gci mode is also referred to as the smcx gci controller. 16.11.8.0.1 smcx gci monitor channel transmission process. the monitor channel 0 is used to exchange data with a layer 1 device (reading and writing internal registers and transferring the s and q bits). monitor channel 1 is used for programming and controlling voice/data modules, such as codecs. the core writes the data byte into the transmit (tx) buffer descriptor. the serial management controller transmits the data on the monitor channel and handles the a and e control bits according to the gci monitor channel protocol. you can issue the timeout command to solve deadlocks when errors in the a and e bit occur on the data line. 16.11.8.0.2 smcx gci monitor channel reception process. the serial management controller receives data and handles the a and e control bits according to the gci monitor channel protocol. when the communication processor module stores a received data byte in the smcx receive (rx) buffer descriptor, a maskable interrupt is generated. you can issue the transmit abort request command and the mpc823e transmits an abort request on the e bit. 16.11.8.1 handling the smcx circuit interface channel. the circuit interface channel is used to control the layer 1 device. the layer 2 device in the te sends commands and receives indication to or from the upstream layer 1 device via circuit interface channel 0. in the scit configuration, circuit interface channel 1 is used to convey real-time status information between the layer 2 device and nonlayer 1 peripheral devices (codecs). 16.11.8.1.1 smcx gci circuit interface channel transmission process. the core writes the data byte into the circuit interface tx buffer descriptor and the serial management controller transmits the data continuously on the circuit interface channel to the physical layer device. 16.11.8.1.2 smcx gci circuit interface channel reception process. the smcx receiver continuously monitors the circuit interface channel and when it recognizes a change in the data and this value is received in two successive frames, it is interpreted as valid data. this is referred to as the double last-look method. the received data byte is stored by the communication processor module in the circuit interface rx buffer descriptor and a maskable interrupt is generated. if the serial management controller is configured to support scit channel 1, the double last-look method is not used.
communication processor module motorola mpc823e reference manual 16-427 smc communication 16 processor module 16.11.8.2 smcx gci parameter ram memory map. the smcx gci parameter ram area begins at the same offset from each smcx base area. the smcx in gci mode has a very different parameter ram memory map than the smcx in uart or transparent mode. in gci mode, the general-purpose parameter ram contains the buffer descriptors, instead of pointers, to the buffer descriptors. you can see the difference when you compare table 16-38 with table 16-36. the smcx in gci mode contains no protocol-specific parameter ram. ? m_rxbdthe smcx monitor channel receive buffer descriptor is used by the communication processor module to report information about the monitor channel receive byte. eempty when a serial management controller uses the monitor channel protocol, it waits until the core sets this bit before acknowledging the monitor channel data. 0 = the communication processor module clears this bit to indicate that the data byte associated with this buffer descriptor is now available to the core. 1 = the core sets this bit to indicate that the data byte associated with this buffer descriptor has been read. table 16-38. smcx gci parameter ram memory map address name width description smcx base + 00 m_rxbd half-word monitor channel rx buffer descriptor smcx base + 02 m_txbd half-word monitor channel tx buffer descriptor smcx base + 04 ci_rxbd half-word circuit interface channel rx buffer descriptor smcx base + 06 ci_txbd half-word circuit interface channel tx buffer descriptor smcx base + 08 temp1 half-word smcbase + 0a temp2 half-word smcx base + 0c temp3 half-word smcx base + 0e temp4 half-word note: you are only responsible for initializing the items in bold. smcx base = (immr & 0xffff0000) + 0x3e80 (smc1) and 0x3f80 (smc2). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e l re ms reserved data note: you are only responsible for initializing the items in bold.
communication processor module 16-428 mpc823e reference manual motorola smc communication 16 processor module llast (eom) this bit is only valid when a serial management controller implements the monitor channel protocol and is set when the eom indication is received on the e bit. when this bit is set, the data byte is invalid. ererror condition this bit is only valid when a serial management controller implements the monitor channel protocol and is set when an error condition occurs on the monitor channel protocol. a new byte is transmitted before a serial management controller acknowledges the previous byte. msdata mismatch this bit is only valid when a serial management controller implements the monitor channel protocol. it is set when two different consecutive bytes are received and it is cleared when the last two consecutive bytes match. a serial management controller waits for the reception of two identical consecutive bytes before writing new data to the rx buffer descriptor. bits 4C7reserved these bits are reserved and must be set to 0. datadata this field contains the monitor channel data byte that a serial management controller received. ? m_txbdthe smcx monitor channel transmit buffer descriptor is used by the communication processor module to report information about the monitor channel transmit byte. rready 0 = this bit is cleared by the communication processor module after transmission. the tx buffer descriptor is now available to the core. 1 = the core sets this bit to indicate that the data byte associated with this buffer descriptor is ready for transmission. llast (eom) this bit is only valid when a serial management controller implements the monitor channel protocol. when it is set, a serial management controller first transmits the buffer data and then transmits the eom indication on the e bit. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 rlar reserved data note: you are only responsible for initializing the items in bold.
communication processor module motorola mpc823e reference manual 16-429 smc communication 16 processor module arabort request this bit is only valid when a serial management controller uses the monitor channel protocol and it is set by a serial management controller when an abort request is received on the a bit. the smcx transmitter transmits the eom on the e bit after an abort request is received. bits 3C7reserved these bits are reserved and must be set to 0. datadata field this field contains the data to be transmitted by a serial management controller on the monitor channel. ? c/i_rxbdthe smcx circuit interface channel receive (rx) buffer descriptor is used by the communication processor module to report information about the circuit interface channel receive byte. eempty 0 = the communication processor module clears this bit to indicate that the data byte associated with this buffer descriptor is now available to the core. 1 = the core set this bit to indicate that the data byte associated with this buffer descriptor has been read. bits 1C7 and 14C15reserved these bits are reserved and must be set to 0. c/i datacommand/indication data bits this field represents a 4-bit data field for circuit interface channel 0 and a 6-bit data field for circuit interface channel 1. it contains the data received from the circuit interface channel. for circuit interface channel 0, bits 10-13 contain the 4-bit data field and bits 8 and 9 are always written with zeros. for circuit interface channel 1, bits 8-13 contain the 6-bit data field. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res c/i data reserved note: additional data received is discarded until the e bit is set.
communication processor module 16-430 mpc823e reference manual motorola smc communication 16 processor module ? c/i_txbdthe smcx circuit interface channel transmit (tx) buffer descriptor is used by the communication processor module to report information about the circuit interface channel transmit byte. rready 0 = the communication processor module clears this bit after transmission to indicate that the buffer descriptor is now available to the core. 1 = the core sets this bit to indicate that the data associated with this buffer descriptor is ready for transmission. bits 1C7 and 14C15reserved these bits are reserved and must be set to 0. c/i datacommand/indication data bits this field represents a 4-bit data field for circuit interface channel 0 and a 6-bit data field for circuit interface channel 1. it contains the data to be transmitted onto the circuit interface channel. for circuit interface channel 0, bits 10-13 contain the 4-bit data field and bits 8 and 9 are always written with zeros. for circuit interface channel 1, bits 8-13 contain the 6-bit data field. ? temp1C4these bits are used internally by the risc microcontroller. 16.11.8.3 smcx gci commands. the following commands are issued to the cpm command register. ? init tx and rx params this command initializes the transmit and receive parameters in the parameter ram to their reset state and it is especially useful when switching protocols on a given serial channel. ? transmit abort request this receiver command can be issued when the mpc823e implements the monitor channel protocol. when it is issued, the mpc823e sends an abort request on the a bit. ? timeout this transmitter command can be issued when the mpc823e implements the monitor channel protocol and it is usually issued because the device is not responding or a bit errors are detected. the mpc823e sends an abort request on the e bit at the time this command is issued. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r reserved c/i data reserved
communication processor module motorola mpc823e reference manual 16-431 smc communication 16 processor module 16.11.8.4 smcx gci mode register. when a serial management controller is in gci mode, the 16-bit, memory-mapped, read/write smcx mode register is referred to as the smcx gci mode (smcmCgci) register. the functions of bits 8C15 are common to each smcx protocol, but bits 0C7 vary according to the protocol selected by the sm bits. bits 0, 6, and 8C9reserved these bits are reserved and must be set to 0. clencharacter length this field is used to define the total number of bits in the circuit interface and monitor channels of the scit channels 0 or 1. clen ranges from 0 to 15 and specifies values from 1 to 16 bits. clen must be written with 13 for the scit channel 0 or gci (8 data bits, plus a and e bits, plus 4 circuit interface bits = 14 bits) or with 15 for the scit channel 1 (8 data, bits, plus a and e bits, plus 6 circuit interface bits = 16 bits). memonitor enable 0 = the serial management controller does not support the monitor channel. 1 = the serial management controller supports the monitor channel with the monitor channel protocol. c#scit channel number 0 = scit channel 0. 1 = scit channel 1. required for siemens arcofi and sgs s/t chips. smsmcx mode 00 = gci or scit mode. required for smcx gci or scit operation. 01 = reserved. 10 = uart mode. 11 = totally transparent mode. dmdiagnostic mode 00 = normal mode. 01 = local loopback mode. 10 = echo mode. 11 = reserved. smcmCgci bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res clen me res c# res sm dm ten ren reset 0 0 000 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa82 (smcmr1), 0xa92 (smcmr2)
communication processor module 16-432 mpc823e reference manual motorola spi communication 16 processor module tensmcx transmit enable 0 = smcx transmitter disabled. 1 = smcx transmitter enabled. rensmcx receive enable 0 = smcx receiver disabled. 1 = smcx receiver enabled. 16.11.8.5 smcx gci event register. when a serial management controller is in gci mode, the 8-bit memory-mapped smcx event register is referred to as the smcx gci event (smceCgci) register. it is used to generate interrupts and report events recognized by the smcx channel. when an event is recognized, a serial management controller sets the corresponding bit in this register. interrupts generated by this register can be masked in the smcmCgci register. a bit is cleared by writing a 1 (writing a zero has no effect) more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module clears the internal interrupt request to the cpm interrupt controller. this register is cleared by reset and can be read at any time. bits 0C3reserved these bits are reserved and must be set to 0. ctxbcircuit interface channel buffer transmitted this bit indicates that the circuit interface transmit buffer is now empty. crxbcircuit interface channel buffer received this bit indicates when the circuit interface receive buffer is full. mtxbmonitor channel buffer transmitted this bit indicates that the monitor transmit buffer is now empty. mrxbmonitor channel buffer received this bit indicates when the monitor receive buffer is full. smceCgci bit 0 1 2 3 4 5 6 7 field reserved ctxb crxb mtxb mrxb reset 0 0000 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa86 (smc1), 0xa96 (smc2)
communication processor module motorola mpc823e reference manual 16-433 spi communication 16 processor module 16.11.8.6 smcx gci mask register. when a serial management controller is in gci mode, the 8-bit, memory-mapped, read/write smcx mask register is referred to as the smcx gci mask (smcmCgci) register. it has the same bit format as the smceCgci register. if a bit in this register is a 1, the corresponding interrupt in the smceCgci is enabled. if the bit is zero, the corresponding interrupt in the smceCgci is masked. 16.12 the serial peripheral interface the serial peripheral interface (spi) allows the mpc823e to exchange data between other mpc8xx microprocessors, the mc68328, mc68360, and mc68302 embedded microprocessors, as well as the mc68hc11 and mc68hc05 microcontroller families and a variety of peripheral devices. the serial peripheral interface is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock and slave select). the spi block consists of transmitter and receiver sections, an independent baud rate generator, and a control unit. the transmitter and receiver sections use the same clock, which is derived from the spi baud rate generator in master mode and generated externally in slave mode. during an spi transfer, data is transmitted and received simultaneously. because the spi receiver and transmitter are double-buffered, as illustrated in the block diagram below, the effective fifo size is 2 characters. you can program the mpc823e serial peripheral interface to shift out the most- or least-significant bit first. when the serial peripheral interface is not enabled in the spmode register, it consumes very little power. smcmCgci bit 0 1 2 3 4 5 6 7 field reserved ctxb crxb mtxb mrxb reset 0 0000 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xa8a (smc1), 0xa9a(smc2)
communication processor module 16-434 mpc823e reference manual motorola spi communication 16 processor module 16.12.1 features the following is a list of the serial peripheral interfaces main features: ? four-wire interface (spimosi, spimiso, spiclk, and spisel ) ? full-duplex operation ? works with data characters from 4 to 16 bits long ? supports back-to-back character transmission and reception ? master or slave spi modes supported ? multimaster environment support ? continuous transfer mode for autoscanning peripherals ? supports maximum clock rates of 6.25mhz in master mode and 12.5mhz in slave mode, assuming a 25mhz system clock is used ? independent programmable baud rate generator ? programmable clock phase and polarity ? open-drain output pins support multimaster configuration ? local loopback capability for testing figure 16-122. spi block diagram transmit_reg receive_reg shift_register counter pins interface spi mode reg peripheral bus imb spi brg spimiso spimosi spiclk in_clk rxd txd brgclk spisel
communication processor module motorola mpc823e reference manual 16-435 spi communication 16 processor module 16.12.2 spi clocking and pin functions you can configure the serial peripheral interface as a master for the serial channel or as a slave. you can also use it in a multimaster environment. when the serial peripheral interface is a master, use the spi baud rate generator to generate the spi transmit and receive clocks. it takes its input from the brgclk, which is generated in the clock synthesizer of the mpc823e, specifically for the spi baud rate generator and the other three baud rate generators in the communication processor module. the spimiso pin is an input in master mode and an output in slave mode. it follows then, that the spimosi pin is an output in master mode and an input in slave mode. the spimosi and spimiso pins change functionality between master and slave mode to support a multimaster configuration that allows communication from one serial peripheral interface to another with the same hardware configuration. when the serial peripheral interface is in master mode, spiclk is the clock output signal that shifts in the received data from the spimiso pin and shifts out the transmitted data to the spimosi pin. additionally, an spi master device must provide a slave-select signal output to enable the spi slave devices. you can implement this by using one of the mpc823e general-purpose i/o pins. the spisel pin must not be asserted while the serial peripheral interface is in master mode or an error will occur. when the serial peripheral interface is in slave mode, spiclk is the clock input signal that shifts in the received data from the spimosi pin and shifts out the transmitted data to the spimiso pin. the spisel pin provided by the mpc823e is the enable input to the spi slave. when the serial peripheral interface is operating in a multimaster environment, the spisel pin is still an input and is used to detect an error condition when more than one master is operating. using the fields in the spi mode register, you can select any of the four combinations of the gated spiclk phase and polarity. the spi pins can also be configured as open-drain pins to support a multimaster configuration in which the same spi pin is driven by the mpc823e or an external spi device.
communication processor module 16-436 mpc823e reference manual motorola spi communication 16 processor module 16.12.3 the spi transmission and reception process when the serial peripheral interface is in master mode, it transmits a message to the peripheral or slave, which sends back an immediate reply. when the mpc823e has more than one slave, it can use the general-purpose parallel i/o pins to selectively enable different slaves. to start the data exchange process, the core writes the data to be transmitted into a data buffer, configures a transmit (tx) buffer descriptor with its r bit set, and configures one or more receive (rx) buffer descriptors. the core then sets the str bit in the spcom register to start transmitting data, which starts when the sdma channel loads the transmit fifo with data. the serial peripheral interface then generates programmable clock pulses on the spiclk pin for each character and shifts the data out on the spimosi pin. at the same time, the serial peripheral interface shifts received data in from the spimiso pin. this received data is written into a receive buffer using the next available rx buffer descriptor. the serial peripheral interface continues transmitting and receiving characters until the transmit buffer has been completely transmitted or an error has occurred. the communication processor module then clears the r and e bits in the tx and rx buffer descriptors and may issue a maskable interrupt to the cpm interrupt controller. when multiple tx buffer descriptors are ready to be transmitted, the l bit in the tx buffer descriptor determines whether or not the serial peripheral interface must continue transmitting without waiting for the str bit to be set again. if the l bit is cleared, the data from the next tx buffer descriptor begins transmitting after data from the first tx buffer descriptor is transmitted. if the l bit is set, transmission stops after data from this tx buffer descriptor has finished transmitting. in addition, the current rx buffer descriptor that is used to receive data is closed after transmission stops, even if the receive buffer is not full. this means that you do not need to provide receive buffers that are the same length as the transmit buffers. if the serial peripheral interface is the only master in a system, then the spisel pin can be used as a general-purpose i/o, and the internal spisel signal to the serial peripheral interface is always forced internally inactive, thus eliminating the possibility of a multimaster error. when the serial peripheral interface is in slave mode, it receives messages from an spi master and sends back an immediate reply. the spisel pin must be asserted before receive clocks are recognized and once spisel is asserted, the spiclk pin becomes an input from the master to the slave. spiclk can be any frequency from the dc to the brgclk/2, which is 12.5mhz for a 25mhz system. before the data is exchanged, the core writes the data to be transmitted into a data buffer, configures a tx buffer descriptor with its r bit set, and configures one or more rx buffer descriptors. the core then sets the str bit in the spcom register to enable the serial peripheral interface so it will prepare the data for transmission and wait for the spisel pin to be asserted. data is shifted out from the slave on the spimiso pin and shifted in through the spimosi pin. a maskable interrupt is issued when a full buffer finishes receiving and transmitting or after an error occurs. using the next rx buffer descriptor in the ring, the serial peripheral interface continues reception until it runs out of receive buffers or the spisel pin is negated.
communication processor module motorola mpc823e reference manual 16-437 spi communication 16 processor module transmission continues until no more data is available or the spisel pin is negated. if the pin is negated before all the data is transmitted, it stops, but the tx buffer descriptor stays open. further transmission continues once the spisel pin is reasserted and spiclk begins toggling. after the characters in the tx buffer descriptor are transmitted, the serial peripheral interface transmits ones if spisel is not negated. 16.12.3.1 multimaster operation. the serial peripheral interface can operate in a multimaster environment in which more than one spi device is connected to the same bus. in this configuration, the spimosi, spimiso, and spiclk pins of all spis are connected together and the spisel input pins are connected separately. in this environment, only one spi device can be in master mode and all the others must be in slave mode. when the serial peripheral interface is configured as a master and its spisel signal goes active or low, a multimaster error will occur because more than one spi device is a bus master. the serial peripheral interface sets the mme bit in the spie register and a maskable interrupt is issued to the core. it also disables spi operation and the output drivers of the spi pins. the core must clear the en bit the spmode register before using the serial peripheral interface again. after the problems are corrected, clear the mme bit and enable the serial peripheral interface the same way you would after a reset. note: the maximum sustained data rate that the serial peripheral interface supports is systemclk/50. however, the serial peripheral interface can transfer a single character at much higher rates. for instance, systemclk/4 in master mode and systemclk/2 in slave mode. if multiple characters are to be transmitted, you must insert gaps between them so that it will not exceed the maximum sustained data rate.
communication processor module 16-438 mpc823e reference manual motorola spi communication 16 processor module 16.12.3.2 spi parameter ram memory map. the spi parameter ram area begins at the spi base address and is used for the general spi parameters. notice that it is similar to the sccx general-purpose parameter ram. you must initialize certain parameter ram values before the serial peripheral interface is enabled. the communication processor module initilizes the other values. once initialized, the parameter ram values do not usually need to be accessed by your software. they only need to be modified when there is no serial peripheral interface activity in progress. ? rbase and tbasethe dual-port ram starts receiving and transmitting data for the rx and tx buffer descriptors in the rbase and tbase entries. they provide a great deal of flexibility for partitioning buffer descriptors for a serial peripheral interface. you must initialize these entries before enabling the corresponding channel. you must not configure the spi buffer descriptor tables to overlap with the tables of the usb, smcx, and sccx or erratic operation will occur. rbase and tbase must contain a value that is divisible by eight. table 16-39. spi parameter ram memory map address name width description spi base + 00 rbase half-word rx buffer descriptor base address spi base+ 02 tbase half-word tx buffer descriptor base address spi base+ 04 rfcr byte rx function code spi base+ 05 tfcr byte tx function code spi base+ 06 mrblr half-word maximum receive buffer length spi base+ 08 rstate word rx internal state spi base+ 0c rptr word rx internal data pointer spi base + 10 rbptr half-word rx buffer descriptor pointer spi base + 12 rcnt half-word rx internal byte count spi base + 14 rtmp word rx temp spi base + 18 tstate word tx internal state spi base + 1c tptr word tx internal data pointer spi base + 20 tbptr half-word tx buffer descriptor pointer spi base + 22 tcnt half-word tx internal byte count spi base + 24 ttmp word tx temp note: you are only responsible for initializing the items in bold. spi base = (immr & 0xffff0000) + 0x3d80. sccx ethernet parameter ram space overlaps the spi parameter ram space. the address range for sccx space is 0x1000 through 0x1ca3. you need a microcode patch to run spi and ethernet concurrently.
communication processor module motorola mpc823e reference manual 16-439 spi communication 16 processor module ? rfcr and tfcrthe receive and transmit function code register entries contain the value that you want to appear on the at pins when the associated sdma channel accesses memory. this register controls the byte-ordering convention used in the transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set these bits to select the required byte ordering of the data buffer. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type 1C3 these bits contain the function code value used during the sdma channel memory access. at0 is driven with a 1 to identify this sdma channel access as a dma-type access. rfcr bit 0 1 2 3 4 5 6 7 field reserved bo at reset 000 r/w r/w r/w r/w addr spi base + 0x04 tfcr bit 0 1 2 3 4 5 6 7 field reserved bo at reset 000 r/w r/w r/w r/w addr spi base + 0x05
communication processor module 16-440 mpc823e reference manual motorola spi communication 16 processor module bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set these bits to select the required byte ordering of the data buffer. if this bit field is modified on-the-fly, it takes effect at the beginning of the next frame or at the beginning of the next buffer descriptor. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type 1C3 these bits contain the function code value used during the sdma channel memory access. at0 is driven with a 1 to identify this sdma channel access as a dma-type access. ? mrblrthe serial peripheral interface has one maximum receive buffer length entry to define its receive buffer length and it defines the maximum number of bytes that the mpc823e writes to a receive buffer on the serial peripheral interface before moving to the next buffer. the mpc823e can write fewer bytes to the buffer than the mrblr value if an error or end-of-frame occurs, but it never writes more bytes than the mrblr value. buffers you supply for the mpc823e to use must always be at least as long as mrblr. the transmit buffers for a serial peripheral interface are not affected by the value you program into mrblr and they can have different lengths, as needed. you can choose the number of bytes to be transmitted by programming the data length field in the tx buffer descriptor. note: the mrblr is not intended to be dynamically changed while a serial management controller is operating. however, if it is modified in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back), then a dynamic change in the receive buffer length can be successfully achieved. this occurs when the communication processor module transfers control to the next rx buffer descriptor in the table. thus, a change to mrblr does not have an immediate effect. to guarantee that the change occurs on a particular rx buffer descriptor, you must only change the mrblr while the smcx receiver is disabled. the value of mrblr must be greater than zero and it must be even if the character length of the data is greater than 8 bits.
communication processor module motorola mpc823e reference manual 16-441 spi communication 16 processor module ? rrbptrthe rx buffer descriptor pointer entry for each spi channel points to the next buffer descriptor that the receiver transfers data to when it is idle or to the current buffer descriptor during frame processing. after a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the rbase entry. although in most applications you must not write rbptr, it can be modified when the receiver is disabled or when you are sure that no receive buffer is currently in use. ? tbptrthe tx buffer descriptor pointer entry for each spi channel points to the next buffer descriptor that the transmitter transfers data from when it is idle or to the current buffer descriptor during frame transmission. after a reset or when the end of buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the tbase entry. although in most applications you must not write tbptr, it can be modified when the transmitter is disabled or when you are sure that no transmit buffer is currently in use. ? other general parametersfor normal operation, you do not need to access these parameters. they are only listed here because they provide helpful information for debugging purposes. additional parameters are listed in table 16-39. rptr and tptr are updated by the sdma channels to show the next address in the buffer to be accessed. tcnt is a down-count value initialized with the data length field of the tx buffer descriptor and decremented with every byte read by the sdma channels. the rcnt is a down-count value that is initialized with the mrblr value and decremented with every byte the sdma channels write. the rstate, tstate, rtmp, tmp, and reserved areas can only be used by the risc microcontroller. 16.12.3.3 spi commands. the following transmit and receive commands are issued to the cpm command register (cpcr). ? init tx parameters this command initializes all transmit parameters in the serial channel parameter ram to their reset state and must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. ? close rx bd this command is used to force the spi controller to close the current rx buffer descriptor if it is currently being used and to use the next buffer descriptor for any subsequently received data. if the spi controller is not in the process of receiving data, no action is taken by this command. ? init rx parameters this command initializes all the receive parameters in this serial channel parameter ram to their reset state and must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters. note: to extract data from a partially full buffer, issue the close rx bd command.
communication processor module 16-442 mpc823e reference manual motorola spi communication 16 processor module 16.12.3.4 spi buffer descriptor ring. the data associated with the serial peripheral interface is stored in buffers, which are referenced by buffer descriptors organized in a buffer descriptor ring located in the dual-port ram. this ring has the same basic configuration as the sccx, smcx, usb, and i 2 c controllers. the buffer descriptor ring forms a circular queue that helps you organize the buffers you want to transmit or receive. using the buffer descriptors, the communication processor module confirms reception and transmission or indicates error conditions so that the processor knows the buffers have been serviced. the actual buffers can reside in either external or internal memory and the data buffers can reside in the parameter area of another unused controller if it is not enabled. figure 16-123. spi memory format frame status data length data pointer pointer to spi tx ring dual-port ram external memory tx bd ring tx data buffer pointer to spi rx ring rx bd ring rx data buffer tx data buffer frame status data length data pointer
communication processor module motorola mpc823e reference manual 16-443 spi communication 16 processor module 16.12.4 programming the serial peripheral interface 16.12.4.1 spi mode register. the read/write spi mode (spmode) register controls both the serial peripheral interface operation mode and clock source. table 16-2 contains more information on commands that can be used with this register. bit 0reserved this bit is reserved and must be set to 0. looploop mode when set, this bit selects the local loopback operation. the transmitter output is internally connected to the receiver input. the receiver and transmitter operate normally, except that the externally received data is ignored. 0 = normal operation. 1 = the serial peripheral interface is in loopback mode. ciclock invert this bit inverts the spi clock polarity. see figure 16-124 and figure 16-125 for details. 0 = the inactive state of spiclk is low. 1 = the inactive state of spiclk is high. cpclock phase this bit selects one of two fundamentally different transfer formats. see figure 16-124 and figure 16-125 for details. 0 = spiclk starts toggling at the middle of the data transfer. 1 = spiclk starts toggling at the beginning of the data transfer. div16divide by 16 this bit selects the clock source for the spi baud rate generator when configured as an spi master. in slave mode, the clock source is the spiclk pin. 0 = use the brgclk as the input to the spi baud rate generator. 1 = use the brgclk/16 as the input to the spi baud rate generator. spmode bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res loop ci cp div16 rev m/s en len pm reset 00000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xaa0
communication processor module 16-444 mpc823e reference manual motorola spi communication 16 processor module revreverse data this bit determines the receive and transmit character bit order. 0 = reverse data. least-significant bit of the character transmitted and received first. 1 = normal operation. most-significant bit of the character transmitted and received first. m/smaster/slave this bit configures the serial peripheral interface to operate as a master or slave. 0 = the serial peripheral interface is a slave. 1 = the serial peripheral interface is a master. enenable spi this bit enables serial peripheral interface operation. configure the spimosi, spimiso, spiclk, and spisel pins to connect to the serial peripheral interface, as described in section 16.14.6 the port b registers . when the en bit is cleared, the serial peripheral interface is in a reset state and consumes minimal power, which means the spi baud rate generator is not functioning and the input clock is disabled. 0 = the serial peripheral interface is disabled. 1 = the serial peripheral interface is enabled. lencharacter length this field specifies the number of bits in a character. these values must be between 4 and 16 bits. if you program a value less than 4 bits, erratic behavior will occur. if the value of len is less than or equal to a byte, there will be len number of valid bits in every byte (8 bits) in memory. on the other hand, if the value of len is greater than a byte, there is len number of valid bits in every half-word (16 bits) in memory. 0011 = 4-bit character length. 0100 = 5-bit character length. 0101 = 6-bit character length. 0110 = 7-bit character length. 0111 = 8-bit character length. ? ? ? 1111 = 16-bit character length. note: you must not modify other bits of the spmode register when the en bit is set.
communication processor module motorola mpc823e reference manual 16-445 spi communication 16 processor module pmprescale modulus select this field specifies the divide ratio of the prescale divider in the spi clock generator. the brgclk is divided by 4 * ([pm0Cpm3] + 1), thus giving a clock divide ratio of 4 to 64. the clock has a 50% duty cycle. 16.12.4.1.1 spi examples with different len values. the programming examples below illustrate the effect of the len field and the rev bit in the spmode register on output from the spi controller. they illustrate the master mode output from the spi controller as the len varies. to help map the output process, make g through v the binary symbols, use x to indicate a deleted bit, use __ to indicate original byte boundaries, and use _ to indicate original nibble (4-bit) boundaries. the initial pattern for all examples is ghij_klmn__opqr_stuv . example 1 len = 0x4 (data size = 5) data selected: xxxj_klmn_xxxr_stuv data transmitted for rev=0: nmlk_j__vuts_r data transmitted for rev=1: j_nmlk__r_stuv example 2 len = 0x7 (data size = 8) data selected: ghij_klmn_opqr_stuv data transmitted for rev=0: nmlk_jihg__vuts_rqpo data transmitted for rev=1: ghij_klmn__opqr_stuv example 3 len = 0xc (data size = 13) data selected: ghij_klmn_xxxr_stuv data transmitted for rev=0: nmlk_jihg__vuts_r data transmitted for rev=1: r_stuv__ghij_klmn example 4 len = 0xf (data size = 16) data selected: ghij_klmn_opqr_stuv data transmitted for rev=0: nmlk_jihg__vuts_rqpo data transmitted for rev=1: opqr_stuv__ghij_klmn
communication processor module 16-446 mpc823e reference manual motorola spi communication 16 processor module figure 16-124. spi transfer format if cp is set to 0 figure 16-125. spi transfer format if cp is set to 1 spiclk (ci = 0) spiclk (ci = 1) spimosi (from master) spimiso (from slave) spisel msb lsb msb lsb q note: q = undefined signal spiclk (ci = 0) spiclk (ci = 1) spimosi (from master) spimiso (from slave) spisel msb msb lsb lsb q note: q = undefined signal
communication processor module motorola mpc823e reference manual 16-447 spi communication 16 processor module 16.12.4.1.2 spi receive buffer descriptor. using receive (rx) buffer descriptors, the communication processor module reports information about each buffer of received data, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer once the current buffer is full. additionally, it closes the buffer when the serial peripheral interface is configured as a slave and the spisel pin goes inactive, thus indicating that the reception process has stopped. the first word of the rx buffer descriptor contains status and control bits that you prepare before reception and then the communication processor module sets them after the buffer is closed. the second word contains the data length (in bytes) that is received and the third and fourth words contain a pointer that always points to the beginning of the received data buffer. you must configure the rx buffer descriptor bits before the serial peripheral interface is enabled. eempty 0 = the data buffer associated with this rx buffer descriptor is filled with data or stops receiving data because an error occurred. the core is free to examine or write to any fields of this rx buffer descriptor, but the communication processor module does not use this buffer descriptor as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or is currently receiving data. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bit 1, 5, and 7C13reserved these bits are reserved and must be set to 0. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi l res cm reserved ov me offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-448 mpc823e reference manual motorola spi communication 16 processor module wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 no interrupt is generated after this buffer is filled. 1 the rxb bit in the spie register is set when this buffer is completely filled by the communication processor module, indicating the need for the core to process the buffer. the rxb bit can cause an interrupt if it is enabled. cmcontinuous mode this bit is valid only when the serial peripheral interface is in master mode. in slave mode, it must be written as a zero. 0 = normal operation. 1 = the e bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically overwritten next time the communication processor module accesses this buffer descriptor. this allows continuous reception from an spi slave into one buffer for autoscanning of a serial a/d peripheral with no core overhead. llast this bit is set by the serial peripheral interface when the buffer is closed because the spisel pin was negated. this only occurs when the serial peripheral interface is in slave mode. otherwise, the me bit is set. the serial peripheral interface writes this bit after the received data is placed into the associated data buffer. 0 = this buffer does not contain the last character of the message. 1 = this buffer contains the last character of the message. ovoverrun this bit indicates that a receiver overrun has occurred during reception. this can only occur when the serial peripheral interface is in slave mode. the serial peripheral interface writes this bit after the received data is placed into the associated data buffer. memultimaster error this bit indicates that this buffer is closed because the spisel pin was asserted when the serial peripheral interface was in master mode. this indicates a synchronization problem between multiple masters on the spi bus. the serial peripheral interface writes this bit after the received data is placed into the associated data buffer.
communication processor module motorola mpc823e reference manual 16-449 spi communication 16 processor module data length this field represents the number of octets that the communication processor module writes into this buffer descriptor data buffer. the communication processor module writes it once as the buffer descriptor is closed. the serial peripheral interface writes these bits after the received data is placed into the associated data buffer. the actual amount of memory allocated for this buffer must be greater than or equal to the mrblr entry. rx data buffer pointer this field always points to the first location of the associated data buffer. it must be even and it can reside in internal or external memory. the serial peripheral interface writes these bits after the received data is placed into the associated data buffer. 16.12.4.1.3 spi transmit buffer descriptor. data to be transmitted by the serial peripheral interface is sent to the communication processor module by arranging it in buffers referenced by the transmit (tx) buffer descriptor ring. the first word of the tx buffer descriptor contains status and control bits. you must prepare the following bits before transmitting data. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission and you are free to manipulate it or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error occurs. 1 = the data buffer, which you prepare for transmission, is not transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1, 5, and 7C13reserved these bits are reserved and must be set to 0. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi l res cm reserved un me offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-450 mpc823e reference manual motorola spi communication 16 processor module wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the txb or txe bit in the spi event register is set when this buffer is serviced. txb and txe can cause interrupts if they are enabled. llast 0 = this buffer does not contain the last character of the message. 1 = this buffer contains the last character of the message. cmcontinuous mode this bit is only valid when the serial peripheral interface is in master mode. in slave mode, it must be written as a zero. 0 = normal operation. 1 = the r bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor. ununderrun this bit indicates that the serial peripheral interface has encountered a transmitter underrun condition while transmitting a data buffer. this error condition is only valid when the serial peripheral interface is in slave mode. the serial peripheral interface writes this bit after it finishes transmitting the associated data buffer. memultimaster error this bit indicates that this buffer is closed because the spisel pin was asserted when the serial peripheral interface was in master mode. this indicates a synchronization problem between multiple masters on the spi bus. the serial peripheral interface writes this bit after it finishes transmitting the associated data buffer.
communication processor module motorola mpc823e reference manual 16-451 spi communication 16 processor module data length this field indicates the number of octets that the communication processor module must transmit from this buffer descriptor data buffer. however, it is never modified by the communication processor module. normally, this value is greater than zero, but if the number of data bits in the character is greater than 8, then data length must be even. for example, to transmit three characters of 8-bit data, the data length field must be initialized to 3. however, to transmit three characters of 9-bit data the data length field must be initialized to 6, since the three 9-bit data fields occupy three half-words in memory. the serial peripheral interface writes these bits after it finishes transmitting the associated data buffer. tx data buffer pointer this field always points to the first location of the associated data buffer. they can be even or odd, unless the number of actual data bits in the character is greater than 8 bits, in which case the transmit buffer pointer must be even. the buffer can reside in internal or external memory. the serial peripheral interface writes these bits after it finishes transmitting the associated data buffer. 16.12.4.2 spi command register. the 8-bit read/write spi command (spcom) register is used to start serial peripheral interface operation. strstart transmit when the serial peripheral interface is configured as a master, setting this bit to 1 causes the serial peripheral interface to start transmitting and receiving data to and from the transmit/receive buffers if they are ready. when the serial peripheral interface is in slave mode, setting the str bit to 1 when the serial peripheral interface is idle causes the serial peripheral interface to load the transmit data register from the spi transmit buffer and start transmission as soon as the next spi input clocks and select signal are received. this bit is automatically cleared after one system clock cycle. bits 1C7reserved. these bits are reserved and must be set to 0. spcom bit 0 1 2 3 4 5 6 7 field str reserved reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0xaad
communication processor module 16-452 mpc823e reference manual motorola spi communication 16 processor module 16.12.4.3 spi event register. the 8-bit memory-mapped spi event (spie) register is used to generate interrupts and report events recognized by the serial peripheral interface. when an event is recognized, the serial peripheral interface sets the corresponding bit in this register. interrupts generated by this register can be masked in the spim register. a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. however, all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared by reset and can be read at any time. bits 0C1 and 4reserved these bits are reserved and must be set to 0. mmemulti-master error this bit indicates that the serial peripheral interface has discovered that the spisel pin was asserted externally while the serial peripheral interface was in master mode. txetx error this bit indicates that an error has occurred during transmission. bsybusy condition this bit indicates that received data has been discarded due to a lack of buffers. this bit is set after the first character is received for which there is no receive buffer. txbtx buffer this bit indicates that a buffer has been transmitted. it is set once the transmit data of the last character in the buffer is written to the transmit fifo. you must wait two character times to be sure that the data is completely sent over the transmit pin. rxbrx buffer this bit indicates that a buffer has been received. it set after the last character is written to the receive buffer and the rx buffer descriptor is closed. spie bit 0 1 2 3 4 5 6 7 field reserved mme txe res bsy txb rxb reset 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xaa6
communication processor module motorola mpc823e reference manual 16-453 spi communication 16 processor module 16.12.4.4 spi mask register. the 8-bit read/write spi mask (spim) register has the same bit formats as the spie register. if a bit in the spim is 1, the corresponding interrupt in the spie register is enabled. if the bit is zero, the corresponding interrupt in the spie register is masked. this register is cleared by reset. 16.12.5 spi master programming example the following is an example initialization sequence using the serial peripheral interface in master mode at high speed. 1. configure the port b pins to enable the spimosi, spimiso, and spiclk pins. write pbpar and pbdir bits 30, 29, and 28 with ones and then pbodr bits 30, 29, and 28 with zeros. 2. configure a parallel i/o pin to operate as the serial peripheral interface select pin if needed. if pb16 is chosen, write pbodr bit 16 with a zero, pbdir bit 16 with a one, and pbpar bit 16 with a zero. then write pbdat bit 16 with a zero to constantly assert the select pin. 3. write rbase and tbase in the spi parameter ram to point to the rx buffer descriptor and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor is at the beginning of the dual-port ram and one tx buffer descriptor follows that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 4. program the cpm command register (cpcr) to execute the init rx and tx params command. write 0x0051 to the cpcr. 5. write 0x0001 to the sdcr to initialize the sdma configuration register. 6. write 0x18 to rfcr and tfcr for normal operation. 7. write mrblr with the maximum number of bytes per receive buffer. in this case, assume 16 bytes, so mrblr = 0x0010. 8. initialize the rx buffer descriptor and assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. spim bit 0 1 2 3 4 5 6 7 field reserved mime txe res bsy txb rxb reset 0 000000 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xaaa note: for multimaster operation, enable the spisel pin to internally connect to the serial peripheral interface.
communication processor module 16-454 mpc823e reference manual motorola spi communication 16 processor module 9. initialize the tx buffer descriptor and assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xb800 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. 10. write 0xff to the spie register to clear any previous events. 11. write 0x37 to the spim register to enable all possible serial peripheral interface interrupts. 12. write 0x00000020 to the cimr to allow the serial peripheral interface to generate a system interrupt. the cicr must also be initialized. 13. write 0x0370 to the spmode register to enable normal operation (not loopback), master mode, serial peripheral interface enabled, 8-bit characters, and the fastest speed possible. 14. set the str bit in the spcom register to start the transfer. 16.12.6 spi slave programming example the following is an example initialization sequence to follow when the serial peripheral interface is in slave mode. it is very similar to the master example, except that the spisel pin is used instead of a general-purpose i/o pin. 1. configure the port b pins to enable the spimosi, spimiso, spisel , and spiclk pins. write pbpar bits 31, 30, 29, and 28 with ones and the pbodr bits 31, 30, 29, and 28 with zeros. write pbdir bits 30, 29, and 28 with ones and bit 31 with zero. 2. write rbase and tbase in the spi parameter ram to point to the rx and tx buffer descriptor in the dual-port ram. assuming one rx buffer descriptor at the beginning of the dual-port ram and one tx buffer descriptor following that rx buffer descriptor, write rbase with 0x2000 and tbase with 0x2008. 3. write 0x18 to rfcr and tfcr for normal operation. 4. program the cpm command register (cpcr) to execute the init rx and tx params command. write 0x0051 to the cpcr. 5. write 0x0001 to the sdcr to initialize the sdma configuration register. 6. write mrblr with the maximum number of bytes per receive buffer. assume 16 bytes, so mrblr = 0x0010. 7. initialize the rx buffer descriptor and assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0000 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. 8. initialize the tx buffer descriptor and assume the tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters. write 0xb800 to tx_bd_status, 0x0005 to tx_bd_length, and 0x00002000 to tx_bd_pointer. note: after 5 bytes are transmitted, the tx buffer descriptor is closed. additionally, the receive buffer is closed after 5 bytes are received because the l bit of the tx buffer descriptor is set.
communication processor module motorola mpc823e reference manual 16-455 spi communication 16 processor module 9. write 0xff to the spie register to clear any previous events. 10. write 0x37 to the spim register to enable all possible serial peripheral interface interrupts. 11. write 0x00000020 to the cimr to allow the serial peripheral interface to generate a system interrupt. the cicr must also be initialized. 12. write 0x0170 to the spmode register to enable normal operation (not loopback), master mode, and 8-bit characters. the spi baud rate generator speed is ignored because the serial peripheral interface is in slave mode. 13. set the str bit in the spcom register to enable the serial peripheral interface to be ready once the master begins the transfer. 16.12.7 handling interrupts in the spi the following sequence must be followed to handle interrupts in the serial peripheral interface. 1. once an interrupt occurs, read the spie register to discover the cause of the interrupts. normally, the spie bits must be cleared at this time. 2. process the tx buffer descriptor to reuse it and the rx buffer descriptor to extract the data from it. to transmit another buffer, simply set the r bit of the tx buffer descriptor, the e bit of the rx buffer descriptor, and the str bit of the spcom register. 3. clear the spi bit in the cisr. 4. execute the rfi instruction. note: if the master transmits 3 bytes and negates the spisel pin, the rx buffer descriptor is closed, but the tx buffer descriptor remains open. if the master transmits 5 or more bytes, the tx buffer descriptor is closed after the fifth byte. if the master transmits 16 bytes and negates the spisel pin, the rx buffer descriptor is closed with no errors and no out-of-buffer error occurs. if the master transmits more than 16 bytes, the rx buffer descriptor is closed (completely full) and the out-of-buffer error occurs after the 17th byte is received.
communication processor module 16-456 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13 the i 2 c controller the inter-integrated circuits (i 2 c ? ) controller enables the mpc823e to exchange data with a number of other i 2 c devices, such as microcontrollers, eeproms, real-time clock devices, a/d converters, and lcd displays. the i 2 c controller is a synchronous, multimaster bus that is used to connect several integrated circuits on a board. it uses two wiresserial data (sda) and serial clock (scl)to carry information between the integrated circuits that are connected to it. the i 2 c controller consists of transmitter and receiver sections, an independent baud rate generator, and a control unit. the transmitter and receiver sections use the same clock, that is derived from the i 2 c baud rate generator in master mode and generated externally in slave mode. according to the i 2 c specification, wait states are inserted during a data transfer if the scl signal is held low by a slave device. as a master in the middle of a data transfer, the i 2 c controller recognizes wait states by monitoring the scl signal. the i 2 c controller does not begin counting down from a specific timeout value when scl is asserted, so the software must monitor scl assertion times for bus timeout. the i 2 c receiver and transmitter are double-buffered, which corresponds to an effective fifo size of 2 characters. the mpc823e i 2 c bit 0 (msb) is shifted out first. when the i 2 c is not enabled in the i2mod register, it consumes very little power. figure 16-126. i 2 c controller block diagram shift register tx data register shift register rx data register mode register brg control peripheral bus u-bus sda scl
communication processor module motorola mpc823e reference manual 16-457 i 2 c communication 16 processor module 16.13.1 features the following is a list of the i 2 c controllers main features: ? two-pin interface ? full-duplex operation ? master or slave i 2 c mode support ? multimaster environment support ? continuous transfer mode for autoscanning peripherals ? supports maximum capacitive load of 400 p f on both bus lines (fully i 2 c-compliant) ? independent programmable baud rate generator ? supports i 2 c low- and high-speed operation ? supports 7-bit i 2 c addressing ? open-drain output pins support multimaster configuration ? local loopback capability for testing 16.13.2 i 2 c controller clocking and pin functions both serial data (sda) and serial clock (scl) are bidirectional pins that must be connected to a positive 5v power supply via an external pull-up resistor in the 6.8k ohm to 10k ohm range. both pins are high when the i 2 c bus is free. the scl signal clocks in received data and clocks out transmitted data on the sda pin. the i 2 c controller can be configured as a master or slave. when configured as a master, the i 2 c controller generates scl, and then initiates and terminates the i/o operation. in addition, the i 2 c controller generates the scl signal via a dedicated baud rate generator that takes its input from brgclk, which is described in section 5.3.4.2 the baud rate generator clock . when configured as a slave, the i 2 c controller receives scl as an input. an i 2 c transaction is initiated when the master generates a start condition, which is defined as the sda signal making a high-to-low transition while scl is high. an acknowledge (ack) is generated by the i 2 c receiver after each byte transfer. the receiver signals an ack by driving the sda signal low during the scl clock pulse immediately following each data byte transmission. the data and ack signals are always sampled on the rising edge of scl. if the receiver does not issue an ack after a data byte is transmitted, the i 2 c master generates a stop condition and transmission stops. a stop condition is when the sda signal makes a low to high transition while the scl signal remains high, as illustrated in figure 16-127.
communication processor module 16-458 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13.3 i 2 c controller transmission and reception process 16.13.3.1 i 2 c master mode. when the i 2 c controller is in master mode, it initiates a transaction by transmitting a message specifying a read or write operation to the i 2 c slave. if a read operation is specified, the direction of the transfer is changed after the read operation is acknowledged, and the slave device then becomes the transmitter. if a write operation is specified, the direction of the transfer remains unchanged. as the i 2 c controller shifts out each bit, it monitors the level of the sda pin to detect a possible collision with other i 2 c master transmitters. if a collision is detected, transmission stops and the controller reverts to slave mode. a maskable interrupt may be issued to the core to allow the software to retransmit later. in master mode operation, setting the s bit in the tx buffer descriptor will cause a start condition to be sent before this buffer is transmitted. if the tx buffer descriptor is the first one in the ring, then a start condition will be issued, regardless of the s bit setting. setting the l bit will cause a stop condition to be sent after the buffer is transmitted. you must set the l bit for the last tx buffer in the ring. you must set the m/s bit in the i2com register to configure the controller as a master. clear the i2cmod registers en bit to disable the i 2 c controller before programming the scl clock frequency for the i2mod and i2brg registers. the i2add register does not need to be programmed when you are operating the i 2 c controller in single-master mode. enable the i 2 c controller by setting the en bit in the i2mod register. figure 16-127. i 2 c timing scl sda data byte start condition stop condition a c k
communication processor module motorola mpc823e reference manual 16-459 i 2 c communication 16 processor module 16.13.3.1.1 master write. to begin a write operation to a slave device that contains internal addresses, you must prepare a tx data buffer that is n+2 bytes in length. the first byte contains the 7-bit device address followed by the write bit asserted (r/w = 0). the second byte contains the internal base address of the write. the remaining n bytes contain the data to be written to the slave. the slave device will process the n bytes of data sequentially, starting at the specified base address. to begin a master write operation to a slave device that does not contain internal addresses, you must prepare a tx data buffer that is n+1 bytes long. the first byte contains the 7-bit slave device address followed by the write bit asserted (r/w = 0). the remaining n bytes contain the data to be written to the slave. next, when communicating to either slave device, the w and l bits must be set in the tx buffer descriptor. set the i bit in the tx buffer descriptor to enable the transmission status to be updated in the i2ce register and to enable i 2 c interrupts to the core. set the r bit in the tx buffer descriptor to prepare the buffer for transmission. the final step is to set the str bit in the i2com register to initiate transmission. the data starts transmitting once the sdma channel loads the transmit fifo with data and the i 2 c bus is not busy. figure 16-128. byte write to device with internal addresses figure 16-129. byte write to device without internal addresses note: some slave devices, such as serial e2proms, may have a minimum write cycle time. for these devices, the i 2 c controller must wait a minimum amount of time after a write before initiating the next read or write. the required delay must be implemented in software. sda device addr w base addr data byte a c k a c k a c k s t a r t s t o p note: data and ack are repeated n times. sda device addr w data byte s t a r t s t o p a c k a c k note: data and ack are repeated n times.
communication processor module 16-460 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13.3.1.2 master read. to begin a read operation to a slave device that contains internal addresses, you must prepare two tx buffers. tx buffer 0 must be 2 bytes long and tx buffer 1 must be n+1 bytes long, where n is the number of bytes to be read sequentially from the slave device. you must also prepare one or more receive buffers for the n bytes of data to receive from the slave device. the first byte of tx buffer 0 must contain the 7-bit slave address followed by the write bit asserted (r/w = 0). the second byte of the first transmit buffer must contain the 1-byte internal address on the slave device. this is the base address on the slave device of the data to be read. the transmission of tx buffer 0 is commonly referred to as a dummy write. its purpose is to select the slave device. the first byte of the second tx buffer (1) must contain the slave address followed by the read bit asserted (r/w = 1). the remaining n bytes of tx buffer 1 may be uninitialized and merely serve as a placeholder for the i 2 c controller. the w, l and s bits must be set in the tx buffer descriptor. to begin a read operation to a slave device that does not contain internal addresses, you must prepare a tx buffer of n+1 bytes long, where n is the number of bytes to be read sequentially from the slave device. the first byte of the tx buffer must contain the 7-bit slave address followed by the read bit asserted (r/w = 1). you must also prepare one or more receive buffers for the n bytes of data to receive from the slave device. figure 16-130. byte read from device with internal addresses figure 16-131. byte read from device without internal addresses sda device addr w base addr data byte device addr r a c k a c k a c k s t a r t s t a r t s t o p n o a c k note: data and ack are repeated n times. sda data byte device addr r s t o p s t a r t n o a c k a c k note: data and ack are repeated n times.
communication processor module motorola mpc823e reference manual 16-461 i 2 c communication 16 processor module when communicating to either slave device, set the r bit in the tx buffer descriptor to prepare it for transmission. set the i bit in the tx and rx buffer descriptors to enable the transmission and reception status to be updated in the i2ce register and to enable i 2 c interrupts to the core. set the e bit on the rx buffer descriptor to prepare it for reception. finally, set the str bit in the i2com register to initiate transmission. the data starts transmitting once the sdma channel loads the transmit fifo with data and the i 2 c bus is not busy. 16.13.3.1.3 i 2 c loopback configuration. loopback on the i 2 c controller is a special part of master mode operation with a device that does not contain internal addresses. refer to figure 16-129 for more information. to begin a loopback transmission, you must prepare a tx buffer descriptor with a data buffer n+1 bytes long, where n is the number of data bytes to be written back to the i 2 c controller. you must also prepare one or more rx buffer descriptors to receive the n bytes of data. the first byte of the tx buffer descriptor must contain the address of the mpc823e i 2 c devices own address, which is in the i2cadd register, followed by the write bit asserted (r/ w = 0). the remaining n bytes of the tx buffer descriptor contain the data to be sent and received by the i 2 c controller. next, set the r bit in the tx buffer descriptor and the e bit in the rx buffer descriptor. then set the w and l bits in the tx buffer descriptor. setting the l bit causes a stop condition to be issued after this buffer is transmitted to conclude the operation. set the i bit in the tx and rx buffer descriptors to enable the transmission and reception status to be updated in the i2ce register and to enable i 2 c transmit and receive interrupts to the core. you must then set the str bit in the i2com register to initiate the loopback operation. 16.13.3.2 i 2 c slave mode. when the i 2 c controller is in slave mode, it receives messages from an i 2 c master and sends back a reply. once the i 2 c controller is configured for slave mode operation (by clearing the m/s bit in the i2com register), the scl signal becomes an input driven by the external master. the i 2 c controller can operate with an scl of any frequency from dc to 400khz or more. after the start condition, the first transmitted byte to the i 2 c slave device contains the 7-bit slave device address and the read/write bit. the i 2 c controller will compare the transmitted slave device address with its own programmed address. if there is a match, the read/write bit is evaluated. you must the clear the m/s bit in the i2com register to configure the controller as a slave. you do not program the i2mod and i2brg registers to set the scl frequency, as scl is an input to the slave. instead, program the i2add register with the 7-bit i 2 c address of the slave. enable the i 2 c controller by setting the en bit in the i2mod register.
communication processor module 16-462 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13.3.2.1 write to master. if an external master requests a write operation, the i 2 c controller acknowledges the received data and writes it into a receive buffer using the next available rx buffer descriptor until the next start or stop condition is detected. after transmitting each data byte, the master checks for the acknowledge bit from the slave. if an overrun condition occurs on the slave receiver, it will fail to acknowledge a byte and the transmission will abort. an overrun condition occurs when more data is transmitted than the slave can receive. a maskable interrupt may be issued by the i 2 c controller at the conclusion of a normal or errant reception. to prepare the i 2 c controller in slave mode for data reception, you must configure one or more rx buffer descriptors to receive the data from the master. set the e bit in the rx buffer descriptors to prepare them to receive data. other rx buffer descriptor control bits, such as w and i, may also be set. you must then set the str bit in the i2com register to prepare the slave to respond to the master. 16.13.3.2.2 read from master. if an external master requests a read operation, the i 2 c controller will acknowledge the newly received byte containing the slave address and read bit (r/w = 1), but only if the transmitter fifo has been loaded by the sdma channel. if the transmitter is ready, the slave starts transmitting on the next clock pulse following the acknowledge. otherwise, the transaction is aborted and a maskable tx error interrupt may be issued to notify the software to prepare transmit data for another attempt. a maskable interrupt may be issued upon normal completion of transmission or after other transmission errors occur. if an underrun condition occurs, the slave transmits ones until a stop condition is detected. an underrun occurs if the slave device does not transmit all of the data requested by the master. to prepare the i 2 c controller in slave mode to transmit data, you must configure one or more tx buffer descriptors to transmit the data to the master. set the e bit in the rx buffer descriptors to prepare them to receive data. other tx buffer descriptor control bits, such as w, i, and l, may also be set. you must then set the str bit in the i2com register to prepare the slave to respond to the master.
communication processor module motorola mpc823e reference manual 16-463 i 2 c communication 16 processor module 16.13.4 i 2 c parameter ram memory map the i 2 c controller parameter ram area begins at the i 2 c base address, which is used for the general i 2 c parameters. it is similar to the sccx general-purpose parameter ram. you must initialize certain parameter ram values before the serial peripheral interface is enabled. the communication processor module initializes the other values. once initialized, the parameter ram values do not usually need to be accessed by your software. they must only be modified when there is no serial peripheral interface activity. ? rbase and tbasethe dual-port ram starts receiving and transmitting data for the i 2 c buffer descriptors in the rbase and tbase entries. they provide a great deal of flexibility for partitioning buffer descriptors for an i 2 c controller. by selecting rbase and tbase for the i 2 c controller and by setting the w bit in the last buffer descriptor in each buffer descriptor list, you can select the number of buffer descriptors to allocate for the transmit and receive side of the i 2 c controller. however, you must initialize these entries before enabling the corresponding channel. furthermore, you must not configure the buffer descriptor tables of the i 2 c controller to overlap because erratic operation will occur. rbase and tbase must contain a value that is divisible by eight. table 16-40. i 2 c controller parameter ram memory map address name width description i 2 c base + 00 rbase half-word rx buffer descriptor base address i 2 c base+ 02 tbase half-word tx buffer descriptor base address i 2 c base+ 04 rfcr byte rx function code i 2 c base+ 05 tfcr byte tx function code i 2 c base+ 06 mrblr half-word maximum receive buffer length i 2 c base+ 08 rstate word rx internal state i 2 c base+ 0c rptr word rx internal data pointer i 2 c base+ 10 rbptr half-word rx buffer descriptor pointer i 2 c base+ 12 rcnt half-word rx internal byte count i 2 c base+ 14 rtmp word rx temp i 2 c base+ 18 tstate word tx internal state i 2 c base+ 1c tptr word tx internal data pointer i 2 c base+ 20 tbptr half-word tx buffer descriptor pointer i 2 c base+ 22 tcnt half-word tx internal byte count i 2 c base+ 24 ttmp word tx temp note: you are only responsible for initializing the items in bold. i 2 c base = (immr & 0xffff0000) + 0x3c80.
communication processor module 16-464 mpc823e reference manual motorola i 2 c communication 16 processor module ? rfcr and tfcrthe rx and tx function code entries contain the value that you want to appear on the at pins when the associated sdma channel accesses memory. this register controls the byte-ordering convention used in the transfers. bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set these bits to select the required byte ordering of the data buffer. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type 1C3 these bits contain the function code value used during the sdma channel memory access. at0 is driven with a 1 to identify this sdma channel access as a dma-type access. rfcr bit 0 1 2 3 4 5 6 7 field reserved bo at reset 000 r/w r/w r/w r/w addr i2c base + 0x04 tfcr bit 0 1 2 3 4 5 6 7 field reserved bo at reset 000 r/w r/w r/w r/w addr i2c base + 0x05
communication processor module motorola mpc823e reference manual 16-465 i 2 c communication 16 processor module bits 0C2reserved these bits are reserved and must be set to 0. bobyte ordering you must set this bit to select the required byte ordering of the data buffer. 00 = the dec/intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. 01 = powerpc little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1x = motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. ataddress type 1C3 these bits contain the function code value used during the sdma channel memory access. at0 is driven with a 1 to identify this sdma channel access as a dma-type access. ? mrblrthe i 2 c controller has a maximum receive buffer length register entry to define its receive buffer length and it defines the maximum number of bytes that the mpc823e writes to a receive buffer on that i 2 c controller before moving to the next buffer. the mpc823e writes fewer bytes to the buffer than the mrblr value if an error or end-of-frame occurs, but it never writes more bytes than the mrblr value. buffers you supply for the mpc823e to use must always be at least as long as mrblr. the i 2 c transmit buffers are not affected by the value you program into mrblr and they can be different lengths. you can choose the number of bytes to be transmitted by programming the data length field in the tx buffer descriptor. note: the mrblr is not intended to be dynamically changed while a serial management controller is operating. however, if it is modified in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back), then a dynamic change in the receive buffer length can be successfully achieved. this occurs when the communication processor module transfers control to the next rx buffer descriptor in the table. thus, a change to mrblr does not have an immediate effect. to guarantee that the change occurs on a particular rx buffer descriptor, you must only change the mrblr while the smcx receiver is disabled. the value of mrblr must be greater than zero and it must be even if the character length of the data is greater than 8 bits.
communication processor module 16-466 mpc823e reference manual motorola i 2 c communication 16 processor module ? rbptrthe receive buffer pointer entry for each i 2 c channel points to the next buffer descriptor that the receiver transfers data to when it is idle or to the current buffer descriptor during frame processing. after a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the rbase entry. although in most applications you must not write the rbptr, it can be modified when the receiver is disabled or when you are sure no receive buffer is currently in use. ? tbptrthe transmit buffer pointer entry for each i 2 c channel points to the next buffer descriptor that the transmitter transfers data from when it is idle or to the current buffer descriptor during frame transmission. after a reset or when the end of buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the tbase entry. although in most applications you must not write tbptr, it can be modified when the transmitter is disabled or when you are sure no transmit buffer is currently in use. ? other general parametersfor normal operation, you do not need to access these parameters. they are only listed here because they provide helpful debugging information. additional parameters are listed in table 16-40. rptr and tptr are updated by the sdma channels to show the next address to be accessed. tcnt is a down-count value that is initialized with the data length field of the tx buffer descriptor and decremented with every byte read by the sdma channels. rcnt is a down-count value that is initialized with the mrblr value and decremented with every byte the sdma channels write. the rstate, tstate, rtmp, ttmp, and reserved areas can only be used by the risc microcontroller. 16.13.5 i 2 c commands you can program the cpm command register (cpcr) with the following commands to transmit or receive data. ? init tx parameters this command initializes all transmit parameters in this serial channels parameter ram to their reset state and must only be issued when the transmitter is disabled. the init tx and rx params command can also be used to reset the transmit and receive parameters. ? close rx bd this command is used to force the i 2 c controller to close the current rx buffer descriptor if it is being used and to use the next buffer descriptor for any subsequently received data. if the i 2 c controller is not in the process of receiving data, no action is taken by this command. ? init rx parameters this command initializes all the receive parameters in this serial channels parameter ram to their reset state and must only be issued when the receiver is disabled. the init tx and rx params command can also be used to reset the receive and transmit parameters.
communication processor module motorola mpc823e reference manual 16-467 i 2 c communication 16 processor module 16.13.6 the i 2 c buffer descriptor ring the data associated with the i 2 c controller is stored in buffers, which are referenced by buffer descriptors organized in a buffer descriptor ring located in the dual-port ram. this ring has the same basic configuration as the serial communication and serial management controllers. the buffer descriptor ring forms a circular queue that helps you organize the buffers you want to transmit or receive. using the buffer descriptors, the communication processor module confirms reception and transmission or indicates error conditions so that the processor knows the buffers have been serviced. the actual buffers can reside in either external or internal memory and the data buffers can reside in the parameter ram area of another controller if it is not enabled. figure 16-132. i 2 c memory format frame status data length data pointer frame status data length data pointer tx data buffer pointer to i2c rx ring rx data buffer dual-port ram external memory tx buffer descriptor ring rx buffer descriptor ring tx data buffer pointer to i2c tx ring
communication processor module 16-468 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13.7 programming the i 2 c controller 16.13.7.1 i 2 c mode register. the read/write i 2 c mode (i2mod) register controls both the i 2 c operation mode and clock source. bits 0C1reserved these bits are reserved and must be set to 0. revdreverse data this bit determines the receive and transmit character bit order. 0 = normal operation. most-significant bit of character transmitted and received first. 1 = reverse data. least-significant bit of character transmitted and received first. gcdgeneral call disable this bit determines if the receiver will acknowledge a general call address. 0 = general call address is enabled. 1 = general call address is disabled. fltclock filter this bit determines if the i 2 c input clock is filtered to prevent spikes in a noisy environment. 0 = i2clk is not filtered. 1 = i2clk is filtered by a digital filter. pdivpre divider this field determines the division factor of the clock before it is fed into the baud rate generator. the clock source for the i 2 c controller is the brgclk that is generated by the system interface unit. 00 = use the brgclk/32 as the input to the i 2 c baud rate generator. 01 = use the brgclk/16 as the input to the i 2 c baud rate generator. 10 = use the brgclk/8 as the input to the i 2 c baud rate generator. 11 = use the brgclk/4 as the input to the i 2 c baud rate generator. i2mod bit 0 1 2 3 4 5 6 7 field reserved revd gcd flt pdiv en reset 000000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x860
communication processor module motorola mpc823e reference manual 16-469 i 2 c communication 16 processor module enenable i 2 c this bit enables i 2 c operation. when en is cleared, the i 2 c controller is in a reset state and consumes minimal power. 0 = i 2 c controller is disabled. 1 = i 2 c controller is enabled. 16.13.7.2 i 2 c receive buffer descriptor. using receive (rx) buffer descriptors, the communication processor module reports information about each buffer of received data, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current buffer is full. in addition, it closes the buffer when a stop or start condition is found on the i 2 c bus or when an overrun error occurs. the first word of the rx buffer descriptor contains status and control bits, which you prepare before reception and then the communication processor module sets them after the buffer is closed. the second word contains the data length (in bytes) that is received and the third and fourth words contain a pointer that always points to the beginning of the received data buffer. the core writes these rx buffer descriptor bits before the i 2 c controller is enabled. note: do not modify other bits of the i2mod register when the en bit is set or else erratic operation will occur. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e res wi l reserved ov res offset + 2 data length offset + 4 rx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold.
communication processor module 16-470 mpc823e reference manual motorola i 2 c communication 16 processor module eempty 0 = the data buffer associated with this rx buffer descriptor is filled with received data or data reception is aborted due to an error condition. the core is free to examine or write to any fields of this rx buffer descriptor. the communication processor module does not use this buffer descriptor as long as the e bit is zero. 1 = the data buffer associated with this buffer descriptor is empty or reception is currently in progress. this rx buffer descriptor and its associated receive buffer are owned by the communication processor module. once the e bit is set, the core must not write any fields of this rx buffer descriptor. bits 1, 5C13, and 15reserved these bits are reserved and must be set to 0. wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the rx buffer descriptor table. 1 = this is the last buffer descriptor in the rx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that rbase points to in the table. the number of rx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is filled. 1 = the rxb bit in the i2ce register is set when this buffer is completely filled by the communication processor module, indicating the need for the core to process the buffer. the rxb bit can cause an interrupt if it is enabled. llast the i 2 c controller sets this bit when the buffer is closed because a stop (or start) condition occurred on the bus or as a result of an overrun. the i 2 c controller writes this bit after the received data is placed into the associated data buffer. 0 = this buffer does not contain the last character of the message. 1 = this buffer contains the last character of the message. ovoverrun this bit indicates that a receiver overrun has occurred during reception. the i 2 c controller writes this bit after the received data is placed into the associated data buffer.
communication processor module motorola mpc823e reference manual 16-471 i 2 c communication 16 processor module data length this field represents the number of octets that the communication processor module writes into this buffer descriptor data buffer. the communication processor module writes it once the buffer descriptor closes. the i 2 c controller writes these bits after the received data is placed into the associated data buffer. the actual amount of memory allocated for this buffer must be greater than or equal to the mrblr entry. rx data buffer pointer this field always points to the first location of the associated data buffer. it must be even and can reside in internal or external memory. the i 2 c controller writes these bits after the received data is placed into the associated data buffer. 16.13.7.3 i 2 c transmit buffer descriptor. data to be transmitted with the i 2 c is sent to the communication processor module by arranging it in buffers referenced by the transmit (tx) buffer descriptor ring. the first word of the tx buffer descriptor contains status and control bits. you must prepare the following bits before transmitting data. rready 0 = the data buffer associated with this buffer descriptor is not ready for transmission. you are free to manipulate this buffer descriptor or its associated data buffer. the communication processor module clears this bit after the buffer is transmitted or after an error occurs. 1 = the data buffer, which you prepare for transmission, is not transmitted yet or is currently being transmitted. you cannot write any fields of this buffer descriptor once this bit is set. bits 1 and 6C12reserved these bits are reserved and must be set to 0. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r res wi ls reserved nak un cl offset + 2 data length offset + 4 tx data buffer pointer offset + 6 note: you are only responsible for initializing the items in bold. note: the communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
communication processor module 16-472 mpc823e reference manual motorola i 2 c communication 16 processor module wwrap (final buffer descriptor in table) 0 = this is not the last buffer descriptor in the tx buffer descriptor table. 1 = this is the last buffer descriptor in the tx buffer descriptor table. after this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that tbase points to in the table. the number of tx buffer descriptors in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. iinterrupt 0 = no interrupt is generated after this buffer is serviced. 1 = the txb or txe bit in the i 2 c event register is set when this buffer is serviced. txb and txe can cause interrupts if they are enabled. llast 0 = this buffer does not contain the last character of the message. 1 = this buffer contains the last character of the message. stransmit start condition when this bit is set to 1, the i 2 c controller transmits a start condition before the first byte of the buffer. if this buffer descriptor is the first one in the frame, a start condition is transmitted, regardless of the value of this bit. this bit provides the ability to transmit a start byte or back-to-back frames. 0 = a start condition is not transmitted before the first byte of the buffer, unless it is the first byte of a frame. 1 = a start condition is transmitted before the first byte of the buffer. nakno acknowledge this bit indicates that the transmission has been aborted because the last transmitted byte was not acknowledged. the i 2 c controller writes this bit after it finishes transmitting the associated data buffer. ununderrun this bit indicates that the i 2 c controller has encountered a transmitter underrun condition while transmitting the associated data buffer. the i 2 c controller writes this bit after it finishes transmitting the associated data buffer. clcollision this bit indicates that transmission has been aborted because the transmitter was lost while arbitrating for the bus. the i 2 c controller writes this bit after it finishes transmitting the associated data buffer.
communication processor module motorola mpc823e reference manual 16-473 i 2 c communication 16 processor module data length this field represents the number of octets the communication processor module must transmit from this buffer descriptor data buffer. however, it is never modified by the communication processor module. normally, this value must be greater than zero. the i 2 c controller writes these bits after it finishes transmitting the associated data buffer. tx data buffer pointer this field always points to the first location of the associated data buffer. they can be even or odd, unless the number of actual data bits in the character is greater than 8 bits, in which case the transmit buffer pointer must be even. the buffer can reside in internal or external memory. the i 2 c controller writes these bits after it finishes transmitting the associated data buffer. 16.13.7.4 i 2 c address register. the 8-bit, memory-mapped, read/write i 2 c address (i2add) register holds the address for this i 2 c port. you must program this register if you are operating in multimaster, slave, or local loopback mode. you must clear this register before using i 2 c master mode. if you do not, this register may cause the i 2 c controller to match the address of an external device, thus causing incorrect behavior. sad slave address 0C6 this field holds the slave address for the i 2 c port. bit 7reserved this bit is reserved and must be set to 0. i2add bit 0 1 2 3 4 5 6 7 field sad reserved reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x864 note: = undefined.
communication processor module 16-474 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13.7.5 i 2 c baud rate generator register. the 8-bit, memory mapped, read/write i 2 c baud rate generator (i2brg) register sets the divide ratio of the baud rate generator. this register is set to all ones at hard reset. div division ratio 0C7 this field specifies the divide ratio of the baud rate generator divider in the i 2 c clock generator. the output of the prescaler is divided by 2 x (div + 3 + (2 x flt)) and the clock has a 50% duty cycle. the flt bit is in the i2mod register. 16.13.7.6 i 2 c command register. the 8-bit read/write i 2 c command (i2com) register is used to start i 2 c operation. strstart transmit when the i 2 c controller is in master mode, setting this bit to 1 causes the i 2 c controller to start transmitting data from the i 2 c transmit buffers if they are ready. when the i 2 c controller is in slave mode, setting the str bit to 1 when the i 2 c controller is idle causes it to load the transmit data register from the i 2 c transmit buffer and start transmitting when it receives an address byte that matches the slave address with the r/w bit set to 1. the str bit is always read as a zero. i2brg bit 0 1 2 3 4 5 6 7 field div reset 11111111 r/w r/w addr (immr & 0xffff0000) + 0x868 note: the minimum value for div is three if the digital filter is disabled (flt=0) and six if it is enabled (flt=1). i2com bit 0 1 2 3 4 5 6 7 field str reserved m/s reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x86c
communication processor module motorola mpc823e reference manual 16-475 i 2 c communication 16 processor module bits 1C6reserved. these bits are reserved and must be set to 0. m/smaster/slave this bit configures the i 2 c controller to operate as a master or a slave. 0 = i 2 c controller is a slave. 1 = i 2 c controller is a master. 16.13.7.7 i 2 c event register. the 8-bit memory-mapped i 2 c event register (i2cer) is used to generate interrupts and report events recognized by the i 2 c controller. when an event is recognized, the i 2 c controller sets its corresponding bit in the i2cer. interrupts generated by this register can be masked in the i 2 c mask register. a bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. all unmasked bits must be cleared before the communication processor module clears the internal interrupt request. this register is cleared by reset and can be read at any time. bits 0C2 and 4reserved these bits are reserved and must be set to 0. txetx error this bit indicates that an error has occurred during transmission. bsybusy condition this bit indicates that received data has been discarded due to a lack of buffers. this bit is set after the first character is received for which there is no receive buffer available. txbtx buffer this bit indicates that a buffer has been transmitted. it is set once the transmit data of the last character in the buffer is written to the transmit fifo. you must wait two character times to be sure that the data is completely sent over the transmit pin. rxbrx buffer this bit indicates that a buffer has been received. this bit is set after the last character is written to the receive buffer and the rx buffer descriptor is closed. i2cer bit 0 1 2 3 4 5 6 7 field reserved txe reserved bsy txb rxb reset 0 00000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x870
communication processor module 16-476 mpc823e reference manual motorola i 2 c communication 16 processor module 16.13.7.8 i 2 c mask register. the 8-bit read/write i 2 c mask register (i2cmr) has the same bit formats as the i2cer. if a bit in the i2cmr is 1, the corresponding interrupt in the i2cer is enabled. if the bit is zero, the corresponding interrupt in the i2cer is masked. this register is cleared by reset. 16.13.8 i 2 c controller initialization sequence the following initialization sequence is for the i 2 c controller to operate in master mode and read one byte from a slave device that contains an internal read address. the i 2 c controller operates the scl at 391khz. a system frequency of 50mhz is assumed. the sda and scl pins of the mpc823e are connected to an external 5v power supply with 6.8k ohm to 10k ohm resistors. 1. configure the port b pins to enable the sda and scl pins. write pbpar, pbdir, and pbodr bits 26 and 27 with ones. 2. disable the i 2 c controller by clearing the i2mod register, including the en bit. now you can modify other fields in the i2mod register. 3. configure the i 2 c dedicated baud rate generator to operate at 391khz at a system frequency of 50mhz by programming the divider and pre-divider. the overall i 2 c baud rate generator clock divider is 128 (decimal) and is realized by establishing a pre-divider of 8 and a divider of 16. write the pdiv field of the i2mod register with 2 to pre-divide by 8. write the div field of the i2brg register with 5 to divide by 16. 4. write 0x0 to the i2cadd register to clear it. 5. write 0x01 to the i2com register to configure the i 2 c controller for master mode operation. 6. write 0x0001 to the sdcr to set the sdma bus arbitration level to 5. 7. write rbase and tbase in the i 2 c parameter ram to point to the rx and tx buffer descriptors in the dual-port ram. assuming the initial rx buffer descriptor at the beginning of dual-port ram and the initial tx buffer descriptor 64 bytes from the beginning, write rbase with 0x2000 and tbase with 0x2040. 8. write 0x11 into the cpcr to execute the init rx and tx params command for i 2 c. 9. write 0x15 into the rfcr and tfcr for normal operation. 10. write mrblr with the maximum bytes per receive buffer. in this case, assume 16 bytes, so mrblr = 0x10. i2cmr bit 0 1 2 3 4 5 6 7 field reserved txe reserved bsy txb rxb reset 0 00000 r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x874
communication processor module motorola mpc823e reference manual 16-477 ports communication 16 processor module 11. initialize the rx buffer descriptor. assume the rx data buffer is at 0x00001000 in main memory. write 0xb000 to rx_bd_status, 0x0 to rx_bd_length (optional), and 0x00001000 to rx_bd_pointer. 12. initialize the tx buffer descriptors. assume the tx data buffer 0 is at 0x00004000 in main memory. write 0x9000 to tx_bd_status 0, 0x2 to tx_bd_length 0, and 0x00004000 to tx_bd_pointer 0. assume the tx data buffer 1 is at 0x00004010 in main memory. write 0xbc000 to tx_bd_status 1, 0x2 to tx_bd_length 1, and 0x00004010 to tx_bd_pointer 1. 13. write 0xffff to the i2cer to clear any previous events. 14. write 0x17 to the i2cmr to enable all transmit and receive interrupts. 15. write 0x10000 to the cimr to allow the i 2 c controller to generate a system interrupt. write 0x8080 to the cicr to configure interrupt request level 4 and enable cpm interrupts. 16. write 0x01 to the i2mod register to enable the i 2 c controller. 17. set the str bit in the i2com register to begin a master read operation. 16.14 the parallel i/o ports the communication processor module supports four general-purpose i/o portsa, b, c, and d. each pin in the i/o ports can be configured as a general-purpose i/o pin or as a dedicated peripheral interface pin. port a is shared with the serial communication controller 2 rxd2 and txd2 pins, the bank of clocks pins, and some time-division multiplex pins. port b is shared with functions like the idma, scc3 (rxd3 and txd3), smcx, spi, tdm, usb, and i 2 c pins. port c is shared with the rtsx , ctsx , and cdx pins of the serial communication controllers as well as some time-division multiplex pins. however, port c is unique in that its pins can generate interrupts to the cpm interrupt controller. you can configure the pins as an input or output, to have a latch for data output, or to be read or written at any time. you can even configure them to be either general-purpose i/o or dedicated peripheral pins. ports a and b have pins that can be configured as open-drain. these pins drive a zero voltage, but they three-state when driving a high voltage. note: the port pins do not have internal pull-up resistors. because of the significant flexibility of the communication processor module, many dedicated peripheral functions are multiplexed onto ports a, b, and c. the functions are grouped in such a way as to maximize the usefulness of the pins in the greatest number of mpc823e applications. it may be difficult to fully understand the pin assignment capability described in this section until you better understand the cpm peripherals themselves.
communication processor module 16-478 mpc823e reference manual motorola ports communication 16 processor module 16.14.1 features the following is a list of the parallel i/o ports main features: ? port a is 12 bits ? port b is 16 bits ? port c is 12 bits ? port d is 13 bits ? all ports are bidirectional ? all ports have alternate on-chip peripheral functions ? all ports are three-stated at system reset ? all pin values can be read while the pin is connected to an on-chip peripheral ? ports a and b have open-drain capability ? port c has 12 interrupt input pins 16.14.2 port a pin functionality the 12 port a pins are independently configured as general-purpose i/o pins if the corresponding bit in the port a pin assignment register (papar) is cleared. on the other hand, each pin is configured as a dedicated on-chip peripheral pin if the corresponding papar bit is set. when the port a pin is configured as a general-purpose i/o pin, the signal direction for that pin is determined by the corresponding control bit in the port a data direction register (padir). the port a pin is configured as an input if the corresponding padir bit is cleared and configured as an output if the corresponding bit is set. all papar and padir bits are cleared at system reset, which configures all port a pins as general-purpose input pins.
communication processor module motorola mpc823e reference manual 16-479 ports communication 16 processor module table 16-41 contains the default description of all port a pin options. if a port a pin is selected as a general-purpose i/o pin, it can be accessed through the port a data register (padat). data written to the padat is stored in an output latch. if a port a pin is configured as an output, the output latch data is gated onto the port pin. when padat is read, the port pin itself is read. if a port a pin is configured as an input, data written to padat is still stored in the output latch, but is prevented from reaching the port pin. in this case, when padat is read, the state of the port pin is read. if an input to a peripheral is not supplied from a pin, then a default value is supplied to the on-chip peripheral as listed in table 16-41. table 16-41. port a pin assignment signal pin function papar = 0 papar = 1 peripherals padir = 0 padir = 1 pa15 port a15 usbrxd gnd pa14 port a14 usboe pa13 port a13 rxd2 gnd pa12 port a12 txd2 pa9 port a9 smrxd2 l1txda undefined pa8 port a8 smtxd2 l1rxda gnd pa7 port a7 clk1/tin1/l1rclka brgo1 clk1/tin1/l1rclka = brgo1 pa6 port a6 tin3/clk2/l1rclkb tout1 tin3/clk2 = gnd pa5 port a5 clk3/tin2/l1tclka brgo2 clk3/tin2/l1tclka = brgo2 pa4 port a4 tin4/clk4/l1tclkb tout2 tin4/clk4 = gnd note: the items in bold have open-drain capability. the i/o direction for the tdm and smc2 pins are reversed. see pa8 and pa9.
communication processor module 16-480 mpc823e reference manual motorola ports communication 16 processor module 16.14.3 the port a registers port a has four 16-bit, memory-mapped, read/write control registers. 16.14.3.1 port a open-drain register. the port a open-drain register (paodr) indicates when the port pins are configured in a normal or wired-or configuration. three of the paodr bits can be open-drain to correspond to those pins that have serial channel output capability. the other bits are always zero. paodr is cleared by system reset. bits 0C8, 10C11, 13 and 15reserved these bits are reserved and must be set to 0. od9Cod15open-drain pins 9-15 0 = the i/o pin is actively driven as an output. 1 = the i/o pin is an open-drain driver. as an output, the pin is actively driven low. otherwise, it is three-stated. 16.14.3.2 port a data register. a read of the port a data (padat) register returns the data at the pin, regardless of whether the pin is defined as an input or output. this allows output conflicts to be found on the pin by comparing the written data with the data on the pin. a write to the padir is latched and if the bit is configured as an output, the value latched for that bit is driven onto its respective pin. padat is not initialized and is undefined at reset. bits 0C3reserved these bits are reserved and must be set to 0. d4Cd15data pins 4-15 the value written into these bits may be read on the port a pins. paodr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved od9 reserved od12 res od14 res reset 0 0 0 0000 r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x954 padat bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset 0 000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x956
communication processor module motorola mpc823e reference manual 16-481 ports communication 16 processor module 16.14.3.3 port a data direction register. the port a data direction (padir) register is cleared by system reset. bits 0C3reserved these bits are reserved and must be set to 0. dr4Cdr15direction pins 4-15 0 = the corresponding pin is an input. 1 = the corresponding pin is an output. 16.14.3.4 port a pin assignment register. the port a pin assignment register (papar) is cleared at system reset. bits 0C3reserved these bits are reserved and must be set to 0. dd4Cdd15dedicated peripheral pins 4-15 0 = general-purpose i/o. the peripheral functions of the pin are not used. 1 = dedicated peripheral function. the pin is used by the internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits. padir bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15 reset 0 000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x950 papar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved dd4 dd5 dd6 dd7 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 reset 0 000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x952
communication processor module 16-482 mpc823e reference manual motorola ports communication 16 processor module 16.14.4 port a example configurations the port a pins can be configured in many ways. pa15 can be configured as a general-purpose i/o pin, but not an open-drain pin. it can also be the usbrxd pin for the usb. if it is configured as a general-purpose i/o pin, the usbrxd input is internally grounded. figure 16-133 and figure 16-134 illustrate the block diagrams of the pa15 and pa14 pins. pa14 can be configured as a general-purpose i/o pin, either open-drain or not. it can also be the usboe pin for the usb. if usboe is configured as an output on pa14 and the od14 bit is set in the paodr, then usboe is output from the usb as an open-drain output. if pa14 is configured as a general-purpose i/o pin, then the usboe output is not externally connected. figure 16-133. parallel block diagram for pa15 mux mux 0 1 en en 0 1 usbrxd/pa15 pin mux en 1 0 usbrxd to usb 16 bits to padat bit 15 output latch padir 16 bits papar en en
communication processor module motorola mpc823e reference manual 16-483 ports communication 16 processor module pa7 can be configured as a general-purpose i/o pin, but not an open-drain pin. if the corresponding padir bit is a zero, it can also be the clk1 pin, the tin1 pin, the l1rclka pin, or all three at once. there is nothing to select other than these three inputs in port a because the connections are made separately in the serial interface and timer mode registers. if the padir bit is a 1, this pin can also be the brgo1 pin. if the pa7 pin is a general-purpose i/o pin, then the input to the on-chip peripheral is internally connected to brg01. refer to section 16.7 the serial interface with time-slot assigner for more details about using the clk1 and l1rclka pins. pa4 can be configured as a general-purpose i/o pin, but not an open-drain pin. if the padir bit is zero, pa4 can also be the clk4 pin, tin4 pin, l1tclkb pin or all three at once. if the padir bit is a 1, pa4 can be the tout2 pin. if the pa4 pin is a general-purpose i/o pin, then the input to the on-chip clk4 function is grounded. refer to section 16.7 the serial interface with time-slot assigner for more details. figure 16-134. parallel block diagram for pa14 usboe /pa14 pin usboe /pa14 pin
communication processor module 16-484 mpc823e reference manual motorola ports communication 16 processor module 16.14.5 port b pin functionality all port b pins can be open-drain and are independently configured as general-purpose i/o pins if the corresponding bit in the pbpar is cleared. they are configured as dedicated on-chip peripheral pins if the corresponding pbpar bit is set. when configured as a general-purpose i/o pin, the signal direction of that pin is determined by the corresponding control bit in the pbdir. the port b pin is configured as an input if the corresponding pbdir bit is cleared and as an output if the corresponding pbdir bit is set. all pbpar bits and pbdir bits are cleared by total system reset, which configures all port b pins as general-purpose input pins. refer to table 16-42 for a description of all port b pin options. if a port b pin is used as a general-purpose i/o pin, it can be accessed with the pbdat where data is stored in an output latch. if a port b pin is configured as an output, the output latch data is gated onto the port pin. when pbdat is read, the port pin itself is read. if a port b pin is configured as an input, data written to pbdat is still stored in the output latch, but is prevented from reaching the port pin. when pbdat is read, the state of the port pin is read. many of the port b pins have more than one function, including on-chip peripheral functions for spi, i 2 c, smc1, smc2, scc3, tdm, and lcd. pb27 and pb26 are unusual in that their on-chip peripheral functions (brgo2 and brgo1) are also used in port a. this allows an alternate way to output the brgo pins if other functions are used. pb18 and pb16 are also unusual in that their on-chip peripheral functions (rts2 and l1rqa) are used in port c, which is an alternate location to output these pins if using other functions on port c. table 16-42. port b pin assignment signal pin function pbpar = 0 pbpar = 1 input to on-chip peripherals pbdir = 0 pbdir = 1 pb31 port b31 spisel lcd_a spisel=v dd pb30 port b30 txd3 spiclk spiclk = gnd pb29 port b29 rxd3 spimosi spimosi=v dd ; txd3 = pb24 (rxd3) pb28 port b28 brgo3 spimiso spimiso = spimosi pb27 port b27 brgo1 i2csda i2csda= v dd pb26 port b26 brgo2 i2cscl i2cscl = gnd pb25 port b25 smtxd1 txd3 pb24 port b24 smrxd1/l1rxdb rxd3 smrxd1 = vcc;rxd3 = gnd pb23 port b23 smsyn1 /l1tsyncb sdack1 smsyn1 = gnd pb22 port b22 smsyn2 /l1rsyncb sdack2 smsyn2 = gnd pb19 port b19 l1st1 lcd_b pb18 port b18 l1st2 rts2
communication processor module motorola mpc823e reference manual 16-485 ports communication 16 processor module 16.14.6 the port b registers port b has four memory-mapped, read-write control registers. 16.14.6.1 port b open-drain register. the 16-bit port b open drain register (pbodr) indicates when the port pins are configured in a a normal or wired-or configuration. bits 0 and 15 of this register are reserved. bits 0C15reserved these bits are reserved and must be set to 0. od16Cod31open-drain pins 16-31 0 = the i/o pin is actively driven as an output. 1 = the i/o pin is an open-drain driver. as an output, the pin is actively driven low. otherwise, it is three-stated. pb17 port b17 l1st3 lcd_c pb16 port b16 l1st4 l1rqa pbodr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x ac0 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field od16 od17 od18 od19 od20 od21 od22 od23 od24 od25 od26 od27 od28 od29 od30 od31 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x ac2 note: smtxd1 cannot be set as an open-drain driver, regardless of how this register is set. table 16-42. port b pin assignment signal pin function pbpar = 0 pbpar = 1 input to on-chip peripherals pbdir = 0 pbdir = 1
communication processor module 16-486 mpc823e reference manual motorola ports communication 16 processor module 16.14.6.2 port b data register. a read of the port b data register (pbdat) returns the data to the pin, regardless of whether the pin is defined as an input or output. this allows output conflicts to be found on the pin by comparing the written data with the data on the pin. a write to the pbdat is latched and if that bit in the pbdir is configured as an output, the value latched for that bit is driven onto its respective pin. pbdat can be read or written at any time, is not initialized, and is undefined at reset. bits 0C15reserved these bits are reserved and must be set to 0. d16C31data pins 16C31 these bits contain data can be read or written from the port b pins. pbdat bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x ac4 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xac6
communication processor module motorola mpc823e reference manual 16-487 ports communication 16 processor module 16.14.6.3 port b data direction register. the port b data direction register (pbdir) is cleared at system reset. bits 0C15reserved these bits are reserved and must be set to 0. dr16Cdr31data direction pins 16-31 0 = the corresponding pin is an input. 1 = the corresponding pin is an output. pbdir bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x ab8 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dr16 dr17 dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 dr26 dr27 dr28 dr29 dr30 dr31 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xaba
communication processor module 16-488 mpc823e reference manual motorola ports communication 16 processor module 16.14.6.4 port b pin assignment register. the port b pin assignment register (pbpar) is cleared by system reset. bits 0C15reserved these bits are reserved and must be set to 0. dd16Cdd31dedicated function pins 16-31 0 = general-purpose i/o. the peripheral functions of the pin are not used. 1 = dedicated peripheral function. the pin is used by the internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits, such as those in the pbdir. pbpar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset 0 r/w r/w addr (immr & 0xffff0000) + 0x abc bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xabe
communication processor module motorola mpc823e reference manual 16-489 ports communication 16 processor module 16.14.7 port b configuration example you can configure the pb31 pin as a general-purpose i/o or open-drain pin. it can also be the lcd_a pin for the lcd controller or the spi select input spisel pin. if pb31 is not configured to connect to the lcd_a or spisel signal, then the serial peripheral interface receives v dd on that signal. 16.14.8 port c pin functionality port c consists of 12 general-purpose i/o pins that have interrupt capability. refer to table 16-43 for a description of all port c pin options. all pcdir and pcpar bits are cleared by a total system reset, which configures all port pins as general-purpose input pins. notice that the global cpm interrupt mask register is also cleared when a total system reset occurs, so if any port c pin is left floating it does not cause a false interrupt. if a port c pin is selected as a general-purpose i/o pin, it can be accessed through the pcdat register where written data is stored in an output latch. if a port c pin is configured as an output, the output latch data is gated onto the port pin. when the pcdat register is read, the port pin itself is read. if a port c pin is configured as an input, data written to pcdat register is still stored in the output latch, but is prevented from reaching the port pin. in this case, when pcdat register is read, the state of the port pin is read. table 16-43. port c pin assignment signal pcpar = 0 pcpar = 1 input to on-chip peripherals pcdir = 1 or pcso = 0 pcdir = 0 and pcso = 1 pcdir = 0 pcdir = 1 pc15 port c15 dreq1 l1txdb l1st5 ext0 = vdd pc14 port c14 dreq2 rts2 l1st6 ext1 = vdd pc13 port c13 rts3 l1st7 pc12 port c12 l1rqa l1st8 pc11 port c11 usbrxp gnd pc10 port c10 usbrxn tgate1 gnd pc9 port c9 cts2 gnd pc8 port c8 cd2 tgate1 gnd pc7 port c7 usbtxp pc6 port c6 usbtxn pc5 port c5 cts3 l1tsynca sdack1 pc4 port c4 cd3 l1rsynca cd3 = gnd
communication processor module 16-490 mpc823e reference manual motorola ports communication 16 processor module when the pin is configured as an output, port c interrupts cannot be generated. to configure a port c pin as a general-purpose output pin, follow these steps: 1. write the corresponding pcpar bit with a zero. 2. write the corresponding pcdir bit with a 1. 3. write the corresponding pcso bit with a zero (for clarity). 4. the corresponding pcint bit is a dont care bit. 5. write the pin value using the pcdat register. to configure a port c pin as a general-purpose input pin that does not generate an interrupt, follow these steps: 1. write the corresponding pcpar bit with a zero. 2. write the corresponding pcdir bit with a zero. 3. write the corresponding pcso bit with a zero. 4. the corresponding pcint bit is a dont care bit. 5. write the corresponding cimr bit with a zero to prevent interrupts from being generated to the core. 6. read the pin value using the pcdat register. when a port c pin is configured as a general-purpose input pin, a change in the port c interrupt register (pcint) causes an interrupt request signal to be sent to the cpm interrupt controller. you can program each port c line to assert an interrupt request when a high-to-low change occurs or when any change occurs. each port c line asserts a unique interrupt request to the cpm interrupt pending register and has a different internal interrupt priority level within the cpm interrupt controller. refer to section 16.15 the cpm interrupt controller for more details. each request can be masked independently in the cpm interrupt mask register. to configure a port c pin as a general-purpose input pin that generates an interrupt, follow these steps: 1. write the corresponding pcpar bit with a zero. 2. write the corresponding pcdir bit with a zero. 3. write the corresponding pcso bit with a zero. 4. set the pcint bit to discover the edges that cause the interrupts. 5. write the corresponding cimr bit with a 1 so that interrupts can be sent to the core. 6. read the pin value using the pcdat register.
communication processor module motorola mpc823e reference manual 16-491 ports communication 16 processor module the port c lines associated with the cdx and ctsx pins have a mode of operation in which the pin can be internally connected to the corresponding serial communication controller, but can also generate interrupts. port c still detects changes on the ctsx and cdx pins and asserts the corresponding interrupt request, but the serial communication controller simultaneously uses the ctsx and/or cdx pin to automatically control operation. this allows you to fully implement protocols v.24, x.21, and x.21 bis with the assistance of other general-purpose i/o lines. to configure a port c pin as a ctsx or cdx pin that connects to a serial communication controller and generates interrupts, follow these steps: 1. write the corresponding pcpar bit with a zero. 2. write the corresponding pcdir bit with a zero. 3. write the corresponding pcso bit with a 1. 4. set the pcint bit to find out which edges cause the interrupts. 5. write the corresponding cimr bit with a 1 so that interrupts can be sent to the core. 6. the pin value can be read at any time using the pcdat register. the dreq1 and dreq2 pins in port c can assert an external request to the risc microcontroller instead of asserting an interrupt to the core. you can program each pin to assert an interrupt request when a high-to-low change occurs or any change that as configured in pcint. 16.14.9 port c registers you can communicate with port c using five registers. the port c interrupt control register (pcint) indicates how changes on the pin cause interrupts when they are generated with that pin. the port c special options register (pcso) indicates whether certain port c pins can connect to on-chip peripherals and generate an interrupt at the same time. the remaining port c registers exist on the other ports as well. however, since port c does not have an open-drain capability, there is no open-drain register. note: after connecting the ctsx or cdx pins to the corresponding serial communication controller, you must also choose normal operation mode in the diag field of the gsmr_l to enable or disable sccx transmission and reception with these pins. note: do not program the dreq1 and dreq2 pins to assert external requests to the risc microcontroller, unless instructed to do so by motorola as part of a ram microcode package. otherwise, erratic behavior will occur.
communication processor module 16-492 mpc823e reference manual motorola ports communication 16 processor module 16.14.9.1 port c data register. a read of the port c data register (pcdat) returns the data to the pin, regardless of whether the pin is defined as an input or output. this allows output conflicts to be found on the pin by comparing the written data with the data on the pin. a write to the pcdat is latched and if that bit in the pcdir is configured as an output, the value latched for that bit is driven onto its respective pin. pcdat can be read or written at any time, is not initialized, and is undefined at reset. bits 0C3reserved these bits are reserved and must be set to 0. d4C15data pins 4C15 these bits contain data can be read or written from the port c pins. 16.14.9.2 port c data direction register. the port c data direction register (pcdir) is a 16-bit register that is cleared by system reset. bits 0C3reserved these bits are reserved and must be set to 0. dr4Cdr15data direction pins 4C15 0 = the corresponding pin is an input. 1 = the corresponding pin is an output. pcdat bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset 0000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x966 note: = undefined. pcdir bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x960
communication processor module motorola mpc823e reference manual 16-493 ports communication 16 processor module 16.14.9.3 port c pin assignment register. the port c pin assignment register (pcpar) is a 16-bit register that is cleared by system reset. bits 0C3reserved these bits are reserved and must be set to 0. dd4Cdd15dedicated function pins 4-15 0 = general-purpose i/o. the peripheral functions of the pin are not used. 1 = dedicated peripheral function. the pin is used by the internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the pbdir. 16.14.9.4 port c special options register. the port c special options (pcso) register indicates whether certain port c pins can connect to on-chip peripherals and generate an interrupt at the same time. each bit defined in the pcso corresponds to a port c line (pc8Cpc11 and pc14Cpc15). the pcso is cleared by reset. bits 0C5 and 12C13reserved these bits are reserved and must be set to 0. cdxcarrier detect 2 and 3 0 = pcx is a general-purpose interrupt i/o pin. the sccx internal cdx signal is always asserted. if pcdir configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the pcint bits. 1 = pcx is connected to the corresponding sccx signal input in addition to being a general-purpose interrupt pin. pcpar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved dd4 dd5 dd6 dd7 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x962 pcso bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved cd3 cts3 cd2 cts2 usb rxn usb rxp reserved dreq1 dreq2 reset 0 000000 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x964
communication processor module 16-494 mpc823e reference manual motorola ports communication 16 processor module ctsxclear to send 2 and 3 0 = pcx is a general-purpose interrupt i/o pin. the sccx internal ctsx signal is always asserted. if pcdir configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the pcint bits. 1 = pcx is connected to the corresponding sccx signal input in addition to being a general-purpose interrupt pin. usbrxnusb receive (negative differential) 0 = pc10 is general purpose i/o pin. if pcdir configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the pcint bits. 1 = pc10 functions as usbrxn, provided that bits pcdir[10] and pcpar[10] are zero. in addition, this pin is a general-purpose interrupt pin. usbrxpusb receive (positive differential) 0 = pc11 is general purpose i/o pin. if pcdir configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the pcint bits. 1 = pc11 functions as usbrxp, provided that bits pcdir[11] and pcpar[11] are zero. in addition, this pin is a general-purpose interrupt pin. dreqx dma request to the risc microcontroller 0 = pcx is a general-purpose interrupt i/o pin, with the direction controlled in pcdir. if pcdir configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the pcint bits. 1 = pcx becomes an external request to the risc microcontroller instead of being a general-purpose interrupt pin. the corresponding pcint bits control when a request is generated. note: dreqx must only be set if you are using idma.
communication processor module motorola mpc823e reference manual 16-495 ports communication 16 processor module 16.14.9.5 port c interrupt control register. the 16-bit read/write port c interrupt control (pcint) register indicates how changes on the pin cause interrupts when they are generated with that pin. the pcint is cleared by reset. bits 0C3reserved. these bits are reserved and must be set to 0. edm4Cedm15edge detect mode for lines 4C15 the corresponding port c line asserts an interrupt request. 0 = any change on pcx generates an interrupt request. 1 = high-to low change on pcx generates an interrupt request. pcint bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved edm4 edm5 edm6 edm7 edm8 edm9 edm10 edm11 edm12 edm13 edm14 edm15 reset 0 000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x968
communication processor module 16-496 mpc823e reference manual motorola ports communication 16 processor module 16.14.10 port d pin functionality the 13 port d pins are independently configured as general-purpose i/o pins if the corresponding port d pin assignment register (pdpar) is cleared. they are configured as dedicated on-chip peripheral pins if the corresponding pdpar bit is set. as a general-purpose i/o pin, the signal direction is determined by the corresponding control bit in the port d data direction register (pddir). the port i/o pin is configured as an input if the corresponding pddir is cleared and it is configured as an output if the corresponding pddir is set. all pdpar and pddir pins are cleared at total system reset, which configures all port d pins as general-purpose input pins. refer to table 16-44 for all the port d pin options default descriptions. table 16-44. port d pin assignment signal pdpar = 0 pdpar = 1 input to on-chip peripherals pddir = 1 pddir=0 pd15 port d15 ld8 vd7 pd14 port d14 ld7 vd6 pd13 port d13 ld6 vd5 pd12 port d12 ld5 vd4 pd11 port d11 ld4 vd3 pd10 port d10 ld3 vd2 pd9 port d9 ld2 vd1 pd8 port d8 ld1 vd0 pd7 port d7 ld0 field pd6 port d6 lcd_ac/oe blank pd5 port d5 frame/vsync vv pd4 port d4 load/hsync vh pd3 port d3 shift/clk vclk vcc
communication processor module motorola mpc823e reference manual 16-497 ports communication 16 processor module 16.14.11 port d registers port d has three 16-bit, memory-mapped, read/write control registers. 16.14.11.1 port d data register. a read of the port d data (pddat) register returns the data on the pins, regardless of whether the pins are an input or an output. this allows output conflicts to be found on the pins by comparing the written data with the data on the pins. a write to the pddir is latched, and if that bit in the pddir is configured as an output, the value latched for that bit will be driven onto its respective pin. pddat can be read or written at any time. pddat is not initialized and is undefined by reset. bits 0C2reserved these bits are reserved and must be set to 0. d3C15data pins 3C15 these bits contain data can be read or written from the port d pins. 16.14.11.2 port d data direction register. the port d data direction register (pddir) is cleared at system reset. bits 0C2reserved these bits are reserved and must be set to 0. dr3Cdr15data direction pins 3C15 0 = the corresponding pin is an input. 1 = the corresponding pin is an output. pddat bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x976 note: = undefined. pddir bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved dr3 dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15 reset 0 0000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x970
communication processor module motorola mpc823e reference manual 16-498 cpic communication 16 processor module 16.14.11.3 port d pin assignment register. the port d pin assignment register (pdpar) is cleared at system reset. bits 0C2reserved these bits are reserved and must be set to 0. dd3Cdd15dedicated function pins 3-15 0 = general-purpose i/o. the peripheral functions of the pin are not used. 1 = dedicated peripheral function. the pin is used by the internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits, such as those in the pddir. 16.15 the cpm interrupt controller the communication processor modules interrupt controller (cpic) is the focal point for all interrupts associated with the communication processor module and it accepts and prioritizes the internal and external interrupt requests from the cpm blocks. it is also responsible for generating a vector during the core interrupt acknowledge cycle. the cpm interrupt controller receives interrupts from such internal sources as the usb, sccs, smcs, spi, i 2 c, general-purpose timers, and port c parallel i/o pins. the cpm interrupt controller allows you to mask each interrupt source. when multiple events within a sub-block of the communication processor module cause the interrupt, each event is maskable in that sub-block. all cpm sub-block interrupt sources are prioritized and bits are set in the cpm interrupt pending register (cipr) where all interrupt sources are assigned one programmable priority level (0C7) before the request for an interrupt is sent to the u-bus. an overview of the mpc823e interrupt structure is illustrated in figure 16-135. the lower half of the figure illustrates the cpm interrupt controller. pdpar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved dd3 dd4 dd5 dd6 dd7 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x972
communication processor module 16-499 mpc823e reference manual motorola cpic communication 16 processor module figure 16-135. mpc823e interrupt structure level 2 level 7 level 6 level5 level 4 level 3 level 1 level 0 nmi ireq[0:7] ireq nmi gen powerpc core system interface unit cpm port c[4:15] timer1 timer2 scc2 smc1 spi i 2 c smc2 tb pit rtc pcmcia lcd swt irq0 interrupt controller interrupt controller dec dec debug debug idma1 idma2 sdma risc timers edge/ level usb scc3 timer3 timer4
communication processor module motorola mpc823e reference manual 16-500 cpic communication 16 processor module within the cpm interrupt level, the sources are assigned a priority structure. on the mpc823e, you have some flexibility with the relative priority of the interrupt sources. once an unmasked interrupt source is pending in the cipr, the cpm interrupt controller sends an interrupt request to the u-bus at level 0, 1, 2, 3, 4, 5, 6, or 7. the cpm interrupt controller then waits for the interrupt to be recognized. after the core accepts the interrupt request, the core acknowledges the interrupt by setting the iack bit in the cpm interrupt vector register. when the iack bit is set, the civr is updated with a 5-bit vector corresponding to the sub-block with the highest current priority and the iack is cleared after one clock cycle. 16.15.1 features the following is a list of the cpm interrupt controllers main features: ? twenty-eight interrupt sources ? sources can be assigned to a programmable interrupt level ? programmable priority between the sccs and usb ? two priority schemes for the sccs and usb ? programmable highest priority request ? fully nested interrupt environment ? unique vector number for each interrupt source 16.15.2 cpm interrupt source priorities the cpm interrupt controller has 28 interrupt sources that assert a programmable interrupt request level to the core and the priority of these sources is shown in table 16-45. there is some flexibility in the relative ordering of the interrupts in the table, but, in general, the relative priorities are fixed in the descending order shown. an interrupt from the parallel i/o signal pc15 has the highest priority and an interrupt from the parallel i/o signal pc4 has the lowest. a single interrupt priority number is associated with each table entry. notice the lack of sdma interrupt sources. they are reported through each individual usb, scc, smc, spi, or i 2 c channel. the only true sdma interrupt source is the sdma channel bus error entry that is reported when a bus error occurs during an sdma access. there are two ways to add flexibility to the table of cpm interrupt priorities (the usb/sccx relative priority option or the highest priority option).
communication processor module 16-501 mpc823e reference manual motorola cpic communication 16 processor module 16.15.2.1 usb and sccx relative priority. the relative priority between the usb and sccs is programmable and can be dynamically changed. in table 16-45 there is no entry for the usb and sccs, but rather there are entries for scca, sccb, sccc, and sccd because each one of them can be mapped to any of these locations. this is programmed in the cicr and can be dynamically changed. you can use this on-the-fly capability to implement a rotating priority. in addition, there are two ways to group the locations of the scca, sccb, sccc, and sccd entriesgroup and spread. in the group scheme, the usb and sccs are all grouped together at the top of the priority table, ahead of most of the other cpm interrupt sources. this scheme is ideal for applications in which the usb and sccs function at a very high data rate and interrupt latency is very important. in the spread scheme, usb and sccs priorities are spread over the table, so other sources can have lower interrupt latencies than the usb and sccs. this scheme is also programmed in the cicr, but it cannot be dynamically modified. 16.15.2.2 highest priority interrupt. in addition to the usb and sccs relative priority option, you can choose one interrupt source to be of the highest priority. this highest priority interrupt is still within the same interrupt level as the rest of the cpic interrupts, but is serviced prior to any other interrupt in the table. if the highest priority feature is not used, select pc15 to be the highest priority interrupt and no modifications to the standard interrupt priority order will be made. this highest priority source is dynamically programmable in the cicr and it allows you to change a normally low priority source into a high priority source for a certain period of time.
communication processor module motorola mpc823e reference manual 16-502 cpic communication 16 processor module table 16-45. prioritization of cpm interrupt sources number priority level interrupt source description multiple events 1f highest parallel i/oCpc15 no 1e scca (grouped and spread) yes 1d sccb (grouped) yes 1c sccc (grouped) yes 1b sccd (grouped) yes 1a parallel i/oCpc14 no 19 timer 1 yes 18 parallel i/oCpc13 no 17 parallel i/oCpc12 no 16 sdma channel bus error yes 15 idma1 yes 14 idma2 yes 13 sccb (spread) yes 12 timer 2 yes 11 risc timer table yes 10 i 2 c yes f parallel i/oCpc11 no e parallel i/oCpc10 no d sccc (spread) yes c timer 3 yes b parallel i/oCpc9 no a parallel i/oCpc8 no 9 parallel i/oCpc7 no 8 sccd (spread) yes 7 timer 4 yes 6 parallel i/oCpc6 no 5 spi yes 4 smc1 yes 3 smc2 yes 2 parallel i/oCpc5 no 1 parallel i/oCpc4 no 0 lowest reserved
communication processor module 16-503 mpc823e reference manual motorola cpic communication 16 processor module 16.15.2.3 nested interrupts. the cpm interrupt controller supports a fully nested interrupt environment that allows a high priority interrupt from another cpm source to suspend a lower priority interrupt service routine. this nesting is achieved by the cpm interrupt in-service register (cisr). the cpm interrupt controller prioritizes all interrupt sources based on their assigned priority level. the highest priority interrupt request is presented to the core for servicing and the core acknowledges the interrupt by setting the iack bit in the civr. after the iack bit is set, the vector number that corresponds to this interrupt is made available to the core in the civr and the interrupt request is cleared. if there are remaining interrupt requests, they are then prioritized and another interrupt request can be presented to the core. upon interruption, the interrupt mask bit in the machine status register (msr) is cleared to disable further interrupt requests until the software is ready to handle them. refer to section 6.4.1.2.1 machine state register for more information. the cisr can be used to allow a higher priority interrupt within the same interrupt level to be presented to the core before a lower priority interrupt service is completed. each bit in the cisr corresponds to a cpm interrupt source. when the core acknowledges the interrupt by setting the iack bit of the civr, the bits in the cisr are set by the cpm interrupt controller for that interrupt source. setting the bit prevents any subsequent cpm interrupt requests at this priority level or lower, until the servicing of the current interrupt has completed and you clear the in-service bit. pending interrupts for these sources are still set in the cpm interrupt controller, which means that, in the interrupt service routine for the cpm interrupts, you can enable the core interrupt mask to allow higher priority interrupts within this level to generate an interrupt request. this capability provides nesting of interrupt requests for cpm interrupt level sources. 16.15.3 masking interrupt sources in the cpm by programming the cpm interrupt mask register (cimr), you can mask the cpm interrupts to prevent an interrupt request to the core. each bit in the cimr corresponds to one of the cpm interrupt sources. to enable an interrupt, write a 1 to the corresponding cimr bit. when a masked cpm interrupt source has a pending interrupt request, the corresponding bit in the cipr is still set, even though the interrupt is not generated to the core. by masking all interrupt sources in the cimr, you can implement a polling interrupt servicing scheme for the cpm interrupts. when a cpm interrupt source has multiple interrupting events, you can individually mask these events by programming a mask register within that block. table 16-46 shows the interrupt sources that have multiple interrupting events and figure 16-136 illustrates an example of how the masking occurs using scc2 as an example.
communication processor module motorola mpc823e reference manual 16-504 cpic communication 16 processor module 16.15.4 generating and calculating an interrupt vector all pending unmasked cpm interrupts are presented to the core in order of priority. the core responds to an interrupt request by setting the iack bit in the civr. the interrupt vector that allows the core to locate the interrupt service routine is made available to the core by reading the civr. for cpm interrupts, the cpm interrupt controller passes an interrupt vector corresponding to the unmasked pending interrupt of the highest priority. the cpm interrupt controller encoding of the five low-order bits of the interrupt vector is shown in table 16-46. figure 16-136. interrupt request masking scce event bit sccm mask bit 13 input or (13 event bits) cipr cimr mask bit 28 input or (28 cipr bits) request to the imb at the level specified in irl2?rl0 in the cicr.
communication processor module 16-505 mpc823e reference manual motorola cpic communication 16 processor module table 16-46. encoding the interrupt vector interrupt number interrupt source description interrupt vector 1f parallel i/opc15 11111 1e usb 11110 1d scc2 11101 1c scc3 11100 1b reserved 11011 1a parallel i/opc14 11010 19 timer 1 11001 18 parallel i/opc13 11000 17 parallel i/opc12 10111 16 sdma channel bus error 10110 15 idma1 10101 14 idma2 10100 13 reserved 10011 12 timer 2 10010 11 risc timer table 10001 10 i 2 c 10000 f parallel i/opc11 01111 e parallel i/opc10 01110 d reserved 01101 c timer 3 01100 b parallel i/opc9 01011 a parallel i/opc8 01010 9 parallel i/opc7 01001 8 reserved 01000 7 timer 4 00111 6 parallel i/opc6 00110 5 spi 00101 4 smc1 00100 3 smc2 00011 2 parallel i/opc5 00010 1 parallel i/opc4 00001 0 error 00000
communication processor module motorola mpc823e reference manual 16-506 cpic communication 16 processor module the interrupt vector table is the same as the cpm interrupt priority table, except for two differences. first, the usb and sccx vectors are fixed. they are not affected by the usb and sccx group mode, spread mode, or the relative priority order of the usb and sccs. second, an error vector is the last entry in this table. the error vector is issued by the communication processor module if there were no other pending interrupts or if it requested one, but you masked it before it was serviced by the core. you must provide an error interrupt service routine, even if it is simply an rfi instruction. 16.15.5 programming the cpm interrupt controller 16.15.5.1 cpm interrupt configuration register. the 24-bit read/write cpm interrupt configuration register (cicr) defines the request level for the cpm interrupts, the priority between the usb and sccs and the highest priority interrupt. bits 0C7 and 25C30reserved these bits are reserved and must be set to 0. scdpsccd priority order this field defines whether the usb or sccs will assert a request in the sccd priority position. 00 = usb will assert its request in the sccd position. 01 = scc2 will assert its request in the sccd position. 10 = scc3 will assert its request in the sccd position. 11 = neither the usb or sccx will assert its request in the sccd position. cicr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved scdp sccp scbp scap reset 0 0000 r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x940 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field irl0 irl1 irl2 hp0 hp1 hp2 hp3 hp4 ien reserved sps reset 000000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x942
communication processor module 16-507 mpc823e reference manual motorola cpic communication 16 processor module sccpsccc priority order this field defines whether the usb or sccs will assert a request in the sccc priority position. 00 = usb will assert its request in the sccc position. 01 = scc2 will assert its request in the sccc position. 10 = scc3 will assert its request in the sccc position. 11 = neither the usb or sccx will assert its request in the sccc position. scbpsccb priority order this field defines whether the usb or sccs will assert a request in the sccb priority position. 00 = usb asserts its request in the sccb position. 01 = scc2 asserts its request in the sccb position. 10 = scc3 will assert its request in the sccb position. 11 = neither the usb or sccx will assert its request in the sccb position. scapscca priority order this field defines whether the usb or sccs will assert a request in the scca priority position. 00 = usb asserts its request in the scca position. 01 = scc2 asserts its request in the scca position. 10 = scc3 will assert its request in the scca position. 11 = neither the usb or sccx will assert its request in the scca position. irlinterrupt request level this field contains the priority request level of the interrupt from the communication processor module that is sent to the core. level 0 indicates the highest priority interrupt and level 7 indicates the lowest. the irl field is initialized to zero during reset. in most systems, value 0x4 is a good value to choose for these bits. 000 = highest priority interrupt. 111 = lowest priority interrupt. hphighest priority this field specifies the 5-bit interrupt number of the single cpm interrupt controllers interrupt source that is advanced to the highest priority in the table. these bits can be dynamically modified. to keep the original priority order intact, simply program these bits to 11111. note: you must not program the usb or sccs to more than one priority position (a, b, c, or d). these bits may be changed dynamically.
communication processor module motorola mpc823e reference manual 16-508 cpic communication 16 processor module ieninterrupt enable this bit is a master enable for the cpm interrupts. 0 = cpm interrupts are disabled. 1 = cpm interrupts are enabled. spsspread priority scheme this bit selects the relative usb and sccx priority scheme and cannot be changed dynamically. 0 = grouped. the usb and sccs are grouped by priority at the top of the table. 1 = spread. the usb and sccs are spread by priority in the table. 16.15.5.2 cpm interrupt pending register. each bit in the 32-bit read/write cpm interrupt pending register (cipr) indicates which cpm interrupt sources require interrupt service. when a cpm interrupt is received, the cpm interrupt controller sets the corresponding bit in the cipr. in a vectored interrupt scheme, the cpm interrupt controller clears the bit in the cipr that corresponds to the current interrupt when the core acknowledges the interrupt. the core acknowledges the interrupt by setting the iack bit in the civr. the vector number that corresponds to the cpm interrupt source is then available to the core in the civr. however, the cipr bit is not cleared if an event register exists for that interrupt source. event registers only exist for interrupt sources that have multiple source events. for example, the serial communication controllers have multiple events that cause sccx interrupts. cipr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pc15 usb scc2 scc3 res pc14 timer 1 pc13 pc12 sdma idma1 idma2 res timer 2 rCtt i2c reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x944 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field pc11 pc10 res timer 3 pc9 pc8 pc7 res timer 4 pc6 spi smc1 smc2 pc5 pc4 res reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x946
communication processor module 16-509 mpc823e reference manual motorola cpic communication 16 processor module in a polled interrupt scheme, you must periodically read the cipr. when a pending interrupt is handled, clear the corresponding bit in the cipr. however, if an event register exists, clear the unmasked event register bits instead, thus causing the cipr bit to be cleared. to clear a bit in the cipr, write a 1 to that bit. since you can only clear bits in this register, bits written as zeros are unaffected. the cipr is cleared at reset. 16.15.5.3 cpm interrupt mask register. each bit in the 32-bit read/write cpm interrupt mask register (cimr) corresponds to a cpm interrupt source. you can mask an interrupt by clearing the corresponding bit in the cimr and you can enable one by setting the corresponding bit in the cimr. when a masked cpm interrupt occurs, the corresponding bit in the cipr is still set, regardless of the cimr bit, but no interrupt request is passed to the core. if a cpm interrupt source is requesting interrupt service when you clear its corresponding bit in the cimr, the request stops. if you set its bit in the cimr later, a previously pending interrupt request is processed by the core, according to its assigned priority. you can read the cimr at any time and it is cleared by reset. note: the usb or sccx cipr bit positions are not changed according to the relative priority between the usb or sccs (as determined by the scxp and sps bits in the cicr). writing a zero to a bit in the cipr has no effect. cimr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pc15 usb scc2 scc3 res pc14 timer 1 pc13 pc12 sdma idma1 idma2 res timer 2 rCtt i2c reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x948 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field pc11 pc10 res timer 3 pc9 pc8 pc7 res timer 4 pc6 spi smc1 smc2 pc5 pc4 res reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x94a
communication processor module motorola mpc823e reference manual 16-510 cpic communication 16 processor module 16.15.5.4 cpm interrupt in-service register. each bit in the 32-bit read/write cpm interrupt in-service register (cisr) corresponds to a cpm interrupt source. in a vectored interrupt environment, the cpm interrupt controller sets the cisr bit when the core acknowledges the interrupt by setting the iack bit in the cpm interrupt vector register. your interrupt service routine must clear this bit after servicing is complete. if an event register exists for this peripheral, its bits would normally be cleared as well. to clear a bit in the cisr, write a 1 to that bit. since you can only clear bits in this register, bits written as zeros will not be affected. the cisr is cleared by reset. you can read this register to determine the interrupt requests that are currently in progress for each cpm interrupt source. more than one bit in the cisr can be a 1 if higher priority cpm interrupts are allowed to interrupt lower priority level interrupts within the same cpm interrupt level. for example, the timer1 interrupt routine could interrupt the handling of the timer2 routine using a special nesting technique described earlier. during this time, you can see both the timer2 and the timer1 bits simultaneously set in the cisr. note: the usb or sccx cimr bit positions are unaffected by the relative priority between the usb or sccs. to clear bits that were set by multiple interrupt events, you must clear all the unmasked events in the corresponding event register. if a bit in the cimr is masked at the same time that the corresponding cipr bit causes an interrupt request to the core, then the interrupt is not processed, but the error vector is issued if the interrupt acknowledge cycle occurs with no other cpm interrupts pending. thus, you must always include an error vector routine, even if it just contains the rfi instruction. the error vector cannot be masked. cisr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pc15 usb scc2 scc3 res pc14 timer 1 pc13 pc12 sdma idma1 idma2 res timer 2 rCtt i2c reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x94c bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field pc11 pc10 res timer 3 pc9 pc8 pc7 res timer 4 pc6 spi smc1 smc2 pc5 pc4 res reset 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x94e
communication processor module 16-511 mpc823e reference manual motorola cpic communication 16 processor module 16.15.5.5 cpm interrupt vector register. the cpm interrupt vector register (civr) is a 16-bit register. bits 0-4 of the register contain the interrupt vector number. to update the register with the current interrupt vector number, the core must set the iack bit. the bit is cleared after one clock cycle. the register can be read at any time. 16.15.6 interrupt handling examples you can use the following examples to learn how to properly handle cpm interrupts. 16.15.6.1 pc6 interrupt handler example. in this example, the cpm interrupt controller hardware clears the pc6 bit in the cipr during the interrupt acknowledge cycle. use the following steps to handle an interrupt source without multiple events. 1. set the iack bit in the civr. 2. read the vector to access the interrupt handler. 3. handle the event associated with a change in the state of the pc6 pin. 4. clear the pc6 bit in the cisr. 5. execute the rfi instruction. note: the usb or sccx cisr bit positions are not affected by the relative priority between the usb or sccs. if the error vector is taken, no bit in the cisr is set. all undefined bits in the cisr return zeros when read. you can control the extent to which cpm interrupts can interrupt other cpm interrupts by selectively clearing the cisr. a new interrupt is processed if it has a higher priority than the higher priority interrupt having its cisr bit set. thus, if an interrupt routine sets the interrupt mask bit in the core and also clears its cisr bit at the beginning of the interrupt routine, a lower priority interrupt can interrupt the higher one, as long as the lower priority interrupt is of higher priority than any other cisr bits that are currently set. civr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field vector number reserved iack reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x930
communication processor module motorola mpc823e reference manual 16-512 cpic communication 16 processor module 16.15.6.2 usb interrupt handler example. in this example, the usb bit in the cipr remains set as long as one or more unmasked event bits remain in the usbe register. this is an example of a handler for an interrupt source with multiple events. notice that the usb bit in the cipr does not need to be cleared by the handler, but the usb bit in the cisr does. 1. set the iack bit in the civr. 2. read the vector to access the interrupt handler. 3. immediately read the usbe register into a temporary location. 4. choose the events in the usbe that will be handled in this handler and clear them. the usbe bits are cleared by writing ones. 5. handle the events in the usb rx or tx buffer descriptor tables. 6. clear the usb bit in the cisr. 7. execute the rfi instruction. if any unmasked bits (those not cleared by the software or set by the mpc823e during the execution of this handler) in the usbe remain at this time, this interrupt source is pending again after the rfi instruction.
motorola mpc823e reference manual 17-1 pcmcia interface 17 section 17 pcmcia interface the pcmcia host adapter module provides all control logic for a pcmcia interface. only the analog power switching logic and buffering needs to be provided externally. the pcmcia host supports one pcmcia socket. 17.1 features the following list summarizes the main features of the pcmcia interface: ? a host adapter interface fully compliant with the pcmcia standard, release 2.1+ (pc card -16). ? supports one pcmcia socket, requiring only external buffering and analog switching logic. the socket is referred to as slot b to maintain compatibility with the mpc821 microprocessor. ? supports eight memory or i/o windows. ? provides eight general-purpose i/o pins when the pcmcia controller is not operating. ? provides two general-purpose output-only pins when the pcmcia controller is not operating. 17.2 system configuration the pcmcia host adapter interface module can control one pcmcia socket, which is illustrated in figure 17-1. in this system configuration, you must accomplish electrical isolation between the sockets and system bus using external buffers and bus transceivers. these buffers also provide the voltage conversion needed from the mpc823es 3.3v to 5v cards. they must be powered by the card v cc . since the mpc823e is 5v friendly and will accept 5v inputs while generating 3.3v outputs, no conversion is needed for inputs.
pcmcia interface 17-2 mpc823e reference manual motorola pcmcia interface 17 figure 17-1. system with one pcmcia socket 5 d[8:15] d[0:7] ce2_b ce1_b ale_b data_b[7:0] data_b[15:8] r/w rdy/bsy_b, bvd1_b,bvd2_b we /pgm_b address_b[25:0] ce1_b ce2_b 3v 12v socket max 780a a[6:31] 8 8 1 1 26 1 1 1 vcc_b vpp1_b 5v 1 vpp2_b we /pgm reg_b 1 reg oe_b 1 oe (iord_b ),(iowr_b ) 2 (iord ),(iowr ) reset_b 2 spkrout pcmcia host adapter b module 1 1 26 3 1 1 1 2 2 8 8 1 1 6 1 or equiv. wait_b , iois16_b 2 power on indication poe_b 1 irq 1 1 buffer with oe transparent latch with oe transceiver buffer with oe cd1_b, cd2_b, vs1_b, vs2_b 4 1 csi chip vdd vcc_b
pcmcia interface motorola mpc823e reference manual 17-3 pcmcia interface 17 17.3 pcmcia signals the pcmcia module consists of the cycle control, input port, output port, and various other signals. 17.3.1 the pcmcia cycle control signals the following signals are used for i/o accesses to the pcmcia card: ? address bus (a[6:31])output. these signals must be buffered to generate the sockets a25 through a0 signals, which are address bus output lines that allow direct addressing of up to 64m of memory on the pcmcia card. signal a6 is the most-significant bit and a31 is the least-significant bit. ? attribute memory select (reg )output. when this signal is asserted during a pcmcia access, card access is limited to attribute memory when a memory access occurs (we or oe are asserted), and to i/o ports when an i/o access occurs (iord or iowr are asserted). on accesses with reg asserted, accesses to common memory or dma devices are blocked. when no pcmcia access is performed, this signal is tsiz0. ? card enables (ce1_b , ce2_b )output. when a pcmcia access is performed, the ce1 and ce2 signals are card enable output signals. the ce1 signal enables even bytes and ce2 enables odd bytes. the cex signals can be configured to duplicate the values of the a[22:23] signals. at the end of the pcmcia access, these lines will be always negated. see table 17-1 for details. this feature can be used to access devices supporting ide/ata protocols. table 17-1. card enable as driven by the mpc823e prs field a22 a23 port size access size mpc823e: a31 (slot: a0) ce2 ce1 prs 1 110 x x 8 bits 16 bit (only even) 0 1 0 8 bit odd 1 1 0 8 bits even 0 1 0 16 bits 16 bit (only even) 0 0 0 8 bit odd 1 0 1 8 bits even 0 1 0 no access x 1 1 prs = 110 0 0 x x x 0 0 01 x x x 0 1 10 x x x 1 0 11 x x x 1 1
pcmcia interface 17-4 mpc823e reference manual motorola pcmcia interface 17 ? data bus (d[0:15])bidirectional. signals d0 through d15 constitute the bidirectional data bus. the most-significant bit is d0. significance decreases downward to d15. ? extend bus cycle (wait_b )input. this signal is asserted by the pc card to delay completion of the pending memory or i/o cycle. ? external transceiver direction (r/w )output. this signal is part of the mpc823e bus. it is asserted or driven high during any read cycles of the mpc823e and negated or driven low during write cycles. it is used in the pcmcia interface to control the direction of the data bus transceivers. ? i/o read (iord_b )output. during pcmcia accesses, this signal is asserted in conjunction with reg_b . it is used to read data from the pc cards i/o space. iord _b is valid only when the reg_b and at least one of ce1_b and ce2_b signals is asserted. ? i/o write (iowr_b )output. during pcmcia accesses, this signal is asserted in conjunction with reg_b . it is used to latch data into the pc cards i/o space. iowr _b is valid only when the reg _b and at least one of the ce1_b and ce2_b signals is asserted. ? output enable (oe_b )output. during pcmcia accesses, the oe_b signal is used to drive memory read data from a pc card into the pcmcia socket. ? write enable/program (we_b )output. during pcmcia accesses, the we_b signal is used to latch memory write data to a pc card in the pcmcia socket. this signal can also be used as the programming strobe for pc cards employing programmable memory technologies. ? address latch enable (ale_b)output. this strobe signal controls the external buffers of the address and reg signals. ? i/o port is 16 bits (iois16_b )input. when the card and its socket are programmed for i/o interface operation, this signal is used as iois16_b and must be asserted by the card when the address on the bus corresponds to an address on the pc card and the i/o port being addressed is capable of 16-bit accesses. if the i/o region in which the address resides is programmed as 8 bits wide, then the iois16_b signal is ignored.
pcmcia interface motorola mpc823e reference manual 17-5 pcmcia interface 17 17.3.2 the pcmcia input port signals the mpc823e provides synchronization, transition detection, optional interrupt generation and a means for the software to read the signal state. this function is not necessarily specific to pcmcia and the signals can be used as a general-purpose input port with edge detection and interrupt capability. the following signals are used by a pcmcia slot to indicate the status of the card. they appear on the ip_b[0:7] pins, which you can access through bits 16-23 of the pipr when you are not operating the pcmcia controller. all these signals are symmetrical, except for ip_b7, which has extended edge detection capability, and ip_b2 that serves as iois16_b cycle control signals for pcmcia cycles. ? voltage sense (vs1_b , vs2_b )input. these signals are used as vs1 and vs2 and are generated by pc cards. they notify the socket of the cards v cc requirement. these signals are connected to the ip_b[0:1] pins. ? write protect (wp)input. when the card and its socket are programmed for memory interface operation, wp reflects the status of the write protect switch on the pc card. it must be asserted by the pc card when the switch is enabled and negated when the switch is disabled. for a pc card without a switch, this signal must be connected to ground if the pc card can be written and connected to system v cc if the pc card is permanently write-protected. this signal is connected to the ip_b2 pin. ? card detect (cd2_b , cd1_b )input. these signals ensure that a card has been inserted properly. they must be connected to ground internally on the pc card and they will be forced low whenever a card is placed in the socket. these signals must be pulled up to system v cc to allow card detection to function while the card socket is powered down. these signals are connected to the ip_b3 and ip_b4 pins, respectively. ? battery voltage detect (bvd2_b, bvd1_b)input. when the card and its socket are programmed for memory interface operation, these signals are generated by pc cards with an onboard battery. they report the batterys condition. both bvd1_b and bvd2_b must be held asserted when the battery is in good condition. negating bvd2_b while keeping bvd1_b asserted indicates the battery is in a warning condition and must be replaced, although data integrity on the card is still assured. negating bvd1_b indicates that the battery is no longer serviceable and data is lost, regardless of the state of bvd2_b. these signals are connected to the ip_b5 and ip_b6 pins, respectively. ? status change (stschg )input. when the card and its socket are programmed for i/o interface operation, the bvd1_b signal is used as stschg , it is generated by the i/o pc card. the stschg signal must be held negated when the signal on change bit and changed bit in the card status register on the pc card are set to zero. the stschg signal must be asserted when both bits are set to one.
pcmcia interface 17-6 mpc823e reference manual motorola pcmcia interface 17 ? speaker (spkr )input. when the card and its socket are programmed for i/o interface operation, the bvd2_b signal is used as spkr and it is generated by the i/o pc cards. the spkr signal must be used to provide the sockets single amplitude (digital) audio waveform to the system. the spkr signal is routed out the spkrout signal if the card and its socket are programmed for i/o interface operation. ? ready/busy/interrupt request (rdy/bsy_b/ireq_b )input. when the card and its socket are programmed for memory interface operation, this signal is used as rdy/ bsy_b and must be asserted low by a pc card to indicate that the pc card is busy processing a previous write command. when the card and its socket are programmed for i/o operation, this signal is used as ireq_b and must be asserted low to generate an interrupt. this signal must be set high when no interrupt is requested. this signal is connected to the ip_b7 pin. 17.3.3 the pcmcia output port signals the following signals are used by a pcmcia slot to control the reset signal to the card and the output enable of the buffers to the card. the mpc823e allows software to control the output signal state. this function is not necessarily specific to the pcmcia interface and these signals, which appear on the op[2:3] pins, may be used by a system as a general- purpose output port. the op[2:3] pins, when they are not operating the pcmcia controller, can be accessed as general-purpose outputs through the cboe and cbreset bits of the pgcrb register. ? card reset (reset_b)output. this signal is provided to clear the card configuration option register residing on the card, thus placing the card in its default (memory-only interface) state and initiating the beginning of any additional card initialization. reset_b is connected to the op3 pin. ? pcmcia buffers output enable (poe_b )output. this line is an output port line reflecting the value of the cboe bit in the pcmcia interface power control register. it must be used to three-state the address and strobe pins addressing the slot. poe_b is connected to the op2 pin. 17.3.4 other pcmcia signals the following special function signals can be used by the pcmcia socket or by the system for other purposes. ? power is on (irq )input. one irq signal provided for general-purpose interrupt requests may be used by the card power supply circuitry to notify the mpc823e processor when the power supply to the card has reached the required voltage. ? speaker out (spkrout)output. this signal is used to provide a digital audio waveform that is to be driven to the systems speaker. it is generated from the spkr input port signal exclusive-ored with the output from timer 1. see section 16.4.2 timer operation for more information.
pcmcia interface motorola mpc823e reference manual 17-7 pcmcia interface 17 17.4 pcmcia operation 17.4.1 memory-only cards table 17-2 shows a worst case example of host programming. table 17-2 assumes you are not using the wait_b signal. if you are using it, then the minimum strobe time is at least 35ns + 1 system clock. 17.4.2 i/o cards table 17-3 shows a worst case example of programming pcmcia host for i/o cycle. setup time worst case is for write, so setup = data_setup_before_iord +1 system clock. table 17-2. host programming for memory cards memory access time 600ns 200ns 150ns 100ns stp lng hld stp lng hld stp lng hld stp lng hld clk cycle 100 300 150 30 120 90 20 80 75 15 60 50 20ns 6 24 8 2 8 5 2 6 4 1 4 3 30ns 4 16 5 2 5 3 1 4 3 1 3 2 40ns 3 12 4 1 4 3 1 3 2 1 2 2 62ns 2 8 3 1 2 2 1 2 2 1 1 1 83ns 2 6 2 1 2 2 1 1 1 1 1 1 note: because the minimum hold time is one clock, the real access time is access time plus one clock. hold time and setup time hld and stp, in this table, are the read or write worst case. the worst case hold time is data disable from oe . the worst case setup time is address to strobe. length (lng) is the minimum strobe time. table 17-3. host programming for i/o cards stp(1) lng hld 20ns 4 8 2 30ns 3 6 1 40ns 3 4 1 62ns 2 3 1 83ns 2 2 1
pcmcia interface 17-8 mpc823e reference manual motorola pcmcia interface 17 17.4.3 interrupts each input from the pcmcia card to the host (bvd, cd, rdy and vs) is sampled in the pcmcia interface input pins register (pipr) and any change to these bits is reported in the pcmcia interface status change register (pscr). the contents of the pscr is anded with the pcmcia interface enable register (per) to generate a pcmcia interface interrupt. you can program the interrupt level for the exception that is generated. the pcmcia interface can generate an additional interrupt for the rdy/irq signal. this interrupt can be generated for level (low or high) and for change (fall or rise) of the input signal. 17.4.4 power control you can perform a write cycle using one of memory controllers cs signals to operate an external device that provides a regulated source voltage to the pcmcia slot. there are a number of such devices available. however, auto-power control is not supported. 17.4.5 reset and three-state control you can write to the right bit in the pcmcia general interface control register b (pgcrb) and cause the pcmcia card to be reset or to disable the output drive of the external latches. 17.4.6 dma the mpc823es dma module with the cpm microcode provides two independent dma channels. the pcmcia module can be programmed to generate control for an i/o device implemented as a pcmcia card to act on a dma transfer. refer to the pcmcia 2.1 specification for more information. you can use the prs field in the appropriate pcmcia option register to program any window to be a dma window. the pcmcia controller supplies the signaling for the socket. dma to or from the pcmcia interface is accomplished with dual-address dma transfers. dma requests can be supplied through the spkr , iois16_b or inpack signals. the signal that is used depends on the card that is in the slot. to support the dma function across all cards, the implemented slots inpack signal must be connected to the dreq2 signal. to support the dma function, the slots inpack must be connected to dreq2 . the actual source used for a dma request is programmed in the cbdreq[0:1] field of the pgcrb register. if the internal dma request is enabled, then port c must not be programmed to dreq2 . when the internal dma request is disabled, then the dma request is assumed to be dreq2 . in this case, you must program port cs pc14 to dreq2 . note: the pcmcia controller will internally monitor the sdack2 signal to meet the idma handshaking protocol. therefore, you do not have to monitor this signal for your pcmcia design.
pcmcia interface motorola mpc823e reference manual 17-9 pcmcia interface 17 17.5 programming the pcmcia interface the following section describes the pcmcia interface programming model. all registers are memory-mapped within the internal control register area. the following registers are used to control the pcmcia interface. 17.5.1 pcmcia interface input pins register the pcmcia interface input pins register (pipr) is used to sample the pcmcia input port signals. when the pcmcia controller is not operating, bits 16-23 of the pipr can be used to read from and write to the ip_b[0:7] pins as general-purpose i/o pins. bits 0C15reserved these bits are reserved and must be set to 0. figure 17-2. internal dma request logic pipr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset r/w r/w addr (immr & 0xffff0000) + 0xf0 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field cbvs1 cbvs2 cbwp cbcd2 cbcd1 cbbvd 2 cbbvd 1 cbrdy reserved reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xf0 note: = undefined. iois16_b spkr dreq2 cbdreq1 cbdreq2 internal dma request multiplexer port c logic port c dreq2
pcmcia interface 17-10 mpc823e reference manual motorola pcmcia interface 17 cbvs1 card b voltage sense 1 0 = card b cannot operate at 3.3v. 1 = card b can operate at 3.3v. cbvs2 card b voltage sense 2 this bit is reserved by the pcmcia controller for a secondary operating voltage. it must normally be set to 1 by card b. cbwp card b write-protect 0 = card b is not write-protected. you cannot write to it. 1 = card b is write-protected. cbcd2 card b card detect 2 0 = card b is fully connected in socket. 1 = card b is not properly connected in socket. cbcd1 card b detect 1 0 = card b is fully connected in socket. 1 = card b is not properly connected in socket. cbbvd2card b battery voltage 2/spkr if card b and its socket are configured for i/o interface operation, this bit reflects the value of the spkr signal. if card b and its socket are configured for memory interface operation and card b has an onboard memory, cbbvd2 is: x0 = card b battery is no longer serviceable and data is lost. 01 = card b battery is in a warning condition and must be replaced. card b data integrity is still assured. 11 = card b battery is in good condition. cbbvd1card b battery voltage 1/stschg if card b and its socket are configured for i/o interface operation, this bit reflects the value of the stschg signal. if card b and its socket are configured for memory interface operation and card b has an onboard memory, cbbvd1 is: x0 = card b battery is no longer serviceable and data is lost. 01 = card b battery is in a warning condition and must be replaced. card b data integrity is still assured. 11 = card b battery is in good condition. cbrdycard b rdy/bsy_b/ireq_b /irq if card b and its socket are configured for memory interface operation, cbrdy is: 0 = card b is busy. 1 = card b is ready to accept a new data transfer operation.
pcmcia interface motorola mpc823e reference manual 17-11 pcmcia interface 17 if card b and its socket are configured for i/o interface operation or if the cards power supply circuitry is using the irq signal, cbrdy is: 0 = card b is requesting an interrupt. 1 = card b is not requesting an interrupt. bits 24C31reserved these bits are reserved and must be set to 0. 17.5.2 pcmcia interface status change register the pcmcia interface status change register (pscr) records changes in the state of the pcmcia input port signals. this register is reset by writing ones to it (writing zero has no effect). however, bits 24 and 25 are level-triggered. to clear them, the external source of the interrupt must be cleared. bits 0C15reserved these bits are reserved and must be set to 0 cbvs1_ccard b voltage sense 1 change 0 = signal is changed. 1 = signal is unchanged. cbvs2_ccard b voltage sense 2 change 0 = signal is changed. 1 = signal is unchanged. pscr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset r/w r/w addr (immr & 0xffff0000) + 0xe8 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field cbvs1 _c cbvs2 _c cbwp_ c cbcd2 _c cbcd1 _c cbbvd 2_c cbbvd 1_c res cbrdy _l cbrdy _h cbrdy _r cbrdy _f reserved reset r/w r/w addr (immr & 0xffff0000) + 0xe8 note: = undefined.
pcmcia interface 17-12 mpc823e reference manual motorola pcmcia interface 17 cbwp_ccard b write-protect change 0 = signal is changed. 1 = signal is unchanged. cbcd2_ccard b card detect 2 change 0 = signal is changed. 1 = signal is unchanged. cbcd1_ccard b card detect 1 change 0 = signal is changed. 1 = signal is unchanged. cbbvd2_ccard b battery voltage 2/spkr change 0 = signal is changed. 1 = signal is unchanged. cbbvd1_ccard b battery voltage 1/stschg change 0 = signal is changed. 1 = signal is unchanged. bit 23reserved this bit is reserved and must be set to 0. cbrdy_lcard b rdy/irq low 0 = signal is changed. 1 = signal is unchanged. cbrdy_hcard b rdy/irq high 0 = signal is changed. 1 = signal is unchanged. cbrdy_rcard b rdy/irq rising edge 0 = signal is changed. 1 = signal is unchanged. cbrdy_fcard b rdy/irq falling edge 0 = signal is changed. 1 = signal is unchanged. bits 28C31reserved these bits are reserved and must be set to 0 note: writing logic one to each bit reset its value (zero), except for bit 9, which is always set to one. to reset the value of bits 24 and 25, you must remove the external source of the interrupt.
pcmcia interface motorola mpc823e reference manual 17-13 pcmcia interface 17 17.5.3 pcmcia interface enable register the pcmcia interface enable register (per) acts as a mask for the various sources of a pcmcia interrupt. interrupts caused by bits 16-22 are reported as cbschlvl interrupts, while interrupts caused by bits 24-27 are reported as cbirqlvl interrupts. bits 0C15reserved these bits are reserved and must be set to 0. cb_evs1card b enable for voltage sense 1 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_evs2card b enable for voltage sense 2 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_ewpcard b enable for write-protect 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_ecd2card b enable for card detect 2 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_ecd1card b enable for card detect 1 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. per bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved reset r/w r/w addr (immr & 0xffff0000) + 0xf8 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field cb_ev s1 cb_ev s2 cb_ew p cb_ec d2 cb_ec d1 cb_eb vd2 cb_eb vd1 res cb_er dy_l cb_er dy_h cb_er dy_r cb_er dy_f reserved reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xf8 note: = undefined.
pcmcia interface 17-14 mpc823e reference manual motorola pcmcia interface 17 cb_ebvd2card b enable for battery voltage/spkr 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_ebvd1card b enable for battery voltage/stschg 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. bit 23reserved this bit is reserved and must be set to 0. cb_erdy_lcard b enable for rdy/irq low 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_erdy_hcard b enable for rdy/irq high 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_erdy_rcard b enable for rdy/irq rising edge 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. cb_erdy_fcard b enable for rdy/irq falling edge 0 = disable interrupt on any change in the relevant pin. 1 = enable interrupt on changes in the relevant pin. bits 28C31reserved these bits are reserved and must be set to 0.
pcmcia interface motorola mpc823e reference manual 17-15 pcmcia interface 17 17.5.4 pcmcia interface general control register b the pcmcia interface general control register b (pgcrb) provides control for the ireq and stschg interrupt levels, this register also controls the pcmcia output port signals. when the pcmcia controller is not operating, the cboe and cbreset bits can be used to access the op[2:3] pins as general-purpose output pins without configuring any other pcmcia register. cbirqlvlcard b interrupt request level only one bit of this field must be set at any given time. cbschlvlcard b stschg level only one bit of this field must be set at any given time. cbdreqcard b dma request this field defines the pin to be used as the internal dma request to idma channel 2. 0x = disable internal dma request from slot b. 10 = enable iois16_b as internal dma request for slot b. 11 = enable spkr as internal dma request for slot b. bits 18C23reserved these bits are reserved and must be set to 0. pgcrb bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cbirqlvl cbschlvl reset r/w r/w r/w addr (immr & 0xffff0000) + 0xe4 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field cbdreq reserved cboe cbres et reserved reset r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xe4 note: = undefined. note: if the pcmcia controller is programmed to enable internal dma, then the port c registers must not be configured to select dreq2 .
pcmcia interface 17-16 mpc823e reference manual motorola pcmcia interface 17 cboecard b output enable the value of this bit is always reflected on the op2 pin. when the pcmcia controller is in active mode, poe_b is connected to the op2 pin. poe_b is used to three-state the address and strobe pins addressing the pcmcia card slot. refer to section 17.3.3 the pcmcia output port signals . 0 = poe_b is asserted if the pcmcia controller is active. 1 = poe_b is not asserted if the pcmcia controller is active. cbresetcard b reset the value of this bit is always reflected on the op3 pin. when the pcmcia controller is in active mode, reset_b is connected to the op3 pin. reset_b is used to place the pcmcia card in its default (memory-only interface) state, and initiate the beginning of any further card initialization. refer to section 17.3.3 the pcmcia output port signals . 0 = reset_b is not asserted if the pcmcia controller is active. 1 = reset_b is asserted if the pcmcia controller is active. bits 26C31reserved these bits are reserved and must be set to 0. 17.5.5 pcmcia base registers the pcmcia base registers 0C7 (pbr0-7) contain the pcmcia base addresses for the pcmcia memory or i/o windows. the base registers are used in conjunction with the bsize field of the corresponding pcmcia option register to ensure valid pcmcia accesses. pbapcmcia base address pbr0Cpbr7 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pba reset r/w r/w addr (immr & 0xffff0000) + 0x80 (pbr0), 0x88 (pbr1), 0x90 (pbr2), 0x98 (pbr3), 0xa0 (pbr4), 0xa8 (pbr5), 0xb0 (pbr6), 0xb8 (pbr7) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field pba reset r/w r/w addr (immr & 0xffff0000) + 0x80 (pbr0), 0x88 (pbr1), 0x90 (pbr2), 0x98 (pbr3), 0xa0 (pbr4), 0xa8 (pbr5), 0xb0 (pbr6), 0xb8 (pbr7) note: = undefined.
pcmcia interface motorola mpc823e reference manual 17-17 pcmcia interface 17 this field is compared to the address on the address bus to determine if a pcmcia window is being accessed by an internal bus master. these bits are used in conjunction with the bsize field in the por. 17.5.6 pcmcia option registers the pcmcia option registers 0-7 (por0-por7) control the size, timing parameters, and memory access to the individual pcmcia windows whose base addresses reside in the corresponding pcmcia base registers. bsizepcmcia bank size this field determines the bank size (the size of the address space in bytes) for the corresponding pcmcia window. the bank size is also used as an address mask and is applied to the pba field in the associated pcmcia base register to an address generated by an internal master. the bank size is calculated from bsize as: 00000 = 1 bytes. 00001 = 2 bytes. 00011 = 4 bytes. 00010 = 8 bytes. 00110 = 16 bytes. 00111 = 32 bytes. por0Cpor7 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field bsize reserved psht reset r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x84 (por0), 0x8c (por1), 0x94 (por2), 0x9c (por3), 0xa4 (por4), 0xac (por5), 0xb4 (por6), 0xbc (por7) bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field psst psl pps prs psl ot wp pv reset r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x84 (por0), 0x8c (por1), 0x94 (por2), 0x9c (por3), 0xa4 (por4), 0xac (por5), 0xb4 (por6), 0xbc (por7) note: = undefined. banksize 2 graycode bsize () =
pcmcia interface 17-18 mpc823e reference manual motorola pcmcia interface 17 00101 = 64 bytes. 00100 = 128 bytes. 01100 = 256 bytes. 01101 = 512 bytes. 01111 = 1k. 01110 = 2k. 01010 = 4k. 01011 = 8k. 01001 = 16k. 01000 = 32k. 11000 = 64k. 11001 = 128k. 11011 = 256k. 11010 = 512k. 11110 = 1m. 11111 = 2m. 11101 = 4m. 11100 = 8m. 10100 = 16m. 10101 = 32m. 10111 = 64m. the calculated bank size is used as a mask (mask) to determine a valid pcmcia address as follows: if ((address & mask) == (pba & mask)) valid pcmcia access else invalid pcmcia access
pcmcia interface motorola mpc823e reference manual 17-19 pcmcia interface 17 pshtpcmcia strobe hold time this attribute is used to determine when iowr_b or we_b are negated during a pcmcia write access or when iord_b or oe_b are negated during a pcmcia read access handled by the pcmcia interface. this helps meet address/data hold time requirements for slow memories and peripherals. 0000= strobe negation to address change 0 clocks. 0001= strobe negation to address change 1 clock. 0010= strobe negation to address change 2 clocks. 0011= strobe negation to address change 3 clocks. 0100= strobe negation to address change 4 clocks. 0101= strobe negation to address change 5 clocks. 0110= strobe negation to address change 6 clocks. 0111= strobe negation to address change 7 clocks. 1000= strobe negation to address change 8 clocks. 1001= strobe negation to address change 9 clocks. 1010= strobe negation to address change 10 clocks. 1011= strobe negation to address change 11 clocks. 1100= strobe negation to address change 12 clocks. 1101= strobe negation to address change 13 clocks. 1110= strobe negation to address change 14 clocks. 1111= strobe negation to address change 15 clocks. psstpcmcia strobe setup time this attribute is used to determine when iowr_b or we_b are asserted during a pcmcia write access or when iord_b or oe_b are asserted during a pcmcia read access handled by the pcmcia interface. this helps meet address/setup time requirements for slow memories and peripherals. 0000= reserved. 0001= address to strobe assertion 1 clock cycle. 0010= address to strobe assertion 2 clock cycles. 0011= address to strobe assertion 3 clock cycles. 0100= address to strobe assertion 4 clock cycles. 0101= address to strobe assertion 5 clock cycles. 0110= address to strobe assertion 6 clock cycles. 0111= address to strobe assertion 7 clock cycles. 1000= address to strobe assertion 8 clock cycles. 1001= address to strobe assertion 9 clock cycles. 1010= address to strobe assertion 10 clock cycles. 1011= address to strobe assertion 11 clock cycles. 1100= address to strobe assertion 12 clock cycles. 1101= address to strobe assertion 13 clock cycles. 1110= address to strobe assertion 14 clock cycles. 1111= address to strobe assertion 15 clock cycles.
pcmcia interface 17-20 mpc823e reference manual motorola pcmcia interface 17 pslpcmcia strobe length this attribute determines the number of cycles the strobe will be asserted during a pcmcia access for this window. it is the main parameter for determining the length of the cycle. the cycle may be lengthened by asserting the wait signal. 00001= strobe asserted 1 clock cycle. 00010= strobe asserted 2 clock cycles. 00011= strobe asserted 3 clock cycles. 00100= strobe asserted 4 clock cycles. 00101= strobe asserted 5 clock cycles. 00110= strobe asserted 6 clock cycles. 00111= strobe asserted 7 clock cycles. 01000= strobe asserted 8 clock cycles. 01001= strobe asserted 9 clock cycles. 01010= strobe asserted 10 clock cycles. 01011= strobe asserted 11 clock cycles. 01100= strobe asserted 12 clock cycles. 01101= strobe asserted 13 clock cycles. 01110= strobe asserted 14 clock cycles. 01111= strobe asserted 15 clock cycles. 10000= strobe asserted 16 clock cycles. 10001= strobe asserted 17 clock cycles. 10010= strobe asserted 18 clock cycles. 10011= strobe asserted 19 clock cycles. 10100= strobe asserted 20 clock cycles. 10101= strobe asserted 21 clock cycles. 10110= strobe asserted 22 clock cycles. 10111= strobe asserted 23 clock cycles. 11000= strobe asserted 24 clock cycles. 11001= strobe asserted 25 clock cycles. 11010= strobe asserted 26 clock cycles. 11011= strobe asserted 27 clock cycles. 11100= strobe asserted 28 clock cycles. 11101= strobe asserted 29 clock cycles. 11110= strobe asserted 30 clock cycles. 11111= strobe asserted 31 clock cycles. 00000= strobe asserted 32 clock cycles. ppspcmcia port size this field specifies the port size of this pcmcia window. 0 = 8-bit port size. 1 = 16-bit port size.
pcmcia interface motorola mpc823e reference manual 17-21 pcmcia interface 17 prspcmcia region select 000 = common memory space. 001 = reserved. 010 = attribute memory space. 011 = i/o space. 100 = dma (normal dma transfer. 101 = dma last transaction. 110 = drive the value of the a22 and a23 signals on ce2 and ce1 . 111 = reserved. the dma encoding will generate a normal dma transfer unless signaled as last by the on-chip dma controller. in this case, tc (oe ) or tc (we ) is asserted. the dma last transaction encoding will generate a dma transfer with tc (oe ) or tc (we ) asserted, regardless of any internal indication. pslotpcmcia slot identifier 0 = reserved. 1 = this window defined for slot b. wpwrite-protect 0 = this window is not write-protected. 1 = this window is write-protected. if you try to write to this window, a bus error (machine check interrupt) will occur. pvpcmcia valid this bit indicates that the contents of the pcmcia base register and option register pair are valid. 0 = this bank is invalid. 1 = this bank is valid
pcmcia interface 17-22 mpc823e reference manual motorola pcmcia interface 17 17.6 pcmcia controller timing examples figure 17-3. pcmcia single beat read cycle (prs = 0, psst = 1, psl = 3, psht = 1) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b pcoe wait_b ce [1:2] psst psl psht
pcmcia interface motorola mpc823e reference manual 17-23 pcmcia interface 17 figure 17-4. pcmcia single beat read cycle (prs = 0, psst = 2, psl = 4, psht = 1) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b pcoe wait_b ce [1:2] psst psl psht
pcmcia interface 17-24 mpc823e reference manual motorola pcmcia interface 17 figure 17-5. pcmcia single beat read cycle (prs = 0, psst = 1, psl = 3, psht = 0) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b pcoe wait_b ce [1:2] psst psl psht
pcmcia interface motorola mpc823e reference manual 17-25 pcmcia interface 17 figure 17-6. pcmcia single beat write cycle (prs = 2, psst = 1, psl = 3, psht = 1) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b pcwe wait_b ce [1:2] psst psl psht
pcmcia interface 17-26 mpc823e reference manual motorola pcmcia interface 17 figure 17-7. pcmcia single beat write cycle (prs = 3, psst = 1, psl = 4, psht = 3) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b iowr_b wait_b ce [1:2] psst psl psht iois16_b
pcmcia interface motorola mpc823e reference manual 17-27 pcmcia interface 17 figure 17-8. pcmcia single beat write with wait (prs = 3, psst = 1, psl = 3, psht = 0) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b iowr_b wait_b ce [1:2] psst psl psht wait delay
pcmcia interface 17-28 mpc823e reference manual motorola pcmcia interface 17 figure 17-9. pcmcia single beat read with wait (prs = 3, psst = 1, psl = 3, psht = 1) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b iord_b wait_b ce [1:2] psst psl psht wait delay
pcmcia interface motorola mpc823e reference manual 17-29 pcmcia interface 17 figure 17-10. pcmcia i/o read of a 16-bit slave port (pps = 1, prs = 3, psst = 1, psl = 2, psht = 0) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b iowr ce1 psst psht ce2 iois16_b psl
pcmcia interface 17-30 mpc823e reference manual motorola pcmcia interface 17 figure 17-11. pcmcia i/o read of an 8-bit slave port (pps = 1, prs = 3, psst = 1, psl = 2, psht = 0 clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b iowr ce1 psst psht ce2 iosi16_b psst psl psl psht
pcmcia interface motorola mpc823e reference manual 17-31 pcmcia interface 17 figure 17-12. pcmcia dma read cycle (prs = 4, psst = 1, psl = 3, psht = 0) clkout a[0:31] ts br bg bb data ta rd/wr burst reg ale_b iord size ce [1:2] psst psht size=word psl pcoe psst psl psht size=half at=0xf at=0xf
motorola mpc823e reference manual 18-1 lcd controller 18 section 18 lcd controller the mpc823e contains an on-chip lcd controller that can be used to drive an lcd panel display. the integrated lcd controller shortens access time, reduces power consumption, and saves system board space by not using external glue logic. the lcd controller can interface with a variety of passive, active, dual-scan, single-scan, and smart lcd panels. 18.1 features the following is a list of the lcd controllers main features: ? passive, active, and smart panel interfaces are supported ? requires no special display memory (uses system memory) ? one, two, or four bits per pixel in grayscale mode generates a maximum of 16 grayscale levels using an advanced frame rate control algorithm ? four or eight bits per pixel in color mode generates 16 or 256 simultaneous colors from 4,096 color patterns ? interfaces to the lcd panel through a 4-, 8-, or 12-bit parallel output bus ? supports single-scan or dual-scan screens ? supports many split display data modes ? requires no cpu or communication processor module intervention ? built-in 256-entry color ram ? programmable wait time between lines and frames ? programmable panel voltage control for brightness and contrast ? programmable polarity for all lcd interface signals ? tft/rgb output drives advanced buffer lcd driver chips ? bus performance optimized with burst read dma cycles
lcd controller 18-2 mpc823e reference manual motorola lcd controller 18 18.1.1 lcd technology a liquid crystal display (lcd) implements a low-power display technology that uses ambient light to display images. lcds consist of two pieces of glass with electrodes printed on the inside and polarizers are used on the external front and rear surfaces. when the lcd is off, no voltage is applied to the electrodes and light passes through the lcd. when it is on, voltage is applied to the electrodes and the liquid crystal molecules align themselves in the direction of the electric field. this causes the light to be blocked and out of phase with the polarizers, which creates a dark area on the lcd. this darkness is a function of the rms voltage applied to them. the polarity of the applied voltage is not important and no dc bias is allowed. a typical monochrome lcd module is illustrated in figure 18-1 below. the y drivers apply high voltage to one row at a time. at the same time, the x drivers connect the dark pixels to the opposing voltage and bright pixels to the same voltage as the row. the value of each pixel is shifted by the shift register and latched when the whole row is ready. while one row is being refreshed, the next row is being shifted in and each row is refreshed at a rate inverse to the number of rows. if the number of rows is large, then the refresh rate might become too small. when this occurs, the panel is divided into two sections (upper and lower). then the x shift register, which is twice as long, works at twice the speed to refresh two columns at the same time (one column in the upper section and one in the lower section). the x shift register can be loaded 1, 2, 4, or 8 bits per shift. figure 18-1. lcd panel shift register latch and (t/s) drive one-bit-shifter 640 columns 480 rows 4 / 8 bits shift latch preset shift backplane (common) drivers frontplane drivers single panel x y ( +20v / 0v ) ( 0v / +20v ) data three-state display
lcd controller motorola mpc823e reference manual 18-3 lcd controller 18 the time it takes to refresh a row is called the duty cycle. in a simple refresh policy, one row is refreshed at a time. however, this creates large voltage spikes on the lcd electrodes. another technique, called active addressing, refreshes groups of rows and smoothes the applied voltage that each pixel receives over approximately half a frame cycle. this significantly improves the contrast and other characteristics of a simple lcd display. the drawback of active addressing is that it is fairly complex and requires that you have a dedicated chip to perform it on. this chip holds a large display buffer (typically equivalent to a quarter of a vga display per circuit). the active addressing algorithm is done on entire columns and it usually fits in the lcd display path and appears to the system as a thin film transistor (tft) interface. it is important to avoid long-term dc bias in the voltages applied to the lcd screen because it causes defects in the polarization, as well as raindrop-like patterns (raindrop effect), to appear on the display. to overcome this problem, the controller changes the field polarity every few frames. 18.1.2 types of lcd interfaces basic lcd panels require a clock, one or more data input lines, and horizontal and vertical syncs. these signals are usually provided by an lcd controller that includes a frame buffer ram for display memory. an example of a complete lcd subsystem is illustrated in figure 18-2. figure 18-2. lcd subsystem frame buffer ram lcd array x-drivers y-drivers lcd controller cpu dc-dc converter lcd panel
lcd controller 18-4 mpc823e reference manual motorola lcd controller 18 18.1.2.1 passive lcd interface. a passive lcd panel interface uses x and y shift registers to operate. the x shift register is used to display a column and the y shift register is used to display a row. the lcd controller fills the shift register, provides framing, and reverses the display polarity from frame-to-frame or line-to-line. a passive lcd interface consists of several parallel data bits that are shifted into the x shift register by the shift clock. after the shift register is full, a latch signal transfers the pixels from the shift register to driver latches and moves the y pointer down one line. at this point, the shift operation continues to the next line and after all the lines are scanned, the frame signal moves the y pointer to the beginning of the frame. the lcd controller also accesses the frame buffer. the panel can be single- or dual-scan and the dual-scan function is accomplished by splitting the y dimension. for single-scan panels, the lcd controller only has one buffer. for dual-scan panels, the lcd controller must have one upper and one lower frame buffer. in most lcd panels, you need control to kill any dc biases that build up during normal operation. a signal that inverts the polarity of the voltages is presented to the lcd panel. usually, this signal toggles every few frames (1C20). figure 18-3. passive interfaces shift load frame d[0:x] passive single-scan shift load frame ud[0:x] ld[0:x] passive dual-scan x = [0, 3, 7] x= [1, 3] panel panel
lcd controller motorola mpc823e reference manual 18-5 lcd controller 18 18.1.2.2 active lcd interface. an active lcd panel interface is referred to as a thin film transistor (tft) interface. it provides a high-performance lcd panel that looks more like a digital rgb or monochrome video signal that has several data bits in parallel. the shift clock is also present. latch and frame signals are called horizontal sync and vertical sync and have special timing. there is also a special signal called output enable that blanks/enables data, but does not affect the clock. for color displays, the mpc823e supports a 12-bit (four bits per basic color) data bus. for example, an 8-bit pixel data fetched from the frame buffer is passed through a 256 x 12 memory that selects one out of 256 colors. 18.1.2.3 smart panel lcd interface. in a smart panel interface, the whole memory display buffer resides on the panel, which is directly connected to the system bus. also, the cpu accesses the display memory directly, so you do not need a controller. figure 18-4. active (tft) interface clk hsync vsync r[0:x] g[0:x] b[0:x] active (tft) panel x = [2, 3, 4]
lcd controller 18-6 mpc823e reference manual motorola lcd controller 18 18.2 the mpc823e lcd controller the mpc823e lcd controller is initialized by the core, which provides the frame buffer address, operational modes, and various configuration bits that the lcd controller needs to operate. after it is enabled, the lcd controller requests the dma to fetch the frame buffer data. the frame buffer is always organized in rows and columns. depending on the interface you are using, the data is then interpreted for grayness or color and frame format. the data is then packed according to the model you have chosen. if you are using a split panel display, you must initialize two buffersone for each panel display. the lcd controller uses continuous dma to feed the display. figure 18-5 illustrates a typical mpc823e lcd system. mpc823e figure 18-5. the mpc823e lcd system lcd controller lcd frame buffer panel dma system system bus core internal bus interface unit irq system ram
lcd controller motorola mpc823e reference manual 18-7 lcd controller 18 the mpc823e lcd controller is a module that is separate from the core and communication processor module. it uses the internal dma, bus, and system interface unit to access frame buffer memory. the lcd controller has dedicated registers that provide timing generation to control the panel. it also has two fifos that interface to color ram, which provides pixel generation and a data path to the panel. the lcd controller block diagram is illustrated in figure 18-6. figure 18-6. lcd controller block diagram lcd fifos control interface dma interface timing generation modes frame shift load lcd_ac lcd data dma address color ram registers
lcd controller 18-8 mpc823e reference manual motorola lcd controller 18 18.3 lcd controller operation the lcd controller uses the system interface unit to communicate with the core and external system. it has its own dma functionality to fetch display memory into the fifos for pixel generation. the lcdclk signal is derived from the spll output (vcoout) and is fed to the timing generator for vertical, horizontal, and frame timing. the register set is used to program the timing parameters for an lcd panel. figure 18-7 illustrates the various modules of the lcd controller. figure 18-7. lcd functional module fifoa fifob pixel horizontal control vertical control registers vcoout clock dma controller timing generator frame control generation dflcd dfalcd system interface unit eof irq lcd interface shift/clk lcd_ac/loe frame/vsync load/hsync ld[0:8] lcd_a lcd_b lcd_c lcdclk
lcd controller motorola mpc823e reference manual 18-9 lcd controller 18 after reset, the lcd controller is disabled (pon=0) in the lcd configuration and control register (lccr). to operate the lcd controller, you must program the lcd registers and set the pon bit. when enabled, the fifos ask the dma controller to fill them using burst read memory cycles. when data is available in the fifos, it is used to index into the color ram to produce a grayscale or color pattern. this pattern is then shifted out by the horizontal control block, which generates timing for each pixel on a line, including the wait between lines (wbl). the vertical control block counts the number of lines and provides a wait between frames (wbf) timing. the lcd controller consists of eight main blocks: ? fifos ? pixel generation ? horizontal control ? vertical control ? frame control ? dma control ? timing control ? lcd interface 18.3.1 fifo control there are two fifos in the lcd controller that are concatenated for single-scan displays and used separately for dual-scan displays. each fifo has the capacity to hold 12 32-bit words. when the fifo can accept a burst, it requests a dma controller access, which guarantees no fifo overflow. when the fifo is empty before frame completion and the dma cannot provide data because of heavy bus loading, a fifo underrun condition occurs. if such a condition occurs, the display image may flicker, tear, or shift. in order to recover, you must restart the lcd controller. it is your responsibility to make sure the lcd controller has sufficient bus bandwidth to avoid underrun conditions. when the data is available in the fifos, the frame controller initiates frame processing.
lcd controller 18-10 mpc823e reference manual motorola lcd controller 18 18.3.2 pixel generation the pixel generation block retrieves data from the fifos to generate a grayscale or color pattern by indexing into the color ram area of dual-port ram. for single-scan displays, data is fetched serially from both fifos. for dual-scan displays, data is fetched alternatively from both fifos. 18.3.2.1 grayscale. for single-bit grayscale (monochrome), each pixel is represented by a single bit in the frame buffer, also called the display buffer. a zero signifies pixel off and a one signifies pixel on. for fours bits per pixel, one pixel requires four bits in the memory that are packed together with the next four bits for the next pixel. the lcd controller can generate a maximum of 16 grayscale levels whereby each pixel is represented by four bits in the frame buffer. grayscale is generated by controlling the rate in which each pixel is turned off and on. this method is referred to as frame rate control (frc). turning the pixels on and off under frame rate control may result in a low frequency pixel refresh rate to a given pixel. this refresh rate may cause image flickering when the same gray level is found in adjacent pixels. however, the mpc823e-implemented frc algorithm must minimize this flicker. when one bit per pixel is defined, the color ram table is used as a transparent translation to pass the ram data through the lcd panel interface. when you are using two bits per pixel, the 2-bit code is indexed into the color ram to one of four entries. each of these four entries can be one of 16 possible gray level codes. these four entries are then used to determine the frc value for that pixel. with four bits per pixel, the 4- bit code is used to index one of 16 entries in the color ram. the 4-bit code from the color ram is then used to determine one of the 16 shades generated by frame rate control. figure 18-8 illustrates grayscale generation.
lcd controller motorola mpc823e reference manual 18-11 lcd controller 18 figure 18-8. grayscale generation display data one bit per pixel two bits per pixel (four shades) four bits per pixel (16 shades) (no grayscale) frc 01 1 4-bit code 011 1 0 1 0 * 0110 frc 4-bit code * note: * for each frame in a group of 16, 1 indicates this pixel is on and 0 indicates this pixel is off. color ram lcd interface (ld[1:8]) color ram (4 entries) (16 entries) transparent translation color ram (16 entries) 1 011 display data display data lcd pixel lcd pixel (see section 18.4.7.1 for more information)
lcd controller 18-12 mpc823e reference manual motorola lcd controller 18 18.3.2.2 color. each color pixel is represented as a 4- or 8-bit code in the frame buffer. using the color ram, the pixel code is mapped to a 12-bit red/green/blue (rgb) code, which allows you to select one of 4,096 colors. for passive color displays, the frame rate control algorithm processes each color to generate the required amount of intensity, as derived from the 12 bits (maximum) of rgb information in the color ram. for active color displays, 12 bits (4 bits per color) are output directly onto the lcd data bus. figure 18-9 illustrates color generation. notice that the lcd data bus is shown with msb on the left and lsb on the right. the lcd_a, lcd_b, and lcd_c bits are the least-significant bits of each color, figure 18-9. color generation r gb 011 111 100 color ram active display eight bits per pixel 0110 display data four bits per pixel 0000 0110 1 0 1 1 1 1 0 0 1 0 1 1 1 1 note: * for each frame in a group of 16, 1 indicates this color pixel is on and 0 indicates this color pixel is off. passive display 0110 0000 0110 r gb 011 111 100 110 display data display data display data 0 eight bits per pixel four bits per pixel (256 entries) frc frc frc *** lcd pixel (red) (green) (blue) ld0 lcd_a lcd_b lcd_c ld8 ld7 ld6 ld5 ld4 ld3 ld2 ld1
lcd controller motorola mpc823e reference manual 18-13 lcd controller 18 18.3.3 horizontal control the horizontal control block tracks the pixel count for one line and any additional wait between lines. it also enables the pixel generation block by passing a signal from the vertical control block to each line. upon completion of the wait between lines, as indicated in the wbl field of the lchcr, it signals the vertical control block and activates the load/hsync signal to indicate the start of the next line. 18.3.4 vertical control the vertical control block counts the lines and signals the horizontal control block. upon completion of the wait between frames, as indicated in the wbf field in the lcvcr, it signals the frame control block and activates the frame/vsync signal to indicate the start of the next frame. 18.3.5 frame control the frame control block initializes all counters, starts the dma, and provides signaling to the vertical control block. the frame control block generates an end of frame signal indicator that can be used to generate an interrupt. the end of frame interrupt can be enabled by setting the ien bit in the lccr. 18.3.6 dma control the dma control block handles all data transfers to and from the fifos and keeps them filled. at the appropriate time, each fifo is filled by the dma control block in 16-byte transfers. your frame buffer address must be 16-byte aligned. when the lcd controller is initiated at reset or after an underrun condition occurs, lcd data transfers to the panel start after five dma read burst accesses to display memory have filled the fifos. see section 16.5.1 sdma bus arbitration and transfers for proper arbitration configuration between the lcd controller dma and the sdma.
lcd controller 18-14 mpc823e reference manual motorola lcd controller 18 18.3.7 timing control the lcd controller is clocked by the lcdclk signal that the system interface unit generates by dividing the system clock. the lcdclk signal is used to convert frame data to pixel format. the division factor depends on the type of display you are using. use the following table to program lcdclk. for information on the system clock and reset control register, refer to section 5 clocks and power control . 18.3.8 contrast and brightness control if you do not use frame rate control to handle contrast and brightness, then you will need external circuitry to give you more control for those panel inputs. refer to your panel specifications to find out what you need for your panel. 18.3.9 the lcd interface the lcd interface provides drivers for the data, clock, and control signals to the lcd display. it consists of 12 data bits (ld[0:8], lcd_a, lcd_b, and lcd_c), a data clock (shift/clk), vertical and horizontal control (frame/vsync and load/hsync), and panel control (lcd_ac/loe). you can program the polarity of each of these signals. the lcd interface can be configured to support a variety of panelssingle-scan, dual-scan, color, monochrome, passive, and active. table 18-1. lcdclk programming bits per pixel/panel type lcd panel type/data width single-scan dual-scan 12-bit 8-bit 4-bit 8-bit 4-bit 1-bit black/white f f f f 2-bit grayscale 2 * f f 2 * f f 4-bit grayscale 2 * f f 2 * f f 4- or 8-bit color passive 3 * f 2 * f 2 * f 4- or 8-bit color active (tft) f note: f denotes the lcd panel clock frequency.
lcd controller motorola mpc823e reference manual 18-15 lcd controller 18 18.3.9.1 single-scan and dual-scan panels. some lcd panels split the display area into two horizontal halves that are scanned at the same time so that two lines are shifted and displayed simultaneously in each half. in this case, half of the data bus is used to drive the upper half of the screen and the other half is used to drive the lower half. figure 18-10 illustrates single-scan and dual-scan lcd panels. 18.3.9.2 passive interface. passive lcd interfaces use the following signals. these signals have a programmable polarity. t cyc is the cycle time of the lcd clock (shift/clk). t delay is a circuit delay. ? shift/clkon the asserted edge of shift, data is latched into the x shift register. ? frame/vsyncthe frame signal initiates the frame by putting the y pointer at the first row. ? load/hsyncthe load signal transfers the contents of the shift register into the drive latches. ? lcd_ac/loethe lcd alternating current signal toggles every few frames to nullify any dc voltage. the toggle rate is programmable. ? ldthe width of this data bus is configured to 4 or 8 bits. a general-purpose i/o can be used to output an integrated signal or pulse-width modulation (pwm) waveform and its duty cycle controls the rms value of the voltage to the panel. the pwm signal is generated by one of the communication processor module timers. refer to section 16.2.6 risc microcontroller commands for more details. figure 18-10. single-scan and dual-scan lcd panels data (4 or 8 bits) shift, load frame, load array x by y pixels x y data (2 or 4 bits) shift, load frame, load 0 y array 0 by y / 2 pixels array x by y / 2 pixels x data (2 / 4 bits) dual-scan display single-scan display
lcd controller 18-16 mpc823e reference manual motorola lcd controller 18 figure 18-11. passive interface timing diagram shift/clk ld shift/clk load/hsync frame/vsync lcd_ac/loe t delay t cyc 4.5 t cyc 4 t cyc 5 t cyc 4 t cyc (min) t cyc (min) frame/vsync load/hsync shift/clk nth line first line second line wbf (lines)
lcd controller motorola mpc823e reference manual 18-17 lcd controller 18 18.3.9.3 active interface. active (tft) interfaces use the following signals. these signals have a programmable polarity. t cyc is the cycle time of the lcd clock (shift/clk). t delay is a circuit delay that is specified in section 22 dc electrical characteristics . in figure 18-12, the reference to 1-16 lines signifies that the time period depends on how the the vpw field in the lcvcr register. the reference to 0-1,023 lines signifies that the time period varies between 0 and 1,023 scan lines (wbf field in the lcvcr). ? shift/clkwhen the lcd output enable signal is valid, data is latched on the asserted edge of clk. ? frame/vsyncthis vertical sync signal initiates a new frame. ? load/hsyncthis horizontal sync signal initiates a new line. ? lcd_ac/loewhen the lcd output enable signal is valid, it enables data to be shifted into the display. when it is disabled, the data is invalid and no data is transferred. ? ldthe lcd data bus represents 4-, 8-, or 12-bit data. for monochrome displays, 4- or 8-bit data is the same as passive interfaces and 12-bit data is used for color displays. use the following formulas to calculate the hsync and vsync cycles using the user-programmable parameters that are located in the lcd control registers. vsync = (hsync l) +wbf hsync = shift/clk (p ? lcdbw +12 + twbl) shift/clk = lcdclk / k lcdclk = vcoout / lcd_div_factor (programmed) where: l = number of lines in panel ( ? 2 for dual-scan displays and +vpw in lcvcr for active). wbf = number of waits between frames. p = number of pixels per line in panel ( 2 for dual-scan displays). lcdbw = lcd bus width (4- or 8-bit for passive displays and 1 for active). twbl = wbl + n = total number of waits between lines, where: n = 7 in configurations in which the panel type is a passive monochrome with a 4-bit data bus configured with two or four bits per pixel. bpix = 01 or 10, clor = 0, tft =0, and lbw = 0, as defined in the lccr. n = 5 for all other configurations vcoout = spll output frequency. lcd_div_factor = lcd_div_factor is programmed in the sccr (dflcd dfalcd). k = inner rate factor that depends on your configuration: 3: for a 4-bit per pixel color passive display with an 8-bit lcd data bus width single-scan. 2: for a 4-bit per pixel color passive display with an 8-bit lcd data bus width dual-scan or with a 4-bit lcd data bus width single-scan. 1: for all other configurations.
lcd controller 18-18 mpc823e reference manual motorola lcd controller 18 figure 18-12. active interface timing diagram shift/clk ld lcd_ac/loe frame/vsync load/hsync lcd_ac/loe 4 t cyc t delay 4 t cyc 4 t cyc 1 C 16 lines (vpw) 5 t cyc 0 C 1,023 lines (wbf) load/hsync first line nth line load/hsync frame/vsync wbf (lines) lcd_ac/loe
lcd controller motorola mpc823e reference manual 18-19 lcd controller 18 18.3.9.4 analog interface. the mpc823e has a digital interface, so you will need a dac to connect the mpc823e to an analog panel. 18.3.10 system considerations when you are designing a system with the lcd controller, you must monitor the bus bandwidth used by the lcd subsystem and the maximum allowable bus latency. the configuration below uses the following parameters: ? gclk2/clkoutsystem clock frequency ? bnumnumber of bursts per frame ? frrframe refresh rate ? bpixnumber of bits per pixel ? colnumber of display columns ? rownumber of display rows ? mbnumber of system clocks per memory burst you must configure the parallel to serial clock ratio between the system clock and the lcd serial data clock. the following example contains typical display characteristics for a full vga panel (640 480) calculation: ? 640 480 = 307,200 pixels per screen ? (307,200 pixels per screen) 4 bits per pixel = 1.228mb per screen = 150kb per screen ? 70hz 150kb = 10.5mb/s ? 70hz is 14.3ms per frame: 14.3ms/307,200 pixels clocked 4 bits at a time = 186ns (approximately 5mhz) serial clock to the lcd drivers the display serial clock is slightly faster than 5mhz because of the panel overhead. in most vga displays, however, an 8-bit lcd serial data (dual-scan passive panel) is used and the display frequency is 3.76mhz. the clkout to lcdclk ratio must be between 4:1 and 5:1 for optimum system operation. 18.3.10.1 bus bandwidth. the bus bandwidth that the lcd controller uses depends on the display parameters (size, refresh rate), the memory system (number of clocks per burst), and the system clock frequency. bnum col row bpix 128 ------------------------------------------------------- = bus band width bnum frr mb sclk ----------------------------------------------------- 100% =
lcd controller 18-20 mpc823e reference manual motorola lcd controller 18 the following example shows a monochrome full vga (640 480) passive display, single-scan, 4-bit panel data bus. the lcd controller will provide 8-bit per pixel coding with a refresh rate of 90hz. in this example, assume a display memory cycle burst timing of (2, 1, 1, 1) for a total of five cycles per burst. it is recommended that the lcd controller use less than 45% of the bus. sclk = 25mhz frr = 90hz mb = 5 bpix = 8 col = 640 row = 480 bnum = (col row bpix) ? 128 bus band width = (bnum frr mb) ? sclk 18.3.10.2 bus latency. the maximum bus latency allowed in the system is given by: typical example using the same data from above: bus band width 9600 90 5 25 6 10 ----------------------------------- 100% 17% == max latency mb sclk bnum frr ------------------------------------- - = max latency 525 6 10 9600 90 ---------------------------- - 145 system clocks ==
lcd controller motorola mpc823e reference manual 18-21 lcd controller 18 18.4 register model 18.4.1 lcd controller configuration register the 32-bit, memory mapped, read/write lcd controller configuration register (lccr) holds the mode and configuration parameters that you can use to operate your lcd panel. bnumnumber of bursts this field contains the number of burst cycles required for one refresh cycle. eienexception interrupt enable 0 = the underrun or bus error interrupt is disabled. 1 = the underrun or bus error interrupt is enabled. ieninterrupt enable 0 = the end-of-frame interrupt is disabled. 1 = the end-of-frame interrupt is enabled. irqlinterrupt request level this field contains the priority request level of the lcd controllers interrupt that is sent to the system interface unit. refer to section 12.3.3 programming the interrupt controller for more information. this will generate an interrupt request level with a vector in the sivec register if enabled with the simask register. both eof and the exception interrupts use the same request level. clkpclock polarity 0 = the shift/clk pin polarity is active high. 1 = the shift/clk pin polarity is active low. lccr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field bnum eien reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x840 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ien irql clkp oep hsp vsp dp bpix lbw splt clor tft pon reset 0 0 00000 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x842
lcd controller 18-22 mpc823e reference manual motorola lcd controller 18 oepoutput enable polarity 0 = the lcd_ac/loe pin polarity is active high. 1 = the lcd_ac/loe pin polarity is active low. hsphorizontal sync polarity 0 = the load/hsync pin polarity is active high. 1 = the load/hsync pin polarity is active low. vspvertical sync polarity 0 = the frame/vsync pin polarity is active high. 1 = the frame/vsync pin polarity is active low. dpdata polarity 0 = the lcd data (ld) pin polarity is active high. 1 = the lcd data (ld) pin polarity is active low. bpixbits per pixel this field indicates the number of bits that represent one pixel in display memory. 00 = one bit per pixel. 01 = two bits per pixel. 10 = four bits per pixel. 11 = eight bits per pixel. lbwlcd bus width this field indicates the number of data bits that are output for every shift/clk. it is only valid for passive displays. for tft displays, see the tft bit below. 0 = four bits per clock. 1 = eight bits per clock. spltsplit display mode 0 = the display is single-scan (one row is displayed at a time). 1 = the display is dual-scan (two rows are displayed at a time). clorcolor display 0 = the lcd panel is a monochrome display. 1 = the lcd panel is a color display. tfttft display when this bit is set, 12 bits of rgb (4 bits per color) data are provided on the ld data bus. 0 = the lcd panel is a passive display. 1 = the lcd panel is an active (tft) display.
lcd controller motorola mpc823e reference manual 18-23 lcd controller 18 ponpanel on 0 = the lcd controller operation is disabled. 1 = the lcd controller operation is enabled. 18.4.2 lcd horizontal control register the 32-bit, memory-mapped, read/write lcd horizontal control register (lchcr) holds the panel horizontal pixel resolution and other configuration parameters. bits 0C6reserved these bits are reserved and must be set to 0. bobyte order 0 = the powerpc little-endian convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed in comparison to the motorola mode. this mode is supported only for 32-bit port size memory. motorola byte ordering (normal operation) is also called big-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. 1 = big/little-endian byte ordering. as data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. ataddress type this field contains values that you want to appear on the at pins when the associated sdma channel accesses memory. at0 is always driven to 1. refer to section 13.4.7.3.4 address space attributes for address type descriptions. lchcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved bo at hpc reset 0000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x 844 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field hpc wbl reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x 846
lcd controller 18-24 mpc823e reference manual motorola lcd controller 18 hpchorizontal pixel count this field specifies the number of pixels per line adjusted by panel type and bits per pixel. use table 18-2 to program the value for this field. wblwait between lines to achieve the best display quality, this field can be used as an adjustable parameter to modify the resultant image. this field represents the wait period between lines, which are measured in shift/clk cycles. the total number of wait cycles between lines (twbl) is equal to wbl+n, where: n = 7 in configurations in which the panel type is a passive monochrome with a 4 bit data bus configured with two or four bits per pixel. bpix = 01 or 10, clor = 0, tft = 0, and lbw = 0 as defined in the lccr. n = 5 for all other configurations. twbl is used to calculate hsync timing in section 18.3.9.3 active interface . table 18-2. horizontal pixel count programming bits per pixel/panel type lcd panel type/data width single-scan dual-scan 12 bit 8-bit 4-bit 8-bit 4-bit 1-bit monochrome, 2-/4-bit grayscale 1/8 * h 1/4 * h 1/4 * h 1/2 * h 4-/8-bit color passive 3/8 * h 3/4 * h 3/4 * h 4-/8-bit color active (tft) h note: h indicates the number of pixels per line.
lcd controller motorola mpc823e reference manual 18-25 lcd controller 18 18.4.3 lcd vertical configuration register the 32-bit, memory-mapped, read/write lcd vertical control register (lcvcr) holds the panel vertical pixel resolution and other configuration parameters. vpwvertical sync pulse width (with active (tft) panels only) this field controls the width of the active frame/vsync signal with its value represented in line units. programming this field to n causes frame/vsync to be active for n lines. this field is only valid for tft displays and must be cleared for all others. bits 4C6 and 21reserved these bits are reserved and must be set to 0. lcd_aclcd ac timing this field specifies the number of frames that are displayed before the lcd_ac/loe pin is toggled. lcvcr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field vpw reserved lcd_ac vpc reset 000 0 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x 848 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field vpc res wbf reset 00 0 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x 84a
lcd controller 18-26 mpc823e reference manual motorola lcd controller 18 vpcvertical pixel count this field specifies the number of lines per frame. use table 18-3 to program the value in this field. wbfwait between frames this field represents the wait period between frames, which is measured in lines. table 18-3. vertical pixel count programming bits per pixel/panel type lcd panel type/data width single-scan dual-scan 12-bit 8-bit 4-bit 8-bit 4-bit 1-bit monochrome, 2-/4-bit grayscale v v v/2 v/2 4-/8-bit color passive v v v/2 4-/8-bit color active (tft) v note: v indicates the total number of lines on the panel.
lcd controller motorola mpc823e reference manual 18-27 lcd controller 18 18.4.4 lcd frame buffer a start address register the 32-bit lcd frame buffer a start address (lcfaa) register contains the start address of the frame buffer data that you want to send to your lcd panel. fifo a is the destination for your frame buffer data. for single-scan panels, fifo a concatenated with fifo b is used to transfer data, so only the lcfaa register needs to be loaded. the dma controller uses the buffer start address to initiate data transfers from display memory, which can be system memory or a dedicated display memory block. because all lcd controller dma bursts must be 16-byte aligned, the four least-significant bits of the address are not used. this register is read by the lcd controller at the start of each frame. therefore, changing this register will not take effect until the wbf bit expires. faafifo a address this field designates the start address in display or system memory where lcd panel data resides. lcfaa bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field faa reset r/w r/w addr immr & 0xffff0000 + 0x850 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field faa x reset r/w r/w r/w addr (immr & 0xffff0000) + 0x852 note: x - dont care and = undefined.
lcd controller 18-28 mpc823e reference manual motorola lcd controller 18 18.4.5 lcd frame buffer b start address register the 32-bit lcd frame buffer b start address (lcfba) register contains the start address of the frame buffer data that you want to send to your lcd dual-scan panel (lower half). fifo b is the destination for your frame buffer data to be passed to the lower half of the panel. notice that for single-scan panels, fifo b is concatenated with fifo a to transfer data, so only the lcfaa register needs to be loaded. however, for dual-scan panels, the lcfba register must be set. for dual-scan panels, the dma controller uses the buffer b start address to initiate data transfers from display memory (system memory or a dedicated display memory block) to fifo b. because all lcd controller dma bursts must be 16-byte aligned, the four least-significant bits of the address are not used. this register is read by the lcd controller at the start of each frame. therefore, changing this register will not take effect until the wbf bit expires. fbafifo b address this field designates the start address in display or system memory where the lcd panel data resides. the data retrieved is for the lower half of a dual-scan panel and passes through fifo b. lcfba bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field fba reset r/w r/w addr (immr & 0xffff0000) + 0x854 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field fba x reset r/w r/w r/w addr immr & 0xffff0000 + 0x856 note: x - dont care and = undefined.
lcd controller motorola mpc823e reference manual 18-29 lcd controller 18 18.4.6 lcd status register the 8-bit memory-mapped lcd status register (lcsr) is used to report certain events to the core. when an event is recognized, the lcd controller sets the corresponding bit in this register, regardless of the corresponding enable bit, which is located in the lccr. a bit is cleared by writing a 1 (writing a 0 has no effect) and more than one bit can be cleared at a time. bits 0C4reserved these bits are reserved and must be set to 0. berrbus error this status bit is set if a display memory read cycle by the lcd controller fifo is abnormally terminated. if the eien bit is set in the lccr, then an interrupt is generated to the system interface unit at the level specified in the irql field of lccr. ununderrun when this bit is set, it indicates that a fifo underrun condition has been detected. an underrun condition occurs when the lcd controller is empty before a frame is completed. if the eien bit is set in the lccr, then an interrupt is generated to the system interface unit at the level specified in the irql field of lccr. eofend of frame this status bit is set when a frame is completed and if the ien bit in the lccr is enabled. then an interrupt is generated to the system interface unit at the level specified in the irql field of lccr. lcsr bit 0 1 2 3 4 5 6 7 field reserved berr un eof reset 0 000 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x 858
lcd controller 18-30 mpc823e reference manual motorola lcd controller 18 18.4.7 color ram operation modes the color ram contains 256 entries that are each 16 bits wide. it is located in the dual-port ram and is not initialized at reset. your lcd panel and its required mode will dictate how the display or system memory and the color ram is configured. 18.4.7.1 one bit per pixel monochrome mode. when you are using this mode (tft=0, bpix=00, and clor=0), configure color ram using the following pattern. you must program the first 16 entries of the color ram to be transparent. bits 0C11reserved these bits are reserved and must be set to 0. note: before programming the color ram, you must program the lccr to the specific data coding, number of bits per pixel, color or monochrome, etc. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glc reset r/w r/w r/w addr (immr & 0xffff0000) + (dpr) 0xe000xe1f note: = undefined.
lcd controller motorola mpc823e reference manual 18-31 lcd controller 18 glcgrayscale level code (monochrome display) this field is a 4-bit code that represents the grayscale level. it must be programmed to the value of the entry number. for entry 0 glc = 0000, for entry 1 glc = 0001, and for entry 2 glc = 0010 as shown below. figure 18-13. color ram transparent translation for one-bit per pixel mode glc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 01 0 0 00 0 0 00 1 0 00 0 0 01 1 0 00 0 0 00 0 1 00 0 0 01 0 1 00 0 0 00 1 1 00 0 0 01 1 1 00 0 0 10 0 0 00 0 0 11 0 0 00 0 0 10 1 0 00 0 0 11 1 0 00 0 0 10 0 1 00 0 0 11 0 1 00 0 0 10 1 1 00 0 0 11 1 1 00 0 0
lcd controller 18-32 mpc823e reference manual motorola lcd controller 18 18.4.7.2 two bits per pixel grayscale mode. in 2-bits per pixel grayscale mode, the lcd controller provides four possible shades to be loaded into each pixel of the lcd panel. the two bits of data are provided by each display memory word that is accessed by the dma controller. this value will then index into the color ram at addresses 1, 3, 5, and 7. you can provide any four of 16 possible shades by loading the color ram addresses shown below. bits 0C7reserved these bits are reserved and must be set to 0. glca/glcbgrayscale level code a and b this field is a 4-bit code that represents the grayscale level for a given pixel code. glca and glcb must be programmed to the same value. the 4-bit code must be programmed in one of the following ways: ? program address 1 of the color ram with the grayscale level code that corresponds to pixel code 00 that was retrieved from display memory. ? program address 3 of the color ram with the grayscale level code that corresponds to pixel code 01 that was retrieved from display memory. ? program address 5 of the color ram with the grayscale level code that corresponds to pixel code 10 that was retrieved from display memory. ? program address 7 of the color ram with the grayscale level code that corresponds to pixel code 11 that was retrieved from display memory. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glcb glca reset r/w r/w r/w r/w addr (immr & 0xffff0000) + (dpr) 0xe000xe07 note: = undefined. figure 18-14. color ram entries for two bits per pixel mode 1 3 5 7 glcb glca 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 6
lcd controller motorola mpc823e reference manual 18-33 lcd controller 18 18.4.7.3 four bits per pixel grayscale mode. in 4-bits per pixel grayscale mode, the lcd controller provides 16 possible shades to be loaded into each pixel of the lcd panel. the four bits of data are provided by each display memory word that is accessed by the dma controller. this value will then index into the first 16 odd addresses of the color ram. you can provide any of the 16 possible shades by loading the color ram addresses shown below. see figure 18-8 for more information. bits 0C7reserved these bits are reserved and must be set to 0. glca/glcbgrayscale level code a and b this field is a 4-bit code that represents any one of 16 possible grayscale levels for a given pixel code. this grayscale level is then used to represent the appropriate shade for a given pixel and is passed to the appropriate panel bit. glca and glcb must be programmed to the same value. the color ram to be programmed is shown below. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved glcb glca reset r/w r/w r/w r/w addr (immr &0xffff0000) + (dpr) 0xe000xfff note: = undefined.
lcd controller 18-34 mpc823e reference manual motorola lcd controller 18 figure 18-15. color ram entries for four bits per pixel (grayscale) 1 3 5 7 9 b 0 f f1 glcb glca 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f3 f5 f7 f9 fb fd ff 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
lcd controller motorola mpc823e reference manual 18-35 lcd controller 18 18.4.7.4 passive four and eight bits per pixel color mode. this mode operates the same way for 4- or 8-bits per pixel and the color ram is loaded similarly. you provide a 4- or 8- bit data word that the dma controller retrieves from display memory and that value is indexed into the color ram as shown below. for 4-bits per pixel mode, you can choose one of 16 colors from the 4,096 possible colors. for 8-bits per pixel mode, you can choose one of 256 colors from the 4,096 possible colors. see figure 18-9 for more information. bits 0C3reserved these bits are reserved and must be set to 0. rred level this field is a 4-bit code that represents the red color level. the frame rate control dictates when this color pixel is on or off. ggreen level this field is a 4-bit code that represents the green color level. the frame rate control dictates when this color pixel is on or off. bblue level this field is a 4-bit code that represents the blue color level. the frame rate control dictates when this color pixel is on or off. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved r g b reset r/w r/w r/w r/w r/w addr (immr & 0x ffff0000) + (dpr) 0xe000xe1f (4-bit) or 0xe000xfff (8-bit) note: = undefined.
lcd controller 18-36 mpc823e reference manual motorola lcd controller 18 18.4.7.5 active four and eight bits per pixel color mode. this mode operates the same way for 4- or 8-bits per pixel and the color ram is loaded similarly. you provide a 4- or 8- bit data word that the dma controller retrieves from display memory and that value is indexed into the color ram as shown below. for 4-bits per pixel mode, you can choose one of 16 out of a total of 4,096 possible colors. for 8-bits per pixel mode, you can choose one of 256 out of the 4,096 possible colors. see figure 18-9 for more information. for active (tft) panels, each bit of data for each red, green, or blue value read from the color ram is passed directly to the lcd data bus. these bits follow a particular sequence ld0 (msb), ld1, ld2, lcd_a, ld3, ld4, ld5, lcd_b, ld6, ld7, ld8, and lcd_c (lsb). bits 0C3, 7, 11, and 15reserved these bits are reserved and must be set to 0. rred level this field is a 4-bit code that represents the red color level and is passed directly to the lcd interface. ggreen level this field is a 4-bit code that represents the green color level and is passed directly to the lcd interface bblue level this field is a 4-bit code that represents the blue color level and is passed directly to the lcd interface bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field reserved r g b reset r/w addr (immr & 0xffff0000) + (dpr) 0x e00 0x e1f (4-bit) or 0x e00 0x fff (8-bit) note: = undefined.
lcd controller motorola mpc823e reference manual 18-37 lcd controller 18 18.4.8 lcd panel connection examples some panels connect differently than the mpc823e. these panels are shown as examples in table 18-4 and they may or may not be currently available. table 18-4. lcd panel connection mpc823e signal (port pin) display types sharp lq9d021 active color generic passive color sharp lm64p839 passive monochrome dual-scan hitachi lmg7211urfr passive monochrome sharp lm32k07 passive monochrome sharp lq10d131 color active shift/clk (pd3) ck-p[10] cp2-p[3] cl2-p[3] cp2-p [10] ck-p[10] load/hsync (pd4) hsync-p[6] cp1-p[2] cl1-p[2] cp1-p [11] hsync-p[6] frame/vsync (pd5) vsync-p[4] s-p[1] frame-p[1] s-p [12] vsync-p[4] lcd_ac/loe (pd6) enab-p [28] enab-p[28] ld0 (pd7) r2-p [7] r3-p[7] ld1 (pd8) r1-p [5] d7 (msb) du3-p [11] r2-p[5] ld2 (pd9) r0-p [3] d6 du2-p [10] r1-p[3] lcd_a (pb31) r0-p[1] ld3 (pd10) g2-p [19] d5 du1-p[9] g3-p[19] ld4 (pd11) g1-p [17] d4 du0-p[8] g2-p[17] ld5 (pd12) g0-p [13] d3 dl3-p [15] d3-p [11] d3-p [3] g1-p[13] lcd_b (pb15) g0-p[p11] ld6 (pd13) b2-p [29] d2 dl2-p [14] d2-p [10] d2-p [4] b3-p[31] ld7 (pd14) b1-p [27] d1 dl1-p [13] d1-p [9] d1-p [5] b2-p[29] ld8 (pd15) b0-p [25] d0 (lsb) dl0-p [15] d0-p [8] d0-p [6] b1-p[25] lcd_c (pb17) b0-p[23]
motorola mpc823e reference manual 19-1 video controller 19 section 19 video controller the mpc823e contains an on-chip video controller that can be used to drive a digital tft lcd panel or an analog ntsc/pal display (which needs an external video encoder). it uses the same i/o pins as the lcd controller, which means you can only be using one or the other at a time. the video controller has features that give you more flexibility when preparing data for a video display. the video controller uses a frame buffer, also called a display buffer, that is stored in system memory. the data in the display buffer represents pixel components (bytes), whether it is rgb or yc r c b . you are responsible for preprocessing data as it is stored in the display buffer. the video controller uses a dedicated dma channel to read the data from the display buffer and drive it to the video interface. it also generates the required timing and control signals (horizontal sync, vertical sync, field, and blanking). a typical mpc823e video system is illustrated in figure 19-1. mpc823e figure 19-1. typical mpc823e video system system ram crt frame buffer panel digital video encoder lcd tft panel video controller dma system system bus core internal bus interface unit irq
video controller 19-2 mpc823e reference manual motorola video controller 19 19.1 features the following list summarizes the features of the video controller: ? supports digital tft lcd panels and analog ntsc/pal displays ? sequential rgb, 4:4:4, and 4:2:2 yc r c b (ccir 601) digital component video formats ? ccir-656 compatible 8-bit interface port ? programmable control for horizontal sync, vertical sync, field, blanking, polarity, and timing generation with half-clock resolution ? supports interlace/noninterlace scanning methods ? programmable display active area ? programmable background color for inactive areas ? smooth switching between two picture formats ? supports hardware pan/scroll options in a zoomed buffer ? glueless interface to most digital video encoders ? burst read dma cycles are used for maximum bus performance ? end-of-frame and bus exception interrupt generation 19.2 operation the video controller consists of a register set, dma controller with fifos, and a video control ram array, as shown in figure 19-2. the video controller ram array provides the proper sequencing and control signal generation needed to synchronize the datastream through the fifos. the video controller, a standalone module, is programmed using a set of configuration registers. once the registers have been configured and the video controller is enabled, the dma controller initiates burst read cycles to display memory.
video controller motorola mpc823e reference manual 19-3 video controller 19 19.2.1 the video controller clock the video controller master clock source can either be the lcdclk, which is generated by the system interface unit, or the external video clock signal (clk). refer to section 5.2.1 system clock and reset control register and section 5.3.4.4 the lcd clocks for more information. lcdclk is derived from the spll. if the external video clock is enabled by setting the csrc bit in the vccr, you must provide an external video clock (clk) at the port d input. figure 19-2. video controller block diagram note: if an external video clock (clk) is used, then the ratio between that external clock and gclk1 must not be greater than 1.25:1. for example, if your system clock is 50mhz, then the clk input cannot exceed 62.5mhz. fifo hsync 8-bit data fifo mux configuration registers vsync field blank active pixels background dma dma interface controller pixels u-bus video control ram
video controller 19-4 mpc823e reference manual motorola video controller 19 19.2.2 fifo and dma control the video controller fifo consists of 24 32-bit entries. the dma control block handles all data transfers to the fifos and keeps them filled. at the appropriate time, each fifo is filled by the dma control block in 16-byte transfers. the frame buffer address must be 16-byte aligned. when the video controller is enabled, video data transfers to the panel start after five dma burst accesses have filled the fifos. see section 16.5.1 sdma bus arbitration and transfers for the proper arbitration configuration between the video controller dma and sdma. the fifo has two sets of control registers (0 and 1) associated with the video ram arrays (ram_0 or ram_1 appropriately). if there are problems with the screen blanking when your caches are on, set the sdcr to 0x40. the dma control supports both interlace and noninterlace (progressive) scanning schemes. in interlace mode, the dma fetches the video components of odd lines from display frame buffer a followed by the even lines from display frame buffer b. in noninterlace mode, the lines are fetched sequentially from buffer a. no matter which mode you use, the video components of a line must be stored in an integer number of bursts. if the fifo underruns during a frame, the video controller forces background video on the screen until synchronization between the fifo and video control ram array is regained. synchronization means the fifo and the video control ram array are ready to display a frame from its beginning. at that point, the video controller starts reprocessing the frame at the beginning of the video control ram array. 19.2.3 image sizes the video controller can be used to display an image that is smaller than the size of the display. the area that is used to display the image is defined as the active display area and its video components are taken from the frame buffer. the inactive area is driven with a single user-programmable default background color. the video controller changes smoothly between two image sizes without disturbing the video timings. a display format is defined by the pattern in the ram array (set ram_0 or ram_1) and the appropriate fifo control register set (set_0 or set_1). the active ram set contains the pattern associated with the currently displayed image and the other ram set contains the pattern associated with the second image. figure 19-3. output timing example video clock hsync vd0-vd7 (yc r c b ) vd0-vd7 (rgb) y c r y y c b c r c b br gb r g b
video controller motorola mpc823e reference manual 19-5 video controller 19 after you program the inactive ram set and corresponding fifo control register set, change the asel bit in the vcmr to the value of the inactive set. the video controller will switch between the currently active set and the inactive set at the boundary of the frame. the cas bit in the vsr reflects the currently active set. you can also force background video frames without disturbing the video timings by setting the bd bit in the vcmr. during this time, the fifo is flushed and allows you to reprogram the current fifo buffer address pointer registers. you can also switch between the currently active and inactive sets during this period. after clearing the bd bit, the video controller will continue operating according to the current ram set and fifo control register set. 19.3 register model 19.3.1 video controller configuration register the 16-bit, memory-mapped, read/write video controller configuration register (vccr) contains the mode and configuration bits for the video controller. ddtdata drive timing this bit determines when the data changes. 0 = the video controller drives new data on the rising edge of the video clock. 1 = the video controller drives new data on the falling edge of the video clock. dpdata polarity 0 = the data polarity is active high. 1 = the data polarity is active low. note: if the images contain less than 24 words of data, the video controller will not have time to change images smoothly. you must use the force background video method described above to ensure correct operation. vccr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ddt dp dpf res ien eien irql bo at res csrc von reset 00000 0000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x800
video controller 19-6 mpc823e reference manual motorola video controller 19 dpfdefault pixels format this bit defines the format of the background video components. 0 = bgnd1, bgnd2, bgnd3 values will be used for the inactive area (bgnd1, bgnd2, bgnd3, bgnd1, bgnd2, bgnd3,....). this setting is used for rgb encoding. 1 = bgnd1, bgnd2, bgnd3, bgnd4 values will be used for the inactive area (bgnd1, bgnd2, bgnd3, bgnd4, bgnd1, bgnd2, bgnd3, bgnd4,...). this setting is used for yc r c b format encoding (y 1 c r y 2 c b ). bits 3 and 13reserved these bits are reserved and must be set to 0. ieninterrupt enable 0 = the end-of-frame (eof) interrupt is disabled. 1 = the end-of-frame (eof) interrupt is enabled. eienexception interrupt enable 0 = the underrun/bus error interrupt is disabled. 1 = the underrun/bus error interrupt is enabled. irqlinterrupt request level this field contains the priority request level of the video controllers interrupt that is sent to the system interface unit. refer to section 12.3.3 programming the interrupt controller for more information. this will generate an interrupt request level with a vector in the sivec register if enabled with the simask register. both eof and the exception interrupts use the same request level. 000 is the highest priority level and 111 is the lowest. bobyte order 0 = powerpc little-endian byte order. 1 = big- or little-endian byte order. ataddress type this field contains the value that you want to appear on the at pins when the associated sdma channel accesses memory. at0 will always be driven to 1. refer to section 13.4.7.3.4 address space attributes for address type descriptions. csrcclock source this bit controls the clock source to the video controller. 0 = the video controller source is lcdclk. 1 = the video controller source is the shift/clk/clk pin (pd3). vonvideo controller on 0 = video controller operation is disabled. 1 = video controller operation is enabled.
video controller motorola mpc823e reference manual 19-7 video controller 19 19.3.2 video status register the 8-bit memory-mapped video status register (vsr) is used to report certain events to the core. when an event is recognized, the video controller sets the corresponding bit in the video status register, regardless of the corresponding mask bit. the video status register can be read at any time. a bit is cleared by writing a one (writing a zero has no effect). more than one bit may be cleared at a time. bits 0 and 2C4reserved these bits are reserved and must be set to 0. cascurrent active set this read-only bit indicates the currently active ram array and fifo control register set. 0 = ram_0 and fifo register set_0 are currently active. 1 = ram_1 and fifo register set_1 are currently active. berrbus error this status bit is set if a read cycle associated with the video controller was terminated by the assertion of a tea signal. a maskable interrupt is generated to the core as long as this bit is set. ununderrun this bit indicates that a fifo underrun condition has been detected. an underrun condition occurs when the video controller fifo is empty before a frame is completed. if the eien bit is set in the vccr, then an interrupt is generated to the system interface unit at the level specified in the irql field of vccr. eofend of frame this status bit is set when a ram line, with the int bit set, is executed. if the ram line is repeated for more than one clock cycle, eof will only be set at the last cycle of execution. this bit is typically used to mark the completion of a frame. if the ien bit in the vccr is enabled, an interrupt is generated to the system interface unit at the level specified in the irql field of vccr. vsr bit 0 1 2 3 4 5 6 7 field reserved cas reserved berr un eof reset 00 0 000 r/w r/w r r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x804
video controller 19-8 mpc823e reference manual motorola video controller 19 19.3.3 video command register the 8-bit video command register (vcmr) is used to control the display format. bits 0C5reserved these bits are reserved and must be set to 0. aselactive set select this bit selects one ram array and fifo control register set to be active for the next frame. the current set selection is reflected in the cas bit of the vsr. 0 = selects ram_0 and fifo register set_0 as the active set. 1 = selects ram_1 and fifo register set_1 as the active set. bdblank display when set, this bit forces the background video to be displayed and flushes the current fifo. 0 = display the image from the frame buffer. 1 = force background video and flush fifo. vcmr bit 0 1 2 3 4 5 6 7 field reserved asel bd reset 000 r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x806 note: once the asel bit is changed, you cannot access video ram until the cas bit in the vsr reflects the change.
video controller motorola mpc823e reference manual 19-9 video controller 19 19.3.4 video background color buffer register the 32-bit, read/write video background color buffer (vbcb) register holds components for the background video. it is used as the source of video data for the inactive area of the display, according to the dpf bit in the vccr. when you are using the adv7176, this register must be programmed as c b yc r y. bgndxbackground color component 1C4 this field represents the color component based on the rgb or yc r c b format. vbcb bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field bgnd1 bgnd2 reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x808 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field bgnd3 bgnd4 reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x80a
video controller 19-10 mpc823e reference manual motorola video controller 19 19.3.5 video frame configuration register (set 0) the 32-bit, memory mapped, read/write video frame configuration register set 0 (vfcr0) holds the display horizontal and vertical size, as well as the gap between two sequential lines. sfb0single frame buffer 0 this bit controls whether the video controller displays an image from a single frame buffer (a) or from both frame buffers (a and b). 0 = frame b is valid. 1 = frame b is not valid. bits 1C2reserved these bits are reserved and must be set to 0. vpc0vertical pixel count 0 this field defines the number of lines for a field. gap0gap 0 this field defines the gap in memory between the end of a line and the beginning of the next line in full burst units. for regular noninterlace mode, this field is set to 0. for regular interlace mode, it is set to the value in the nbpl0 field. for example, hardware pan/scroll options in a zoomed buffer can be implemented by using the gap0 field with an appropriate field buffer start address. for example, with 720 pixels in yc r c b format, gap0 must be 0x5a. vfcr0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field sfb0 reserved vpc0 gap0 reset 00 0 0 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x810 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gap0 nbpl0 reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x812 note: the value of the vpc0 field must be non-zero or an error will occur.
video controller motorola mpc823e reference manual 19-11 video controller 19 nbpl0number of bursts per line 0 this field defines the number of bursts per line. 19.3.6 video frame buffer a start address register (set 0) th 32-bit video frame buffer a start address register set 0 (vfaa0) holds the start address of the set_0 odd field. since all bursts must be 16-byte aligned, this register does not use the four least-significant bits of the address. faa0frame buffer a start address for set 0 this field designates the start address of the frame buffer a set 0 in system memory. note: the value of the nbpl0 field must be non-zero or an error will occur. vfaa0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field faa0 reset r/w r/w addr (immr & 0xffff0000) + 0x814 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field faa0 x reset r/w r/w r/w addr (immr & 0xffff0000) + 0x816 note: x = dont care and = undefined.
video controller 19-12 mpc823e reference manual motorola video controller 19 19.3.7 video frame buffer b start address register (set 0) the 32-bit video frame buffer b start address register set 0 (vfba0) holds the start address of the set_0 even field. since all bursts must be 16-byte aligned, this register does not use the four least-significant bits of the address. fba0frame buffer b start address for set 0 this field designates the start address of the frame buffer b set 0 in system memory. vfba0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field fba0 reset r/w r/w addr (immr & 0xffff0000) + 0x818 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field fba0 x reset r/w r/w r/w addr (immr & 0xffff0000) + 0x81a note: x = dont care and = undefined.
video controller motorola mpc823e reference manual 19-13 video controller 19 19.3.8 video frame configuration register (set 1) the video frame configuration register set 1 (vfcr1) has the same structure as vfcr0, except it belongs to set 1 and vfcr0 belongs to set 0. the value of the vpc1 and nbpl1 fields must be non-zero or an error will occur. sfb1single frame buffer 1 this bit controls whether the video controller displays an image from a single frame buffer (a) or from both frame buffers (a and b). 0 = frame b is valid. 1 = frame b is not valid. bits 1C2reserved these bits are reserved and must be set to 0. vpc1vertical pixel count 1 this field defines the number of lines for a field. gap1gap 1 this field defines the gap in the memory between the end of a line and the beginning of the next line in full burst units. for regular noninterlace mode, this field is set to 0. for regular interlace mode, it is set to the value in the nbpl1 field. for example, hardware pan/scroll options in a zoomed buffer can be implemented by using the gap1 field with an appropriate field buffer start address. nbpl1number of bursts per line 1 this field defines the number of bursts per line. vfcr1 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field sfb1 reserved vpc1 gap1 reset 00 0 0 r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0x81c bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gap1 nbpl1 reset 00 r/w r/w r/w addr (immr & 0xffff0000) + 0x81e
video controller 19-14 mpc823e reference manual motorola video controller 19 19.3.9 video frame buffer a start address register (set 1) the 32-bit video frame buffer a start address register set 1 (vfaa1) holds the start address of the set_1 odd field. since all bursts are required to be 16-byte aligned, this register does not use the four least-significant bits of the address. faa1frame buffer a start address for set 1 this field designates the start address of the frame buffer a set 0 in system memory. vfaa1 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field faa1 reset r/w r/w addr (immr & 0xffff0000) + 0x820 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field faa1 x reset r/w r/w r/w addr (immr & 0xffff0000) + 0x822 note: x = - dont care and = undefined.
video controller motorola mpc823e reference manual 19-15 video controller 19 19.3.10 video frame buffer b start address register (set 1) the 32-bit video frame buffer b start address register set 1 (vfba1) holds the start address of the set_1 even field. since all bursts are required to be 16-byte aligned, this register does not use the four least-significant bits of the address. fba1frame buffer b start address for set 1 this field designates the start address of the frame buffer b set 0 in system memory. vfba1 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field fba1 reset r/w r/w addr (immr & 0xffff0000) + 0x824 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field fba1 x reset r/w r/w r/w addr (immr & 0xffff0000) + 0x826 note: x = dont care and = undefined.
video controller 19-16 mpc823e reference manual motorola video controller 19 19.4 video controller ram array the video controller state machine controls data that is shifted out to the video port as well as the timing patterns of the hsync , vsync , field, and blank signals. the video ram consists of two ram arraysram_0 and ram_1that contain 64 32-bit entries. at any given time, one ram array actively drives the panel and controls video controller operation, while the other is inactive but modifiable. you can switch between the two rams at any time, but your change will not take effect until the end of the frame. the cas bit in the vsr reflects the ram that is active. an entry in the active ram is read each video clock and specifies the state of the video port signals for the next cnt video clocks. cnt is specified by a special field within the entry. the next entry is read and used after the cnt clock periods of the previous entry. a few entries can be repeated in a loop to generate a repetitive pattern. read/write operations are always directed to the inactive ram array and can be performed anytime the active ram controls the video controller and display operation. since you can only access one ram array (the inactive one) at a time, both rams are mapped to the same address space. the ram arrays are not initialized after power-on and any access to the ram array is discouraged while the video controller clock inputs are not operating. the video ram array block diagram is illustrated in figure 19-4. figure 19-4. video ram array block diagram 32 bits wide timing generator video vsync hsync field blank address generator ram array 0 clock current entry pointer entry duration counter loop counter loop start pointer 64 entries deep
video controller motorola mpc823e reference manual 19-17 video controller 19 19.4.1 video ram word format the video ram word specifies the timing of all external signals controlled by the video controller. hrhorizontal sync on rising edge of the clock 0 = the value of the hsync signal will be 0 after the rising edge of the clock. 1 = the value of the hsync signal will be 1 after the rising edge of the clock. hfhorizontal sync on falling edge of the clock 0 = the value of the hsync signal will be 0 after the falling edge of the clock. 1 = the value of the hsync signal will be 1 after the falling edge of the clock. vrvertical sync on rising edge of the clock 0 = the value of the vsync signal will be 0 after the rising edge of the clock. 1 = the value of the vsync signal will be 1 after the rising edge of the clock. vfvertical sync on falling edge of the clock 0 = the value of the vsync signal will be 0 after the falling edge of the clock. 1 = the value of the vsync signal will be 1 after the falling edge of the clock. frfield on rising edge of the clock 0 = the value of the field signal will be 0 after the rising edge of the clock. 1 = the value of the field signal will be 1 after the rising edge of the clock. fffield on falling edge of the clock 0 = the value of the field signal will be 0 after the falling edge of the clock. 1 = the value of the field signal will be 1 after the falling edge of the clock. video ram word bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field hr hf vr vf fr ff br bf reserved vds reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xb00C0xbfe bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field int reserved lcyc/cnt lp lst reset r/w r/w r/w r/w r/w r/w addr (immr & 0xffff0000) + 0xb00C0xbff note: = undefined.
video controller 19-18 mpc823e reference manual motorola video controller 19 brblanking on rising edge of the clock 0 = the value of the blank signal will be 0 after the rising edge of the clock. 1 = the value of the blank signal will be 1 after the rising edge of the clock. bfblanking on falling edge of the clock 0 = the value of the blank signal will be 0 after the falling edge of the clock. 1 = the value of the blank signal will be 1 after the falling edge of the clock. bits 8C13 and 17C18reserved these bits are reserved and must be set to 0. vdsvideo data select this field selects the source of the video data or holds the last value of the data for the next cnt cycle. 00 = select active video from display frame buffer (fifo output). 01 = select inactive (background) video from the background color buffer. 10 = hold last value of data. 11 = reserved. intinterrupt 0 = do not generate a interrupt to the core. 1 = generate a maskable interrupt (end of frame) after this entry completes and before the next one begins. note: all pins are general-purpose and can be programmed according to your requirements. the signal pin value only changes at the first cycle in which the line is valid. if a line is valid for more than one clock (cnt > 1), the signal holds its last assigned value.
video controller motorola mpc823e reference manual 19-19 video controller 19 lcyc/cntloop cycles/clock count this field is a special field that is used for two purposes. it is used as the lcyc field if the lp bit is set to mark the beginning of a loop and it is used as a cnt field to count the number of clocks to hold a line. cnt is assumed as 1 if the lcyc field is valid (lp = 1 and at beginning of loop). if lp = 0, then cnt = the number of video clocks for this entry. if lp = 1 and this is the beginning of the loop, then lcyc = the number of loop cycles and cnt is already defined equal to 1. if lp = 1 and this is the end of the loop, then cnt = the number of video clocks for this entry. lploop this bit marks the beginning and end of a loop. the entry that marks the start of a loop must have the lp bit and the lcyc field set to the number of desired iterations. the entry that marks the end of a loop must have the lp bit set as well. since only one bit marks the beginning and end of a loop, nested loops are not possible. lstlast 0 = this is not the last valid entry. 1 = this is the last valid entry. 19.5 programming examples the following examples demonstrate how to program the video controller to support an ntsc or pal interlaced display using analog devices adv7176 video encoder with a few assumptions. ? the ccir 601 4:2:2 video data format is used. ? the adv7176 is controlled by the hsync , blank , and field signals (mode1:slave option) and has already been configured using i 2 c. ? the image data resides in consecutive addresses of the memory. note: the value of the lcyc/cnt field must be 3 1 or erroneous operation will occur.
video controller 19-20 mpc823e reference manual motorola video controller 19 19.5.1 ntsc example the ntsc (national television standards committee) broadcast method defines a virtual screen of 525 lines, in which each line is 858 pixels long, but you can only see 485 of them. each horizontal line contains 720 pixels during the active line period and the rest of the lines pixels are presented during the digital blanking. figure 19-5 illustrates how the frame is divided into the following seven sections that correlate with the behavior of the field and blank signals: ? lines 1-3: frame 1 retrace blanking ? lines 4-21: frame 0 blanking ? lines 22-261: frame 0 active video for odd lines ? lines 262-265: frame 0 retrace blanking ? lines 266-284: frame 1 blanking ? lines 285-524: frame 1 active video for even lines ? line 525: frame 1 retrace blanking figure 19-5. interlaced ntsc format blanking line blank field 101 301 4 0 0 21 0 0 22 0/1 0 261 0/1 0 262 0 0 265 0 0 266 0 1 284 0 1 285 0/1 1 524 0/1 1 525 0 1 blanking odd field even field active video active video field 1 field 0 field 1 cd e ab cd e ab retrace blanking retrace blanking retrace blanking fram buffer a frame buffer b
video controller motorola mpc823e reference manual 19-21 video controller 19 figure 19-6 illustrates the horizontal timing of a single horizontal line, which is represented by five ram entries: ? athe section of the line where both blanking and hsync are asserted. ? bthe section of the line where hsync is negated and blanking is asserted. ? cthe section of the line where both signals are negated while the driven data is background ? dthe section of the line where both signals are negated while the driven data is the image data. ? ethe section of the line where blanking is asserted and hsync is negated. figure 19-6. ntsc horizontal timing 118 pixels (236 clocks) 720 pixels (1440 clocks) 858 pixels (1716 clocks) line 3 line 4 hsync field blank 4 pixels (8 clocks) 16 pixels (32 clocks) ab d e c
video controller 19-22 mpc823e reference manual motorola video controller 19 19.5.1.1 ntsc programming procedure example. use the following procedure to program your video controller using an adv7176 video encoder in slave mode with video data in ccir 4:2:2 format. a clock crystal provides 27mhz to clk. our website ( www.motorola.com ) has a comprehensive example that includes using i 2 c to program the adv7176. ? program the vbcb register with the components of the background video. for a black background, write 0x80108010 to the vbcb register. ? program 0x07805a5a to the vfcr1. it defines a field of 240 lines and each line consists of 90 bursts of data. there is a gap1 of one line (90 bursts) long between two consecutive lines due to interlace mode. ? program the start address of the odd field to vfaa1 register. ? program the start address of the even field to vfba1 register. this address must be equal to vfaa1 address+0x5a0. ? use table 19-1 to configure the video controller ram array. ? write 0x02 to the vcmr to select ram_1 and fifo register set 1 as the active set. ? reset the adv7176 and program the default ntsc settings, except for mode register 1 (0x02), timing register 0 (0x02), and mode register 2 (0x08). ? convert your data to cbycry format for the adv7176. assuming each color ranges between 0 and 100, use the following equations to convert from rgb to yc r c b for the adv7176: void setpixelrgb (int col, int row, pallete color) { int location; vyuy *address; location = screen.burstlength * (row+25) + ((col+55) / 2*4); address = (vyuy *) (location + (int) screen.base); if (col % 2) { address -> y1 = 209 * (color.red + color.green + color.blue) / 300 +16 address -> v = color.blue - color.red/4 - color.green*3/4 = 128; } else { address -> y2 = 209 * (color.red + color.green + color.blue) / 300 + 16 address -> u = color.red - color.green*3/4 - color.blue/4 + 128; } } ? program 0x2043 to the vccr to operate the video controller.
video controller motorola mpc823e reference manual 19-23 video controller 19 table 19-1. video ram array loaded with ntsc example ram entry ram word field line description hx vx fx bx vds int lcyc lp lst 0 00 00 11 00 01 0 3 1 0 entry 0: lp=1beginning of loop. lcyc=3loop entries 0-3 three times. cnt=1hold this entry for one video clock. 1 11 00 11 00 01 0 243 0 0 entry 1: cnt=243hold this entry for 243 video clocks. 2 11 00 11 00 01 0 1440 0 0 entry 2: cnt=1440hold this entry for 1440 video clocks. 3 11 00 11 00 01 0 32 1 0 entry 3: lp=1end of loop. cnt=32hold this entry for 32 video clocks. 4 0000000001 0 18 1 0 lines 4-21, field = 0, blank is asserted (vertical blanking) 5 1100000001 02430 0 6 11 00 00 00 01 0 1440 0 0 7 1100000001 0 32 1 0 8 0000000001 02401 0 lines 22-261. odd field active area, the horizontal line is repeated 240 times 9 1100000001 02350 0 10 11 00 00 11 01 0 8 0 0 11 11 00 00 11 00 0 1440 0 0 12 11 00 00 00 01 0 32 1 0 13 00 00 00 00 01 0 4 1 0 lines 262-265, field = 0, blank asserted (vertical; blanking) 14 11 00 00 00 01 0 243 0 0 15 11 00 00 00 01 0 1440 0 0 16 11 00 00 00 01 0 32 1 0 17 00 00 11 00 01 0 19 1 0 lines 266-284, field = 1, blank asserted (vertical; blanking) 18 11 00 11 00 01 0 243 0 0 19 11 00 11 00 01 0 1440 0 0 20 11 00 11 00 01 0 32 1 0 21 00 00 11 00 01 0 240 1 0 lines 285-524. even field active area 22 11 00 11 00 01 0 235 0 0 23 11 00 11 11 01 0 8 0 0 24 11 00 11 11 00 0 1440 0 0 25 11 00 11 00 01 0 32 1 0 26 00 00 11 00 01 0 1 1 0 line 525, field = 1, blank is asserted (vertical blanking) 27 11 00 11 00 01 0 243 0 0 28 11 00 11 00 01 0 1440 0 0 29 11 00 11 00 01 1 32 1 1 note: hx = hr:hf and vx = vr:vf.
video controller 19-24 mpc823e reference manual motorola video controller 19 19.5.2 pal example the pal (phase alternation line) broadcast method defines a virtual screen of 625 lines, which are 864 pixels long. however, you can only see 576 of these lines. each horizontal line contains 720 pixels during the active line period (which is visible to you) with the rest of the lines pixels presented during digital blanking. figure 19-7 illustrates how the frame is divided into six sections that correlate with the behavior of the field and blank signals: ? lines 1-22: frame 0 blanking ? lines 23-310: frame 0 active video for odd lines ? lines 311-312: frame 0 for retrace blanking ? lines 313-335: frame 1 blanking ? lines 336-623: frame 1 active video for even lines ? lines 624-625: frame 1 retrace blanking figure 19-7. interlaced pal format line blank field 1 0 0 22 0 0 23 0/1 0 310 0/1 0 311 0 0 312 0 0 313 0 1 335 0 1 336 0/1 1 623 0/1 1 624 0 1 625 0 1 blanking blanking odd field even field active video active video field 0 field 1 c de ab cd e ab retrace blanking retrace blanking frame buffer a frame buffer b
video controller motorola mpc823e reference manual 19-25 video controller 19 figure 19-8 illustrates the horizontal timing of a single horizontal line that is represented by five ram entries: ? a defines the section of the line where the both the blank and hsync signals are asserted. ? b defines the section of the line where the hsync signal is negated and blank is asserted. ? c defines the section of the line where the hsync and blank signals are negated while the driven data is background. ? d defines the section of the line where the hsync and blank signals are negated while the driven data is the image data. ? e defines the section of the line where the blank signal is asserted and hsync is negated. figure 19-8. pal horizontal timing 128 pixels (256 clocks) 720 pixels (1440 clocks) 864 pixels (1728 clocks) line 3 line 4 hsync field blank ab d e c 4 pixels (8 clocks) 12 pixels (24 clocks)
video controller 19-26 mpc823e reference manual motorola video controller 19 19.5.2.1 pal programming procedure example. use the following procedure to program your video controller using an adv7176 video encoder in slave mode with video data in ccir 4:2:2 format. ? program the vbcb register with the components of the background video. for a black background, write 0x80108010 to the vbcb register. ? program 0x09005a5a to the vfcr1. it defines a field of 288 lines, in which each line consists of 90 burst of data. there is a gap1 of one line (90 bursts) long between two consecutive lines due to interlace mode. ? program the start address of the odd field to vfaa1 register. ? program the start address of the even field to the vfba1 register. this address must be equal to the vfaa1 address+0x5a0. ? use table 19-2 to configure the video controller ram array. ? write 0x02 to the vcmr to select ram_1 and fifo register set 1 as the active set. ? program 0x2041 to the vccr to operate the video controller.
video controller motorola mpc823e reference manual 19-27 video controller 19 table 19-2. video ram word loaded with pal example ram entry ram word field line description hx vx fx bx vds int lcyc lp lst 0 00 00 00 00 01 0 22 1 0 lines 1-22, field = 0, blank is asserted (vertical blanking) 1 11 00 00 00 01 0 263 0 0 2 11 00 00 00 01 0 1440 0 0 3 1100000001 0 24 1 0 4 00 00 00 00 01 0 288 1 0 entry 4: beginning of loop(loop entries 4-8 288 times). assert hsync and blank for 1 video clock. 5 11 00 00 00 01 0 255 0 0 entry 5: assert blank and negate hsync for 255 video clocks. 6 11 00 00 11 01 0 8 0 0 entry 6: negate blank for 8 video clocks. display video data from the vbcb. 7 11 00 00 11 00 0 1440 0 0 entry 7: display active video data from frame buffer for 1440 video clocks (720 pixels). 8 11 00 00 00 01 0 24 1 0 entry 8: assert blank for 24 video clocks. 9 0000000001 0 2 1 0 lines 311-312, field = 0, blank asserted (vertical; blanking) 10 11 00 00 00 01 0 263 0 0 11 11 00 00 00 01 0 1440 0 0 12 11 00 00 00 01 0 24 1 0 13 00 00 11 00 01 0 23 1 0 lines 313-335, field = 1, blank asserted (vertical; blanking) 14 11 00 11 00 01 0 263 0 0 15 11 00 11 00 01 0 1440 0 0 16 11 00 11 00 01 0 24 1 0 17 00 00 11 00 01 0 288 1 0 lines 336-623. even field active area 18 11 00 11 00 01 0 255 0 0 19 11 00 11 11 01 0 8 0 0 20 11 00 11 11 00 0 1440 0 0 21 11 00 11 00 01 0 24 1 0 22 00 00 11 00 01 0 2 1 0 lines 624-625, field = 1, blank is asserted (vertical blanking) 23 11 00 11 00 01 0 263 0 0 24 11 00 11 00 01 0 1440 0 0 25 11 00 11 00 01 1 24 1 1 note: hx = hr:hf and vx = vr:vf.
motorola mpc823e reference manual 20-1 development 20 capabilities & interface section 20 development capabilities and interface this section discusses the on-chip features that are used during the development phase. background debug monitors and emulators are used to interface with this mpc823e capability. emulators require a level of control and observation that are in sharp contrast to the trend of modern microcomputers and microprocessors in which many bus cycles are directed to internal resources and are not externally visible. the same is true for bus analyzers. to enhance support for development tools, some of the development support functions are implemented in the silicon. program flow tracking, watchpoint and breakpoint generation, and emulation systems that control core activity are just some of the features that allow you to efficiently debug systems based on the mpc823e. 20.1 features the following list summarizes the development features of the mpc823e: ? program flow tracking o instruction show cycles o data show cycles o branching o exception trap ? watchpoint and breakpoint generation o four hardware breakpoints o five watchpoint sources ? simple hardware interface o high-speed data interface o internal status pins o freeze indication ? rich control register set
development capabilities and interface 20-2 mpc823e reference manual motorola development 20 capabilities & interface 20.2 program flow tracking the mpc823e provides many options for tracking program flows that impact performance in varying degrees. the information provided while tracking code flow can be compressed and captured externally and then parsed by a post-processing program using the microarchitecture defined here. the program instruction flow is visible on the external bus when the mpc823e is programmed to operate in serialized mode and show all fetch cycles on the external bus. when working in this mode, although tracking of the program instruction flow is simpler, the performance of the mpc823e is much lower than when working in regular mode. see section 20.6.2.5 instruction support control register for more details about programming the core to operate in this mode. the mpc823e implements a prefetch queue combined with parallel, out-of-order, and pipelined execution. these features, plus the fact that most fetch cycles are performed internally from the instruction cache, increases the performance but makes it very difficult to provide you with the real program trace. instructions progress inside the core from fetch to retirement. an instruction retires from the machine only after it and all preceding instructions finish execution with no exception. therefore, only retired instructions can be considered a rchitecturally executed. reporting program trace during retirement significantly complicates visibility and increases the die size for the two reasonsmore than one instruction can retire in a clock cycle and it is harder to report on indirect branches during retirement. because of this, program trace is reported during fetch and helps to reconstruct the instructions that actually retire after fetch canceled instructions are reported. instructions are fetched sequentially until branches (direct or indirect), exceptions, or interrupts appear in the program flow or until a stall in execution forces the machine to avoid fetching the next address. these instructions can be architecturally executed or they can be canceled in any stage of the machine pipeline. to reconstruct a program trace, you need the program code in addition to the following mpc823e information: ? a description of the last fetched instruction (stall, sequential, branch not taken, branch direct taken, branch indirect taken, interrupt/exception taken). ? the addresses of all indirect flow changes targets. indirect flow changes include all branches using the link and count registers as the target address, all interrupts/ exceptions, as well as rfi and mtmsr because it may cause a context switch. ? the number of instructions canceled on each clock.
development capabilities and interface motorola mpc823e reference manual 20-3 development 20 capabilities & interface 20.2.1 basic operation 20.2.1.1 the internal hardware. to make the events that occur in the machine visible, a few dedicated pins are used. also, a special bus cycle attribute called program trace cycle is defined. the program trace cycle attribute is attached to all fetch cycles that result from indirect flow changes. when program trace recording is required, you must program the appropriate registers to ensure that these cycles are visible on the external bus. the internal visible sync (vsync) signal, when asserted, forces all fetch cycles marked with the program trace cycle attribute to be visible on the external bus, even if their data is found in one of the internal devices. to enable the external hardware to properly synchronize with the internal activity of the core, vsync assertion and negation forces the machine to synchronize and marks the first fetch after the synchronization as a program trace cycle that can be seen on the external bus. for more information about the activity of the external hardware during program trace, refer to section 20.2.1.2 the external hardware when the vsync signal is asserted, all fetch cycles marked with the program trace cycle attribute become visible on the external bus. these cycles generate regular bus cycles when the instructions reside in one of the external devices or address-only cycles when the instructions are in an internal device. when the vsync signal is asserted, some performance degradation occurs because of the additional external bus cycles. since this performance degradation is usually very small, you can program the machine to show all indirect flow changes, perform these additional external bus cycles, and maintain the same behavior when the vsync signal is asserted and negated. for more information, see section 20.6.2.5 instruction support control register . note: to keep the pin count of the chip as low as possible, the vsync signal is not implemented as one of the chips external pins. instead, it is asserted and negated using the serial interface implemented in the development port. for more information on this interface, refer to section 20.4.3 the development interface port . forcing the core to show all fetch cycles marked with the program trace cycle attribute can be accomplished by either asserting the vsync signal or by programming the isct_ser field in the instruction support control (ictrl) register. for more information, see section 20.2.2 controlling instruction fetch show cycles .
development capabilities and interface 20-4 mpc823e reference manual motorola development 20 capabilities & interface the status pins are divided into two groupsthe instruction queue status and the history buffer flush status. ? vf[0:2]visible instruction queue flushes status instruction queue status denotes the type of the last fetched instruction or the number of instructions that were flushed from the instruction queue. these status pins are used for both functions because queue flushes only happen in clocks with no fetch type information to be reported, as shown in table 20-1. 000 = none. 001 = 1 instruction was flushed from the instruction queue. 010 = 2 instructions were flushed from the instruction queue. 011 = 3 instructions were flushed from the instruction queue. 100 = 4 instructions were flushed from the instruction queue. 101 = 5 instructions were flushed from the instruction queue. 110 = reserved. 111 = special case. see section 20.2.1.1 the internal hardware . ? vfls[0:1]visible history buffer flushes status history buffer flushes status indicates the number of instructions that are flushed from the history buffer on this clock. 00 = none. 01 = one instruction was flushed from the history buffer. 10 = two instructions were flushed from the history buffer. 11 = used for debug mode indication and must be ignored by the program trace external hardware. for details, refer to section 20.4.2 debug mode . table 20-1. vf instruction type encoding vf instruction type vf next clock will hold 000 none more instruction type information 001 sequential 010 branch (direct or indirect) not taken 011 vsync was asserted/negated and therefore the next instruction will be marked with the program trace cycle attribute 100 interrupt/exception taken, the target will be marked with the program trace cycle attribute queue flush information 2 101 branch indirect taken, rfi , mtmsr , isync and in some cases mtspr , the target will be marked with the program trace cycle attribute 1 110 branch direct taken 111 branch (direct or indirect) not taken note: unless the next clock has the vf pin set to 111, refer to section 20.2.1.1 the internal hardware .
development capabilities and interface motorola mpc823e reference manual 20-5 development 20 capabilities & interface 20.2.1.1.1 special case queue flush information. there is one special case in which the queue flush information is expected on the vf pins. this is easily monitored since this can only happen when vf equals 111 and the maximum number of possible queue flushes is five. 20.2.1.1.2 program trace in debug mode. when entering debug mode, an interrupt/exception is reported on the vf pins (vf=100) and a cycle marked with the program trace cycle is externally visible. when the cpu is in debug mode, the vf pins equal 000 and the vfls pins equal 11. for more information on the mpc823e debug mode, refer to section 20.4 hardware development system interface . if the vsync signal is asserted/negated while the core is in debug mode, this information is announced when the first vf pins report as the core returns to regular mode. if vsync was not changed while in debug mode, the first vf pins report will be encoded as vf equals 101 (indirect branch) due to the rfi instruction being issued. in both cases, the first instruction fetch after debug mode is marked with the program trace cycle attribute and is externally visible. when the mpc823e external bus is configured to operate at half the speed of the internal system (ebdf=1), the vf and vfls pins will not report fetch and flush information for the program trace capability. however, the internal freeze state of the processor will be reported on the vfls pins. 20.2.1.1.3 sequential instructions marked as indirect branch. there are instances where nonbranch or sequential instructions affect the machine similar to the way that indirect branch instructions affect it. these sequential instructions include rfi , mtmsr , isync , and mtspr to the bar, cmpa-cmph, counta, countb, ictrl, icr, lctrl1, lctrl2, and der registers. the core marks these instructions as indirect branch instructions (vf = 101) and the following instruction address is marked with the program trace cycle attribute as if it was an indirect branch target. therefore, when one of these special instructions is detected in the core, the address of the following instruction is externally visible. the reconstructing software is now able to correctly evaluate the effect of these instructions. 20.2.1.2 the external hardware. when a program trace is needed, the external hardware must sample the status pinsvf and vflsof every clock and mark the address of all cycles with the program trace cycle attribute. program trace is used in various ways, but back trace and window trace are the most common methods.
development capabilities and interface 20-6 mpc823e reference manual motorola development 20 capabilities & interface 20.2.1.2.1 back trace. back trace is useful when a record of the program trace is needed before an event, such as system failure, occurs. if back trace is needed, the external hardware must start sampling the vf and vfls pins and the addresses of all cycles marked with the program trace cycle attribute immediately after reset is negated. since the instruction show cycles programming defaults to show all out of reset, all cycles marked with the program trace cycle attribute are visible on the external bus. vsync must be asserted sometime after reset and negated when the actual event occurs. if show all is not the preferred mode for the instruction show cycles before the event actually occurs, vsync must be asserted before exiting show all mode. if the timing of the event in question is unknown, it is possible to use cyclic buffers. after the vsync signal is negated, the trace buffer contains the program flow trace of the program executed before the event in question occurred. 20.2.1.2.2 window trace. this is useful when a record of the program trace between two events is required. the vsync pin must be asserted between these two events. after vsync is negated, the trace buffer will contain information describing the program trace of the program executed between the two events. 20.2.1.2.3 synchronizing the trace window to the internal core events. the vsync signal is asserted or negated using the serial interface implemented in the development port. to synchronize the assertion or negation to an internal core event, the internal breakpoint hardware must be used with debug mode. this method is available only when debug mode is enabled. for more information on debug mode, refer to section 20.4 hardware development system interface . to synchronize the trace window to the internal core events, follow these steps: 1. enter debug mode either straight from reset or when using a debug mode request. 2. program the hardware to break on the event that marks the start of the trace window using the control registers defined in section 20.3 generating watchpoints and breakpoints . 3. enable debug mode entry for the programmed breakpoint in the debug enable register. see section 20.6.3.2 debug enable register for details. 4. return to the regular code run. the hardware generates a breakpoint when the event in question is detected and the machine enters debug mode. 5. program the hardware to break on the event that marks the end of the trace window. 6. assert the vsync signal. 7. return to the regular code run. the first report on the vf pins is vsync, where vf equals 011. the external hardware starts sampling the program trace information after the vf pins indicate vsync. the hardware generates a breakpoint when the event in question is detected and the machine enters debug mode. 8. negate the vsync signal. 9. return to the regular code run and issue an rfi instruction. the first encoding on the vf pins is vsync, where vf equals 011. the external hardware stops sampling the program trace information after recognizing vsync on the vf pins.
development capabilities and interface motorola mpc823e reference manual 20-7 development 20 capabilities & interface 20.2.1.2.4 detecting the trace window start address. when using back trace, latching vf, vfls, and the address of the program trace cycles must start immediately after reset is negated. the start address is the first address in the program trace cycle buffer. when using window trace, latching of vf, vfls, and the address of the program trace cycles must start immediately after the first vsync is recognized on the vf pins. the start address of the trace window must be calculated according to the first two vf pin reports. assume vf1 and vf2 are the first two vf pin reports and t1 and t2 are the two addresses of the first two cycles marked with the program trace cycle attribute that were latched in the trace buffer. use the following table to calculate the trace window start address. 20.2.1.2.5 detecting vsync assertion/negation. because the vf pins are used to report both instruction type and queue flush information, the external hardware must be cautious when trying to detect the assertion/negation of vsync. when vf equals 011, it is a vsync assertion/negation report only if the prior value of vf was 000, 001, or 010. 20.2.1.2.6 detecting the trace window end address. the information on the status pins that describes the last fetched instruction and last queue/history buffer flush changes every clock. program trace cycles are only generated on the external bus when the system interface unit arbitrates over the external bus. therefore, there is a delay between the report that a program trace cycle is performed and the actual time that this cycle can be detected on the external bus. when you negate vsync using the serial interface of the development port, the core delays reporting that vsync occurred on the vf pins until all addresses marked with the program trace cycle attribute are externally visible. therefore, the external hardware must stop sampling vf, vfls, and the address of the program trace cycles immediately after vf equals vsync. the last two instructions reported on the vf pins are not always valid. therefore, at the last stage of the reconstruction software, ignore the last two instructions. table 20-2. detecting the trace buffer starting point vf1 vf2 starting point description 011 vsync 001 sequential t1 vsync is asserted and followed by a sequential instruction. the start address is t1. 011 vsync 110 branch direct taken t1 - 4 + offset(t1 - 4) vsync is asserted and followed by a taken direct branch. the start address is the target of the direct branch. 011 vsync 101 branch indirect taken t2 vsync is asserted and followed by a taken indirect branch. the start address is the target of the indirect branch.
development capabilities and interface 20-8 mpc823e reference manual motorola development 20 capabilities & interface 20.2.1.3 compression of cancelled instructions. to store all the information generated on the pins during program trace (5 bits per clock + 30 bits per show cycle), a large memory buffer is required. however, since this information includes events that were canceled, compression is possible and can be very beneficial in this situation. external hardware can be added to eliminate all canceled instructions and reports only on taken or not taken branches, indirect flow change, and the number of sequential instructions after the last ?ow change. 20.2.2 controlling instruction fetch show cycles instruction fetch show cycles are controlled by the bits in the ictrl register and the state of the vsync signal. the following table defines the level of fetch show cycles generated by the core and the types of fetch show cycles determined by the isct_ser field. a cycle marked with the program trace cycle attribute is generated for any change in the state of vsync. 20.3 generating watchpoints and breakpoints when detected, watchpoints are reported to the external world on dedicated pins, but do not change the timing and flow of the machine. when breakpoints are detected, they force the machine to branch to the appropriate exception handler. the core supports watchpoints that are generated inside the core as well as breakpoints that are generated inside and outside the core. in the core, as in other risc processors, saving and restoring the machine state on the stack during exception handling is accomplished in the software. when the software is in the middle of saving and restoring, the msr ri bit is cleared. exceptions are handled by the core when the msr ri bit is clear and they result in a nonrestartable machine state. for more information refer to section 6.3.4.1 restartability after an interrupt . table 20-3. fetch show cycle types vsync isct_ser instruction fetch show cycle control field show cycles generated x 000 all fetch cycles x x01 all change of flow (direct and indirect) x x10 all indirect change of flow 0 x11 no show cycles are performed 1 x11 all indirect change of flow note: only cycles that access storage assert the ts signal. all cycles that involve show cycles are marked by asserting the sts signal. when you need to sample the show cycle address and attributes, the sts signal must be enabled by programming the dbgc ?eld of the siumcr. see section 12.12.1.1 siu module configuration register for details.
development capabilities and interface motorola mpc823e reference manual 20-9 development 20 capabilities & interface in general, breakpoints are recognized in the core only when the msr ri bit is set, which guarantees machine restartability after a breakpoint. in this working mode, breakpoints are masked. there are times when it is preferable to enable breakpoints even when the msr ri bit is clear, even though there is a risk of causing a nonrestartable machine state. in programmable nonmasked mode, an external development system can choose to assert a nonmaskable external breakpoint. watchpoints are not masked and are always reported on the external pins, regardless of the value of the msr ri bit. the counters, although they are counting watchpoints, are part of the internal breakpoint logic and are not decremented when the core is in masked mode and the msr ri bit is clear. internal watchpoints are generated when a user-programmable set of conditions are met. internal breakpoints can be programmed to be generated either when one of the internal watchpoints is asserted or after an internal watchpoint is asserted for user-programmable times. programming a certain internal watchpoint to generate an internal breakpoint can be accomplished either in the software by setting the corresponding software trap enable bit or on-the-fly using the serial interface of the development port to set the corresponding trap enable bit. external breakpoints can be generated by any of the system peripherals, including those found on or outside the mpc823e or those found by an external development system. peripherals on the external bus use the serial interface of the development port to assert an external breakpoint. 20.3.1 internal watchpoints and breakpoints internal watchpoints and breakpoints are used in software debugging and the sources are illustrated in figure 20-1. for the recoverable interrupt bit of the msr, see section 6 the powerpc core . watchpoints do not stop your code from executing, but they indicate when you have passed a certain testing point. breakpoints are actually the points at which execution is stopped. for more information on external breakpoint support, refer to section 20.4 hardware development system interface . internal breakpoint and watchpoint support is based on: ? eight comparators that compare information on instruction and load/store cycles ? two counters ? two and-or logic structures the comparators perform a comparison on the instruction address (i-address), the load/ store address (l-address), and the load/store data (l-data). the comparators can detect the following conditions: ? equal to ? not equal to ? greater than ? less than
development capabilities and interface 20-10 mpc823e reference manual motorola development 20 capabilities & interface greater-than-or-equal-to and less-than-or-equal-to are easily obtained from these four conditions. refer to section 20.3.1.5 generating compare types for more information. using the and-or logic structures in range and out of range, detections of address and data comparators are supported. using the counters, you can program a breakpoint to be recognized after an event has been detected after a predefined number of times. the l-data comparators operate on load or store fixed-point data. when operating on fixed-point data, the l-data comparators perform a comparison on bytes, half-words, and words. they treat numbers as either signed or unsigned values. the comparators generate match events and then instruction match events enter the instruction and-or logic where the instruction watchpoints and breakpoint are generated. the asserted instruction watchpoints can generate the instruction breakpoint. two different events can decrement one of the counters. when a counter on one of the instruction watchpoints expires, the instruction breakpoint is asserted. figure 20-1. watchpoint and breakpoint support in the core internal peripherals x x x x development system or external peripherals development port lctrl2 msr internal watchpoints logic watchpoints msr ri nonmasked control bit software trap enable bits development port trap enable bits nonmaskable breakpoint maskable breakpoint cpm code development accessible bit wise and bit wise or counters breakpoint to cpu to watchpoint pins
development capabilities and interface motorola mpc823e reference manual 20-11 development 20 capabilities & interface the instruction watchpoints and load/store match events on the address/data comparators enter the load/store and-or logic where the load/store watchpoints and breakpoint are generated. when asserted, the load/store watchpoints can generate the load/store breakpoint or decrement one of the counters. when a counter on one of the load/store watchpoints expires, the load/store breakpoint is asserted. watchpoints progress in the machine and are reported when they retire. internal breakpoints progress in the machine until they reach the top of the history buffer when the machine branches to the breakpoint exception routine. so the breakpoint features can be used without restricting the software, the address of the load/store cycle that generated the load/store breakpoint is not stored in the data address register (dar). in a load/store breakpoint, the address of the load/store cycle that generated the breakpoint is stored in the breakpoint address register (bar). there are many types of internal watchpoints and breakpoints: ? four i-address comparators supporting equal, not equal, greater than, and less than. ? two l-address comparators supporting equal, not equal, greater than, and less than. ? two l-data comparators supporting equal, not equal, greater than, and less than. ? no internal breakpoint or watchpoint support for unaligned words and half-words. ? the l-data comparators can be programmed to treat fixed-point numbers as signed or unsigned values. ? combined comparator pairs to detect in and out of range conditions, including either signed or unsigned values on the l-data. ? a programmable and-or logic structure between the four instruction comparators results in five outputs, four instruction watchpoints, and one instruction breakpoint. ? a programmable and-or logic structure between the four instruction watchpoints and the four load/store comparators results in three outputs, two load/store watchpoints, and one load/store breakpoint. ? five watchpoint pins, three for the instruction and two for the load/store. ? two dedicated 16-bit down counters. each can be programmed to count either an instruction watchpoint or a load/store watchpoint. only architecturally executed events are counted. ? on-the-fly trap enable programming of the different internal breakpoints using the serial interface of the development port. software control is also available. ? watchpoints do not change the timing of the machine. ? internal breakpoints and watchpoints are detected on the instruction during instruction fetch. ? internal breakpoints and watchpoints are detected on the load/store during load/ store bus cycles. ? instruction and load/store breakpoints and watchpoints are handled on retirement and then reported.
development capabilities and interface 20-12 mpc823e reference manual motorola development 20 capabilities & interface ? breakpoints and watchpoints on recovered instructions (as a result of exceptions, interrupts, or miss prediction) are not reported and do not change the timing of the machine. ? instructions with instruction breakpoints are not executed. the machine branches to the breakpoint exception routine before it executes the instruction. ? instructions with load/store breakpoints are executed. the machine branches to the breakpoint exception routine after it executes the instruction. the address of the access is placed in the breakpoint address register. ? load/store multiple and string instructions with load/store breakpoints first finish execution and then the machine branches to the breakpoint exception routine. ? load/store data compare is made on the load/store, after swap in store accesses and before swap in load accesses (as the data appears on the bus). ? internal breakpoints operate with a context-dependent filter. ? both go to x and continue working modes are supported for instruction breakpoints. 20.3.1.1 restrictions. there are times when the same watchpoint can be detected more than once during the execution of a single instruction. for example, a load/store watchpoint detected on more than one transfer when executing load/store multiple/string or load/store watchpoint detected on more than one byte when working in byte mode. in these cases, only one watchpoint of the same type is reported for a single instruction. similarly, only one watchpoint of the same type can be counted in the counters for a single instruction. since watchpoint events are reported when the instruction that caused the event retires (more than one instruction can retire from the machine in a single clock), ensuing events can be reported in the same clock. moreover, if the same event is detected on more than one instruction (tight loops or range detection), it can just be reported once. the internal counters count correctly in these cases. 20.3.1.2 byte and half-word working modes. you can use watchpoints and breakpoints to detect matches on bytes and half-words when the byte/half-word is accessed in a load/store instruction of larger data widths. for example, when loading a table of bytes using a series of load word instructions. to use this feature in word mode, you must write the required match value to the correct half-word of the data comparator and to the mask in the l-data comparator. if you prefer to break on bytes, the byte mask for each l-comparator and the bytes to be matched must be written in the data comparator. since bytes and half-words can be accessed using a larger data width instruction, it is impossible for you to predict the exact value of the l-address lines when the requested byte/ half-word is accessed. if the matched byte is byte 2 of the word and is accessed using a load word instruction, the l-address value will be of the word (byte 0). therefore, the core masks the two least-significant bits of the l-address comparators when a word access is performed and the least-significant bits when a half-word access is performed. address range is only supported when aligned according to the access size.
development capabilities and interface motorola mpc823e reference manual 20-13 development 20 capabilities & interface byte working mode example data size: byte. address: 0x00000003. data value: greater than 0x07 and less than 0x0c. programming options: one l-address comparator = 0x00000003 and program for equal. one l-data comparator = 0x00000007 and program for greater than. one l-data comparator = 0x0000000c and program for less than. cgbmsk and chbmsk fields of the lctrl1 = 0xe. both l-data comparators program to byte mode. result: the event will be correctly detected, regardless of the load/store instruction the compiler chooses for this access. half-word working mode example 1 data size: half-word. address: greater than 0x00000000 and less than 0x0000000c. data value: greater than 0x4e204e20 and less than 0x9c409c40. programming option: one l-address comparator = 0x00000000 and program for greater than. one l-address comparator = 0x0000000c and program for less than. one l-data comparator = 0x4e204e20 and program for greater than. one l-data comparator = 0x9c409c40 and program for less than. cgbmsk and chbmsk fields of the lctrl1 = 0xe. both l-data comparators program to half-word mode. result: the event will be correctly detected as long as the compiler does not use a load/store instruction with a data size of byte.
development capabilities and interface 20-14 mpc823e reference manual motorola development 20 capabilities & interface half-word working mode example 2 data size: half-word. address: greater than or equal to 0x00000002 and less than 0x0000000e. data value: greater than 0x4e204e20 and less than 0x9c409c40. programming option: one l-address comparator = 0x00000001 and program for greater than. one l-address comparator = 0x0000000e and program for less than. one l-data comparator = 0x4e204e20 and program for greater than. one l-data comparator = 0x9c409c40 and program for less than. cgbmsk and chbmsk fields of the lctrl1 = 0xe. both l-data comparators program to half-word or word mode. result: the event will be correctly detected if the compiler chooses a load/store instruction with a data size of half-word. if the compiler chooses load/store instructions with a data size greater than half-word (word, multiple), there might be some false detections. this example uses figure 20-2 to show the possible false detects that must be ignored by the software that handles the breakpoints. 20.3.1.3 context-dependent filter. the core can only be programmed to recognize internal breakpoints when the msr ri bit is set or to always recognize internal breakpoints. when it is programmed only to recognize internal breakpoints or when msr ri = 1, all parts of the code can be debugged, except when the save and restore register 0 (srr0), save and restore register 1 (srr1), data address register (dar), and data storage interrupt status register (dsisr) are busy and msr ri = 0. figure 20-2. example 2 false detect on watchpoint/breakpoint 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 possible false detect on these half-words when using word/multiple
development capabilities and interface motorola mpc823e reference manual 20-15 development 20 capabilities & interface when the core is programmed to recognize internal breakpoints, you can debug all parts of the code. however, if an internal breakpoint is recognized when msr ri = 0 (registers srr0 and srr1 are busy), the machine enters into a nonrestartable state. for more information refer to section 6.3.4.1 restartability after an interrupt . when working in masked mode, all internal breakpoints that are detected when msr ri =0 are lost and detected watchpoints are not counted by the debug counters. detected watchpoints are always reported on the external pins, regardless of the value of the msr ri bit. the core defaults to masked mode after reset. it is input in the nonmasked mode by setting the brknomsk bit in the lctrl2 register.the brknomsk bit controls all internal breakpoints (i-breakpoints and l-breakpoints). see section 20.6.2.7 load/store support and-or control register for more information. 20.3.1.4 ignore first match option. to facilitate the debugger utilities of continue and go from x, the ignore first match option is supported for the instruction breakpoints. when an instruction breakpoint is first enabled, the first instruction will not cause an instruction breakpoint if the ifm bit in the instruction support control (ictrl) register is set. this is used for continue utilities. when ifm is clear, every matched instruction can cause an instruction breakpoint. this is used for go from x. the ifm bit is set by the software and cleared by the hardware after the first instruction breakpoint (the match is ignored). load/ store breakpoints and all counter-generated breakpoints (instruction and load/store) are unaffected by this mode. 20.3.1.5 generating compare types. using the four compare typesequal to, not equal to, greater than, and less thanit is possible to generate two additional compare types: ? greater than or equal to ? less than or equal to generating the greater than or equal to compare type can be accomplished by programming the comparator to the value in question plus or minus 1. notice that this method does not work for the following boundary cases: ? less than or equal to the largest unsigned number (1111...1) ? greater than or equal to the smallest unsigned number (0000...0) ? less than or equal to the maximum positive number when in signed mode (0111...1) ? greater than or equal to the maximum negative number when in signed mode (1000...) these boundary cases do not require special support because they are considered always true. they can be programmed using the ignore option of the load/store watchpoint programming. see section 20.6.2.7 load/store support and-or control register for more information.
development capabilities and interface 20-16 mpc823e reference manual motorola development 20 capabilities & interface 20.3.2 basic operation 20.3.2.1 instruction support. there are four instruction address comparators (a, b, c, and d). each one is 30 bits long and generates two output eventsequal to and less than. these signals generate one of four eventsequal to, not equal to, greater than, or less than. the instruction watchpoints and breakpoint are generated with these events according to your programming. using the or option enables out of range detect. figure 20-3. instruction support general structure compare type logic compare type logic compare type logic comparator eq lt compare type comparator eq lt comparator eq lt comparator eq lt events generator and-or logic control bits a b (a&b) (a | b) c d (c&d) (c | d) i - watchpoint 0 i - watchpoint 1 i - breakpoint i - watchpoint 2 i - watchpoint 3 compare type logic b c d a
development capabilities and interface motorola mpc823e reference manual 20-17 development 20 capabilities & interface 20.3.2.2 load/store support. there are two load/store address comparators (e and f) that compare the 32 address bits and the cycles attributes (read/write). the two least-significant bits are masked ignored when a word is accessed and the least-significant bit is masked when a half-word is accessed. each comparator generates two output signalsequal to and less than. these signals generate one of four events from each comparatorequal to, not equal to, greater than, or less than. for more information, refer to section 20.3.1.2 byte and half-word working modes . there are two load/store data comparators (g and h) that are 32 bits wide and can be programmed to treat numbers as signed or unsigned values. each data comparator operates as four independent byte comparators that have a mask bit and generate two output signalsequal to and less than (if the mask bit is not set.) therefore, each 32-bit comparator has eight output signals that generate the equal to and less than signals according to the compare size that you program (byte, half-word, word). when operating in byte mode, all signals are significant. in half-word mode only four signals from each comparator are significant and in word mode only two signals are significant. one of the following four match events are generated by the equal to and less than signalsequal to, not equal to, greater than, or less thandepending on the programmed compare type. therefore, from the two 32-bit comparators, eight match indications are generatedgmatch[0:3] and hmatch[0:3]. according to the lower bits of the address and the size of the cycle, only match indications detected on bytes with valid information are validated. the rest are negated. if the executed cycle has a smaller size than the compare size (a byte access when the compare size is word or half-word), no match indication will be asserted. using the match indication signals, four load/store data events are generated as shown in table 20-5. table 20-4. instruction watchpoints programming options name description programming options iw0 first instruction watchpoint comparator a comparators (a & b) iw1 second instruction watchpoint comparator b comparator (a | b) iw2 third instruction watchpoint comparator c comparators (c & d) iw3 fourth instruction watchpoint comparator d comparator (c | d)
development capabilities and interface 20-18 mpc823e reference manual motorola development 20 capabilities & interface the four load/store data events, combined with the match events of the load/store address comparators and the instruction watchpoints, are used to generate the load/store watchpoints and breakpoint according to your programming. when programming the load/store watchpoints to ignore l-address and l-data events, the instruction must be a load/store instruction to trigger the load/store watchpoint event. 20.3.2.3 counter support. there are two 16-bit down counters that count one of the instruction watchpoints or one of the load/store watchpoints. both generate the corresponding breakpoint when they reach zero. when working in masked mode, the counters do not count detected watchpoints when msr ri =0. counter values are not predictable if they are counting watchpoints programmed on the instructions that alter the counters. readings from the active counters must be synchronized by inserting a sync instruction before a read is performed. for details, refer to section 20.3.1.2 byte and half- word working modes . table 20-5. load/store data events event name event function g (gmatch0 | gmatch1 | gmatch2 | gmatch3) h (hmatch0 | hmatch1 | hmatch2 | hmatch3) (g & h) ((gmatch0 & hmatch0) | (gmatch1 & hmatch1) | (gmatch2 & hmatch2) | (gmatch3 & hmatch3)) (g | h) ((gmatch0 | hmatch0) | (gmatch1 | hmatch1) | (gmatch2 | hmatch2) | (gmatch3 | hmatch3)) note: & denotes a logical and, but | denotes a logical or. table 20-6. load/store watchpoints programming options name description i-address event programming options l-address event programming options l-data event programming options lw0 first load/store watchpoint iw0, iw1, iw2, iw3, ignore i-address events comparator e comparator f comparators (e & f) comparators (e | f) ignore l-address events comparator g comparator h comparators (g & h) comparators (g | h) ignore l-data events lw1 second load/ store watchpoint iw0, iw1, iw2, iw3, ignore i-address events comparator e comparator f comparators (e & f) comparators (e | f) ignore l-address events comparator g comparator h comparators (g & h) comparators (g | h) ignore l-data events
development capabilities and interface motorola mpc823e reference manual 20-19 development 20 capabilities & interface figure 20-4. load/store support general structure comparator g byte 0 eq lt compare compare add(30:31) data compare valid 0 valid 1 valid 2 valid 3 g h (g & h) (g | h) instruction l-watchpoint 0 l-watchpoint 1 l-breakpoint size logic compare byte qualifier logic events generator and-or logic control bits e f (e & f) (e | f) comparator e type logic events generator lt eq comparator f type logic lt eq compare type logic byte mask byte 1 byte 2 byte 3 eq lt eq lt eq lt eq lt eq lt eq lt eq lt size type comparator h byte 0 eq lt size logic compare byte qualifier logic type logic byte mask byte 1 byte 2 byte 3 eq lt eq lt eq lt eq lt eq lt eq lt eq lt type cycle size watchpoints size
development capabilities and interface 20-20 mpc823e reference manual motorola development 20 capabilities & interface 20.3.2.4 trap enable programming. the trap enable bits can be programmed by regular software (only if msr pr = 0) using the mtspr instruction or on-the-fly using the special development port interface. for more information, refer to section 20.4.3.7 trap enable mode . the value used by the breakpoint generation logic is the bit-wise or of the software trap enable bits written using the mtspr instruction and the development port trap enable bits that are serially shifted using the development port. the software trap enable bits and development port trap enable bits can be read from the ictrl and lctrl2 registers using the mtspr instruction. for exact bit placement, refer to section 20.6.2.7 load/store support and-or control register and section 20.6.2.5 instruction support control register . 20.4 hardware development system interface when debugging an existing system, it is sometimes helpful to be able to do so without making any changes. although, in some cases it is not helpful and may even make it impossible to add load to the lines connected to the existing system. to support this configuration, the development system interface of the core uses the development port, which is a dedicated serial port that does not need any of the regular system interfaces. system activity can be controlled from the development port when the core is in debug mode. the development port is a relatively inexpensive interface that allows the development system to operate in a lower frequency than the cores frequency. you can also debug the core using monitor debugger software, which is described in section 20.5 software monitor debugger . in debug mode, the core fetches all instructions from the development port. data can be read from or written to the development port. this allows memory and registers to be read and modified by a development tool (emulator) connected to the development port. for protection purposes, two possible working modes are defineddebug mode enable and debug mode disable. these working modes are only selected during reset. for details, refer to section 20.4.2.1 debug mode enable vs. debug mode disable . note: when programmed to count instruction watchpoints, the last instruction that decrements the counter to zero is treated like any other instruction breakpoint in that it is not executed before the machine branches to the breakpoint exception routine. as a side effect of this behavior, the value of the counter inside the breakpoint exception routine equals 1 and not zero. when programmed to count load/store watchpoints, the last instruction that decrements the counter to zero is treated like any other load/store breakpoint in that it is executed before the machine branches to the breakpoint exception routine. therefore, the value of the counter inside the breakpoint exception routine equals zero.
development capabilities and interface motorola mpc823e reference manual 20-21 development 20 capabilities & interface you can work in debug mode directly out of reset or the core can be programmed to enter into the debug mode as a result of a predefined sequence of events. these events can be any interrupt or exception in the core system (including the internal breakpoints) in addition to two levels of development port requests and one peripheral breakpoint request generated internally and externally. each of these can be programmed as a regular interrupt that causes the machine to branch to its interrupt vector or as a special interrupt that causes debug mode entry. when in debug mode, the rfi instruction returns the machine to its regular work mode. the relationship between debug mode logic and the rest of the core is illustrated in the following figure. the development port provides a full-duplex serial interface for communication between the internal development support logic of the core and an external development tool. the development port can operate in two working modestrap enable mode and debug mode. figure 20-5. relationship between the cpu and debug mode development port development port icr der core 9 control logic shift register bkpt, te, vsync dpir dsck dsdi tecr dpdr 35 32 32 internal bus development port support logic dsdo vfls, frz ext bus siu / ebi
development capabilities and interface 20-22 mpc823e reference manual motorola development 20 capabilities & interface 20.4.1 trap enable mode the trap enable mode allows the following incidents to transfer control into the core internal development support logic. ? an instruction trap enable signal is used to program the instruction breakpoint on-the-fly. ? a load/store trap enable signal is used to program the load/store breakpoint on-the-fly. ? a nonmaskable breakpoint is used to assert the nonmaskable external breakpoint. ? a maskable breakpoint is used to assert the maskable external breakpoint. ? a vsync control code is used to assert and negate vsync operation. in debug mode, the development port also controls the debug mode features of the core. for more details, refer to section 20.4.3 the development interface port . 20.4.2 debug mode debug mode provides the development system with the following functions: ? controls and maintains all circumstances of processor execution. ? the development port can force the core to enter debug mode even when the external interrupts are disabled. ? debug mode can be entered immediately out of reset, thus allowing you to debug a system without rom. ? the events that cause the machine to enter into debug mode can be selectively defined through an enable register. ? contains a cause register that indicates why debug mode is entered. ? after entering debug mode, program execution continues where it first entered debug mode. ? all instructions are fetched from the development port, while load/store accesses are performed on the real system memory in debug mode. ? a simple method is provided for memory dump and load via the data register of the development port that is accessed with mtspr and mfspr . ? the processor enters the privileged state (msr pr =0) in debug mode, thus allowing execution of any instruction and access to any storage location. ? an or signal of all interrupt cause register bits enables the development port to detect pending events while in debug mode. for example, the development port can detect a debug mode access to nonexisting memory space.
development capabilities and interface motorola mpc823e reference manual 20-23 development 20 capabilities & interface figure 20-6 illustrates the debug mode logic implemented in the core. figure 20-6. debug mode logic implementation debug enable register (der) interrupt cause register (icr) event (core interrupt set reset icr_or freeze rfi decoder q debug mode enable internal debug 5 event valid mode signal or exception)
development capabilities and interface 20-24 mpc823e reference manual motorola development 20 capabilities & interface 20.4.2.1 debug mode enable vs. debug mode disable. for protection purposes, there are two possible working modesdebug mode enable and debug mode disable. these modes are selected at reset. debug mode is enabled by asserting the dsck pin during reset and the state of this pin is sampled three clocks before sreset negation. if the dsck pin is sampled negated, debug mode is disabled until a subsequent reset that occurs when the dsck pin is asserted. when debug mode is disabled, the internal watchpoint/breakpoint hardware is still operational and can be used by a software monitor program for debugging purposes. a timing diagram for the enabling debug mode is illustrated in figure 20-7 when debug mode is disabled, all development support registers are accessible when msr pr =0 and can be used by the monitor debugger software. however, the processor never enters debug mode and the icr and der are only used to assert or negate the freeze signal. for more information on the software monitor debugger, refer to section 20.5 software monitor debugger . only when the core is in debug mode are all development support registers accessible. therefore, the development system has full control of the cores development support features. for more information, see table 20-12 . 20.4.2.2 entering debug mode. debug mode entry can be the result of a number of events. all events have a programmable enable bit so you can discover the cause of debug mode entry, as well as the events that require regular interrupt handling. by programming the development port, you can enter debug mode immediately out of reset, thus allowing a system to be debugged without rom. if the dsck pin is asserted during sreset assertion and after sreset negation, the processor will take a breakpoint exception and go directly to debug mode, instead of fetching the reset vector. note: sreset negation time depends on an external pull-up resistor, so any reference to sreset negation time refers to the time the mpc823e releases sreset . if the rise time of sreset is long because of a large resistor, the setup time for the debug port signals must be adjusted accordingly.
development capabilities and interface motorola mpc823e reference manual 20-25 development 20 capabilities & interface figure 20-7. debug mode reset configuration timing diagram dsck clkout sreset dsck asserts high while sreset asserted to enable debug mode operation. 012345891011121314151617 dsck asserts high following sreset negation to enable debug mode immediately.
development capabilities and interface 20-26 mpc823e reference manual motorola development 20 capabilities & interface to avoid entering debug mode after reset, the dsck pin must be negated no later than seven clock cycles after sreset negates to allow the processor to jump to the reset vector and begin normal execution. when you enter debug mode immediately after reset, the dpi bit of the interrupt cause register (icr) is set. for details, refer to the timing diagram illustrated in figure 20-7. when debug mode is disabled, all events result in regular interrupt handling. the internal freeze signal is asserted when an enabled event occurs, regardless of whether debug mode is enabled or disabled. the internal freeze signal is connected to all relevant internal modules. these modules can be programmed to stop all operations in response to the assertion of the freeze signal. for more information, refer to section 20.5.1 freeze indication (frz) . furthermore, the freeze indication is negated when exiting the debug mode and section 20.4.2.6 exiting debug mode has more information on the issue. the following list of events can cause the core to enter debug mode. each event results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. the reset values of the enable bits allow you to use debug mode features even when debug enable mode is not programmed in the der (described in section 20.6.3.2 debug enable register ). ? system reset as a result of sreset assertion ? checkstop ? machine check interrupt ? implementation specific instruction tlb miss ? implementation specific instruction tlb error ? implementation specific data tlb miss ? implementation specific data tlb error ? external interrupt, recognized when msr ee =1 ? alignment interrupt ? program interrupt ? floating-point unavailable interrupt ? decrementer interrupt, recognized when msr ee =1 ? system call interrupt ? trace asserted when in single or branch trace mode ? implementation-dependent software emulation interrupt ? instruction breakpoint is recognized only when msr ri =1 and when breakpoints are masked. when breakpoints are not masked, they are always recognized. ? load/store breakpoint is recognized only when msr ri = 1 and when breakpoints are masked. when breakpoints are not masked, they are always recognized.
development capabilities and interface motorola mpc823e reference manual 20-27 development 20 capabilities & interface ? peripheral breakpoint from the development port generated by external modules are recognized only when msr ri =1. ? development port nonmaskable interrupt occurs as a result of a debug station request. useful in some catastrophic events, such as an endless loop when msr ri =0. as a result of this event, the machine can enter a nonrestartable state. the processor enters into the debug mode state when at least one of the bits in the icr is set, the corresponding bit in the der is enabled, and debug mode is enabled. when debug mode is enabled and an enabled event occurs, the processor waits until its pipeline is empty and then starts fetching the next instructions from the development port. for information on the exact value of the srr0 and srr1 registers, refer to section 7.3.7.3 definitions . when the processor is in debug mode, the freeze indication is asserted, thus allowing any properly programmed peripheral to stop. the fact that the core is in debug mode is also broadcasted to the external world using the value b11 on the vfls pins. the freeze signal can be asserted by the software when debug mode is disabled. the development port must read the value of the icr to discover the cause of debug mode entry. reading the icr clears all of its bits. 20.4.2.3 checkstop state and debug mode. the core enters checkstop state if the machine check interrupt is disabled (msr me =0) and a machine check interrupt is detected. however, if a machine check interrupt is detected when msr me =0, debug mode is enabled, the checkstop enable bit in the der is set, and the core enters debug mode rather than the checkstop state. the various actions taken by the core when a machine check interrupt is detected are provided in the following table. table 20-7. checkstop state and debug mode debug mode enable msr me chstpe 1 mcie 2 action performed by the core when a machine check interrupt is detected icr value 0 0 x x enter checkstop state 0x20000000 0 1 x x branch to the machine check interrupt 0x10000000 1 0 0 x enter checkstop state 0x20000000 1 0 1 x enter debug mode 0x20000000 1 1 x 0 branch to the machine check interrupt 0x10000000 1 1 x 1 enter debug mode 0x10000000 notes: 1. the checkstop enable bit of the der register. 2. the machine check interrupt enable bit of the der register.
development capabilities and interface 20-28 mpc823e reference manual motorola development 20 capabilities & interface 20.4.2.4 saving the machine state in debug mode. if entering debug mode is the result of a load/store-type exception, the dar and dsisr registers contain critical information. these two registers must be saved before any other operation is performed. failing to save these registers can result in information loss if another load/store-type exception occurs inside the development software. since exceptions are treated differently in debug mode, there is no need to save the srr0 and srr1 registers. 20.4.2.5 running in debug mode. when running in debug mode, all fetch cycles access the development port, regardless of the cycles actual address. all load/store cycles access the real memory system according to the cycles address. the data register of the development port is mapped as a special control register and is accessed using the mtspr and mfspr instructions, via special load/store cycles. exceptions are treated differently in debug mode. when in debug mode, the icr is updated when an exception is recognized by the event that caused the exception. a special error indication (icr_or) is asserted for one clock cycle to notify the development port that an exception has occurred. execution then continues in debug mode without any change in the srr0 and srr1 registers. icr_or is asserted before the next fetch occurs so the development system can detect the excepting instruction. however, not all exceptions are recognizable in debug mode. breakpoints and watchpoints are not generated by the hardware when in debug mode, regardless of the msr ri bits value. when entering debug mode, the msr ee bit is cleared by the hardware, thus forcing the hardware to ignore external and decrementer interrupts. this restriction is relevant because the external interrupt event is a level signal. because the core only reports exceptions in debug mode and does not perform exception processing, the core hardware does not clear the msr ee bit. this event, if enabled, is then recognized on every clock. when the icr_or signal is asserted, the development station must search the icr to find the event that caused the exception. since the values in the srr0 and srr1 registers do not change if an exception is recognized in debug mode, they only change when entering debug mode. however, it is not necessary to save the srr0 and srr1 registers when entering debug mode. 20.4.2.6 exiting debug mode. the rfi instruction is used to exit from debug mode and return to normal processor operation and negate the frz signal. the development system may monitor the frz signal or status to make sure the mpc823e is out of debug mode. it is the softwares responsibility to read the icr before performing the rfi instruction. failure to do so forces the core to immediately reenter debug mode and reassert the freeze signal if an asserted bit in the icr register has a corresponding enable bit set in the der register. caution: setting the msr ee bit with the debug software in debug mode is strictly forbidden.
development capabilities and interface motorola mpc823e reference manual 20-29 development 20 capabilities & interface 20.4.3 the development interface port the development port provides a full-duplex serial interface for communication between the internal development support logic and an external development tool. the relationship of the development support logic to the rest of the core is illustrated in figure 20-5 (page 20-21). notice that the development port support logic is shown as a separate block for clarity. it will be implemented as part of the system interface unit module. the development interface port contains four pins: ? development serial clock ? development serial data in ? development serial data out ? freeze 20.4.3.1 development serial clock. the development serial clock (dsck) pin is used to shift data into and out of the development interface port shift register. at the same time, the new most-significant bit of the shift register is presented to the development serial data out (dsdo) pin. future references to the dsck signal imply the internally synchronized value of the clock. the dsck input must be driven either high or low at all times and is not allowed to float. with a resistor, a typical target environment would pull this input low. the clock can be implemented as a free-running or gated clock. the shifting of data is controlled by the ready and start signals, so the clock does not need to be gated with the serial transmissions. the dsck pin is used at reset to enable debug mode immediately following reset or when driving an event. 20.4.3.2 development serial data in. data to be transferred into the development interface port shift register is presented to the development serial data in (dsdi) pin by external logic. when driven asynchronous with the system clock, the data presented to the dsdi pin must be stable at setup time before the rising edge of dsck and at hold time after the rising edge of dsck. when synchronously driven to the system clock, the data must be stable on dsdi or a setup time before a system clock output (clkout) rising edge and a hold time after the rising edge of clkout. the dsdi pin is also used at reset to control the overall chip configuration mode and to determine the development port clock mode. refer to section 20.4.3.6 development port serial communication for more information. 20.4.3.3 development serial data out. the debug mode logic shifts data out of the development interface port shift register using the development serial data out (dsdo) pin. all transitions on dsdo are synchronous with dsck or clkout, depending on the clock mode. data will be valid at setup time before the rising edge of the clock and remains valid at hold time after the rising edge of the clock. see table 20-10 for details about dsdo data.
development capabilities and interface 20-30 mpc823e reference manual motorola development 20 capabilities & interface 20.4.3.4 freeze. a freeze indication means that the processor is in debug mode and that normal processor execution of user code is frozen. the freeze state is indicated on the frz pin and is generated synchronous to the system clock. this indication can be used to halt any off-chip device while in debug mode and is a handshake between the debug tool and port. in addition to the frz pin, the freeze state is indicated by the value b11 on the vfls pins. the internal freeze status can also be monitored through status in the data shifted out of the debug port. 20.4.3.5 development interface port registers. the development interface port consists logically of three registersdevelopment interface port instruction register, development interface port data register, and trap enable control register. however, these registers (dpir/dpdr) are physically implemented as two registersthe development interface port shift register and the trap enable control register (tecr). the development interface port shift register acts as both the dpir and dpdr, depending on the operation being performed. it is also used as a temporary holding register for data to be stored in the tecr. see table 6-9 for more information and the dpir and dpdr registers. 20.4.3.5.1 development interface port shift register. the development interface port shift register (dpir/dpdr) is a 35-bit shift register. instructions and data are serially shifted into it from the dsdi using dsck or clkout as the shift clock, which depends on the debug port clock mode. for more information, refer to section 20.4.3.6 development port serial communication . figure 20-8. development port/background development mode connector pinout options 12 3 4 56 78 910 12 3 4 56 78 910 vfls0 gnd gnd hreset v sreset dsck vfls1 dsdi dsdo dd frz gnd gnd hreset v sreset dsck frz dsdi dsdo dd
development capabilities and interface motorola mpc823e reference manual 20-31 development 20 capabilities & interface the instructions or data are then transferred in parallel to the core and tecr. when the processor enters debug mode it fetches instructions from the dpir, which causes an access to the development interface port shift register. these instructions are serially loaded into the shift register from the dsdi using dsck or clkout as the shift clock. similarly, data is transferred to the core. data is shifted into the shift register and read by the processor when a move from special-purpose register dpdr instruction is executed. data is also parallel loaded into the development interface port shift register from the core by executing a move to special-purpose register dpdr instruction. it is then serially shifted out to the dsdo pin using dsck or clkout as the shift clock. 20.4.3.5.2 trap enable control register. the 9-bit trap enable control register (tecr) is loaded from the development interface port shift register. the content of the tecr drives the six trap enable signals, two breakpoint signals, and the vsync signal to the core. the transfer data to trap enable control register commands are used to force the appropriate bits to be transferred to this register. the trap enable control register is not accessed by the core, but supplies signals to the core. the trap enable bits, vsync bit, and the breakpoint bits of this register are loaded from the development interface port shift register as a result of trap enable mode transmissions. the trap enable bits are reflected in the ictrl and lctrl2 special registers. refer to section 20.6.2 development port registers for more information on the support registers. 20.4.3.5.3 decoding the development interface port registers. the development interface port shift register is selected when the core accesses the dpir or dpdr registers. accesses to these two special-purpose registers occur in debug mode and appear on the internal bus as an address and when an address attribute signal is asserted, a special- purpose register is accessed. the dpir is read by the core to fetch all instructions when in debug mode. the dpdr is read and written to transfer data between the core and external development tools. the dpir and dpdr are pseudo-registers, so decoding either of these registers causes the development interface port shift register to be accessed. the debug mode logic knows whether the core is fetching instructions or reading or writing data. a sequence error is signaled to the external development tool when the expected result of the core and the gpr do not match. for example, when an instruction is received instead of the expected data. 20.4.3.6 development port serial communication. all serial transmissions are synchronous, with respect to the transmission clock. 20.4.3.6.1 clock mode selection. with the exception of clkout, the transmission clock can either be synchronous or asynchronous. the development port has two methods for clocking serial transmissions. the first method allows the transmission to occur with no external synchronization to clkout. in this mode, a serial clock dsck must be supplied to the mpc823e. the other communication method requires data to be externally synchronized.
development capabilities and interface 20-32 mpc823e reference manual motorola development 20 capabilities & interface the first clock mode is called asynchronous clocked since the input clock dsck is asynchronous, except for clkout. to be sure that data on dsdi is sampled correctly, transitions on dsdi must meet all setup and hold times related to the rising edge of dsck. this clock mode allows communication with the port from a development tool that does not have access to the clkout signal or has either a delayed or skewed clkout signal. the timing diagram in figure 20-9 illustrates serial communication asynchronous clocked timing. the second clock mode is called synchronous self-clocked and does not require an input clock. instead, the port is clocked by the system clock. the dsdi input is required to meet setup and hold time requirements, with respect to the rising edge of clkout. the data rate for this mode is always the same as the system clock. the timing diagram in figure 20-10 illustrates serial communication synchronous self-clocked timing. clocked or self-clocked mode is selected at reset. the state of the dsdi input is latched eight clocks after sreset is negated. if it is latched low, asynchronous clocked mode is enabled. if it is latched high, then synchronous self-clocked mode is enabled. the timing diagram in figure 20-11 illustrates the clock mode selection following reset. since dsdi is used to select the development port clock scheme, any transitions on dsdi during clock mode selection must not be recognized as the start of a serial transmission. the port will not begin scanning for the start bit of a serial transmission until 16 clocks after sreset is negated. if dsdi is asserted 16 clocks after sreset negates, the port waits until dsdi is negated before it starts scanning for the start bit. 20.4.3.7 trap enable mode. when the development port is not in debug mode, it begins communicating by setting the dsdo field (the msb of the 35-bit development interface port shift register) low to indicate that all activity related to the previous transmission is complete and that a new transmission can begin. the start of a serial transmission from an external development tool to the development port is signaled by a start bit. a mode bit in the transmission defines it as either a trap enable mode or debug mode transmission. if the mode bit is set, the transmission will be 10 bits long and only seven data bits will be shifted into the shift register. these seven bits will be latched into the tecr. a control bit determines whether the data is latched into the tecrs trap enable, vsync, or breakpoints bits. the development interface port shift register is 35 bits wide, but trap enable mode transmissions only use 10 of the 35 bitsstart/ready, mode/status, control/status, and seven least-significant data bits. the encoding of data shifted into the development interface port shift register is shown in table 20-8 and table 20-9.
development capabilities and interface motorola mpc823e reference manual 20-33 development 20 capabilities & interface figure 20-9. asynchronous clocked serial communications timing diagram dsck dsdi mode cntrl di<0> s<0> s<1> do<0> start ready dsdo debug port drives the ready bit onto dsdo when ready for a new transmission. note: dsck and dsdi transitions are not required to be synchronous with clkout. di di di do do do debug port detects the start bit on dsdi and follows the ready bit with two status bits and 7 or 32 output data bits. development tool drives the start bit on dsdi (after detecting the ready bit on dsdo when in debug mode). the start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits.
development capabilities and interface 20-34 mpc823e reference manual motorola development 20 capabilities & interface figure 20-10. synchronous self-clocked serial communications timing diagram clkout debug port drives the ready bit onto dsdo when the cpu starts a read of dpir or dpdr. dsdi mode cntrl di<0> start di<1> s<0> s<1> do<0> ready dsdo do<1> do do do do di di di di debug port detects the start bit on dsdi and follows the ready bit with two status bits and 7 or 32 output data bits. development tool drives the start bit onto dsdi (after detecting the ready bit on dsdo when in debug mode). the start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits.
development capabilities and interface motorola mpc823e reference manual 20-35 development 20 capabilities & interface figure 20-11. enabling clock mode following reset timing diagram dsdi clkout sreset dsdi negates following sreset negation to enable clocked mode. clken 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 first start bit detected after dsdi negation (self-clocked mode). the internal clock enable signal asserts 8 clocks after sreset negation if dsdi is negated. this enables clocked mode.
development capabilities and interface 20-36 mpc823e reference manual motorola development 20 capabilities & interface the watchpoint trap enable and vsync functions are described in section 20.3 generating watchpoints and breakpoints and section 20.2 program flow tracking . the debug port command allows the development tool to either assert or negate breakpoint requests, reset the processor, or activate or deactivate the fast download procedure. status out of the development interface port in the trap enable mode is shown in table 20-10. table 20-8. trap enable data shifted into dps register start mode control first second third fourth first second vsync function instruction watchpoint trap enables data watchpoint trap enables 1 1 0 0 = disabled 1 = enabled transfer data to trap enable control register table 20-9. debug port command shifted into the dps register start mode control extended opcode major opcode function 1 1 1 x x 00000 nop 00001 hard reset request 00010 soft reset request 0 x 00011 reserved 1 0 00011 end download procedure 1 1 00011 start download procedure x x 00100 11110 reserved x 0 11111 negate maskable breakpoint x 1 11111 assert maskable breakpoint 0 x 11111 negate nonmaskable breakpoint 1 x 11111 assert nonmaskable breakpoint
development capabilities and interface motorola mpc823e reference manual 20-37 development 20 capabilities & interface in trap enable mode the valid data from cpu and cpu interrupt status cannot occur. out of debug mode, the sequencing error encoding indicates that the transmission from the external development tool was a debug mode transmission. when a sequencing error occurs, the development interface port ignores the data shifted in while the sequencing error is shifting out and being treated as a no operation (nop) function. the null output encoding indicates that the previous transmission did not have any associated errors. out of debug mode, ready will be asserted at the end of each transmission. if debug mode is not enabled and transmission errors are guaranteed not to occur, the status output is not needed. 20.4.3.8 debug mode. in debug mode, the development interface port starts communicating by setting the dsdo field low to indicate that the core is trying to read an instruction from the dpir or data from the dpdr. when the core writes data to the port to be shifted out, the ready bit is not set. the port waits for the core to read the next instruction before asserting ready. this allows duplex operation of the serial port while allowing the port to control all transmissions from the external development tool. after detecting this ready status, the external development tool begins transmitting the development interface port with a start bit (logic high) on the dsdi pin. in debug mode, the 35 bits of the development interface port shift register are interpreted as a start/ready bit, a mode/status bit, a control/status bit, and 32 bits of data. all instructions and data for the core are transmitted with the mode bit cleared, thus indicating a 32-bit data field. the encoding of data shifted into the development interface port shift register through the dsdi pin is shown in table 20-11. table 20-10. status/data shifted out of dps register ready status [0:1] data function bit 0 bit 1 bits 2-31 or 2-6, depending on the input mode (0) 0 0 data valid data from core (0) 0 1 freeze status download procedure in progress all 1s sequencing error (0) 1 0 all 1s core interrupt (0) 1 1 all 1s null note: for freeze status, 0 means the core is in normal mode and 1 means the core is in debug mode. for download status, 0 means the download is in progress and 1 means the core is in normal mode.
development capabilities and interface 20-38 mpc823e reference manual motorola development 20 capabilities & interface all transmissions from the debug port on dsdo begin with a zero or ready bit. this indicates that the core is trying to read an instruction or data from the port. the external development tool waits until it sees dsdo go low before it starts sending the next transmission. the control bit differentiates between instructions and data that allow the development interface port to detect an instruction that was entered when the core was expecting data and vice versa. if this occurs, a sequence error indication is shifted out in the next serial transmission. the trap enable function allows the development interface port to transfer data to the trap enable control register. the debug port command allows the development tool to either negate breakpoint requests, reset the processor, or activate or deactivate the fast download procedure. the nop function provides a null operation to use when there is data or a response to be shifted out of the data register. the next appropriate instruction or command will be determined by the value of the response or data shifted out. the encoding of data shifted out of the development interface port shift register in debug mode is the same for trap enable mode, as shown in table 20-10. the valid data encoding is used when data has been transferred from the core to the development interface port shift register. this results when an instruction to move the contents of a general-purpose register to the dpdr occurs. the valid data encoding has the highest priority of all status outputs and will be reported even if an interrupt occurs at the same time. since it is not possible for a sequencing error to occur that has valid data, there is no priority conflict with the sequencing error status. also, any interrupt that is recognized at the same time that there is valid data, is not related to the execution of an instruction. therefore, a valid data status will be output and the interrupt status will be saved for the next transmission. table 20-11. debug instructions/data shifted into the dps register start mode control instruction / data (32 bits) function bits 0:6 bits 7:31 1 0 0 cpu instruction transfer instruction to core 1 0 1 cpu data transfer data to core 1 1 0 trap enable bits not exist transfer data to trap enable control register 1 1 1 0011111 not exist negate breakpoint requests to core 1 1 1 0 not exist nop note: see table 20-8 for details on trap enable bits and table 20-9 for details on debug port commands.
development capabilities and interface motorola mpc823e reference manual 20-39 development 20 capabilities & interface the sequencing error encoding indicates that the external development tool inputs are not what the development interface port and/or the core was expecting. there are two possible causes of this error: ? the processor was trying to read instructions and data was shifted into the development interface port. ? the processor was trying to read data and an instruction was shifted into the development interface port. nonetheless, the port terminates the read cycle with a bus error. in turn, this bus error causes the core to signal that an interrupt exception has occurred. since a status of sequencing error is of higher priority than an exception, the port reports the sequencing error first and the core interrupt on the next transmission. the development interface port ignores the command, instruction, or data shifted in while the sequencing error or core interrupt is shifted out. the next transmission, after the error status is reported to the port, must be either a new instruction, trap enable, or command. the interrupt encoding that has occurred indicates that the core encountered an interrupt while executing the previous instruction in debug mode. interrupts can occur as the result of instruction execution (such as unimplemented opcode or arithmetic error), because of a memory access fault, or from an unmasked external interrupt. when an interrupt occurs, the development interface port ignores the command, instruction, or data shifted in while the interrupt encoding was shifting out. the next transmission to the port must be a new instruction, trap enable, or debug port command. finally, the null encoding indicates that no data has been transferred from the core to the development interface port shift register. the fast download procedure is used to download a block of data from the debug tool into the system memory. this procedure can be accomplished by repeating the following sequence of transactions from the development tool to the debug port for the number of data words to be downloaded. init:save rx, ry ry <- memory block address- 4 ??? repeat:mfspr rx, dpdr data word to be moved to memory stwu rx, 0x4(ry) until here ??? restore rx,ry figure 20-12. download procedure code example
development capabilities and interface 20-40 mpc823e reference manual motorola development 20 capabilities & interface for large blocks of data, this sequence can take a significant amount of time to complete. using the fast download procedure of the debug port will reduce the amount of time by eliminating the need to transfer the instructions in the loop to the debug port. the only transactions needed are those used to transfer the data to be placed in the system memory. figure 20-13 and figure 20-14 illustrate the benefit of using the fast download procedure. the sequence of the instructions used in the fast download procedure is illustrated in figure 20-12, with rx = r31 and ry = r30. this sequence is repeated infinitely until the end download procedure command is issued to the debug port. the internal general-purpose register 31 is used for temporary storage of the data value. before beginning the fast download procedure by issuing the start download procedure command, the value (of the first memory block address -4) must be written into the general-purpose register 30. to end the download procedure, an end download procedure command must be issued to the debug port and the development tool will send an additional data transaction. this data word will not be placed into the system memory, but it is needed to stop the procedure. 20.5 software monitor debugger when in debug mode disable, a software monitor debugger can use all of the development support features defined in the core. when debug mode is disabled, all events result in regular interrupt handling, in which the processor resumes execution in the corresponding interrupt handler. the icr and der only influence the assertion and negation of the freeze signal. figure 20-13. slow download procedure loop figure 20-14. fast download procedure loop external mfspr data stwu transaction internal activity external data transaction internal activity
development capabilities and interface motorola mpc823e reference manual 20-41 development 20 capabilities & interface 20.5.1 freeze indication (frz) the internal freeze signal is connected to all relevant internal modules that can be programmed to stop all operations in response to freeze signal assertion. to enable a software monitor debugger to signal that the debug software is now executed, the internal freeze signal can be asserted or negated when debug mode is disabled. assertion of the freeze signal is broadcasted to the external world over frz. asserting and negating the freeze signal when in disabled debug mode is controlled by the icr and der, as illustrated in figure 20-6. to assert the frz signal, the software must be programmed to use the relevant bits in the der. to negate the frz signal, the software must read the icr to clear it and perform an rfi instruction. if the icr is not cleared before the rfi instruction is performed, the frz signal is not negated. therefore, nested exception tracing can be supported by the software monitor debugger without affecting the value of the frz signal. only before the last rfi instruction does the software need to clear the icr. this process enables the software to accurately control frz assertion or negation. 20.6 programming the development port registers normally, the development port registers reside in the control register space and can be accessed using the mtspr and mfspr instructions. they also reside in the memory map i/o to be accessed by the ld and st instructions. the addresses of these registers are in table 6-9 of section 6 development capabilities and interface . 20.6.1 protecting the development port registers the development support registers are protected as shown in the following table. take note of the icr and dpdr registers special behavior. table 20-12. development support register protection operation msr pr debug mode enable in debug mode result read register 0 0 x a read is performed and when reading icr, it is also cleared. 0 1 0 a read is performed and when reading icr, it is not cleared. 0 1 1 a read is performed and when reading icr, it is also cleared. 1 x x a read is not performed, a program interrupt is generated, and when reading icr, it is not cleared. write register 0 0 x a write is performed, a write to icr is ignored, and a write to dpdr is ignored. 0 1 0 a write is ignored. 0 1 1 a write is performed and a write to icr is ignored. 1 x x a write is not performed, but a program interrupt is generated.
development capabilities and interface 20-42 mpc823e reference manual motorola development 20 capabilities & interface 20.6.2 development port registers 20.6.2.1 comparator aCd value registers. the comparator a-d value (cmpa-d) registers contain the address to be compared to the instruction address for generating an instruction watchpoint. these registers have an undefined reset value. icmpvinstruction comparison value this field represents the address bits to be compared to the instruction address. bits 30C31reserved these bits are reserved and must be set to 0. cmpa-d bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field icmpv reset x r/w r/w spr 144, 145, 146, 147 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field icmpv reserved reset x r/w r/w r/w spr 144, 145, 146, 147 note: x = dont care.
development capabilities and interface motorola mpc823e reference manual 20-43 development 20 capabilities & interface 20.6.2.2 comparator eCf value registers. the comparator e-f value (cmpe-f) registers contain the address to be compared to the load/store address for generating a load/store watchpoint. these registers have an undefined reset value. lcmpvload/store comparison value this field is the address bits to be compared to the load/store address. cmpe-f bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field lcmpv reset x r/w r/w spr 152, 153 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field lcmpv reset x r/w r/w spr 152, 153 note: x = dont care.
development capabilities and interface 20-44 mpc823e reference manual motorola development 20 capabilities & interface 20.6.2.3 comparator gCh value registers. the comparator g-h value (cmpg-h) registers contain the data to be compared to the translation data. these registers have an undefined reset value. dcmpvdata comparison value this field represents data to be compared to the translation data. 20.6.2.4 breakpoint address register. the breakpoint address (bar) register contains the address of the transaction or the instruction that causes the breakpoint. this register has an undefined reset value. barvbreakpoint address register value the field represents the value to be compared to the breakpoint. cmpg-h bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field dcmpv reset x r/w r/w spr 154, 155 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dcmpv reset x r/w r/w spr 154, 155 note: x = dont care. bar bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field barv reset x r/w r/w spr 159 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field barv reset x r/w r/w spr 159 note: x = dont care.
development capabilities and interface motorola mpc823e reference manual 20-45 development 20 capabilities & interface 20.6.2.5 instruction support control register. the instruction support control (ictrl) register controls instruction operation. ctacompare type of comparator a 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. ctbcompare type of comparator b 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. ctccompare type of comparator c 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. ctdcompare type of comparator d 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. ictrl bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cta ctb ctc ctd iw0 iw1 reset 00 0 000 r/w r/w r/w r/w r/w r/w r/w spr 158 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field iw2 iw3 siw0en siw1en siw2en siw3en diw0en diw1en diw2en diw3en ifm isct_ser reset 0 0 000000000 0 r/w r/w r/w r/wr/wr/wr/wrrrrr/w r/w spr 158
development capabilities and interface 20-46 mpc823e reference manual motorola development 20 capabilities & interface iw0instruction watchpoint 0 0x = not active (reset value). 10 = match from comparator a. 11 = match from comparators a & b. iw1instruction watchpoint 1 0x = not active (reset value). 10 = match from comparator a. 11 = match from comparators a | b. iw2instruction watchpoint 2 0x = not active (reset value). 10 = match from comparator c. 11 = match from comparators c & d. iw3instruction watchpoint 3 0x = not active (reset value). 10 = match from comparator c. 11 = match from comparators c | d. siw0ensoftware instruction watchpoint trap enable 0 0 = trap disabled (reset value). 1 = trap enabled. siw1ensoftware instruction watchpoint trap enable 1 0 = trap disabled (reset value). 1 = trap enabled. siw2ensoftware instruction watchpoint trap enable 2 0 = trap disabled (reset value). 1 = trap enabled. siw3ensoftware instruction watchpoint trap enable 3 0 = trap disabled (reset value). 1 = trap enabled. diw0endevelopment port instruction watchpoint trap enable 0 this is a read-only bit. 0 = trap disabled (reset value). 1 = trap enabled. diw1endevelopment port instruction watchpoint trap enable 1 this is a read-only bit. 0 = trap disabled (reset value). 1 = trap enabled.
development capabilities and interface motorola mpc823e reference manual 20-47 development 20 capabilities & interface diw2endevelopment port instruction watchpoint trap enable 2 this is a read-only bit. 0 = trap disabled (reset value). 1 = trap enabled. diw3endevelopment port instruction watchpoint trap enable 3 this is a read-only bit. 0 = trap disabled (reset value). 1 = trap enabled. ifmignore first match only for instruction breakpoints 0 = do not ignore first match. used for go to x (reset value). 1 = ignore first match. used for continue. isct_serinstruction fetch show cycle and core serialize control this field defines one of several performance versus visibility options for core behavior. 111 is the preferred encoding for normal operation. changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr instruction to ictrl. 000 = core is fully serialized and show cycle will be performed for all fetched instructions (reset value). has a reset value of 0x00000000. 001 = core is fully serialized and show cycle will be performed for all changes in the program flow. 010 = core is fully serialized and show cycle will be performed for all indirect changes in the program flow. 011 = core is fully serialized and no show cycles will be performed for fetched instructions. 100 = illegal. 101 = core is not serialized (normal mode) and show cycle will be performed for all changes in the program flow. if the fetch of the target of a direct branch is aborted by the core, the target is not always visible on the external pins. this does not affect program trace. 110 = core is not serialized (normal mode) and show cycle will be performed for all indirect changes in the program flow. 111 = core is not serialized (normal mode) and no show cycles will be performed for fetched instructions. for more information, see section 20.2.2 controlling instruction fetch show cycles .
development capabilities and interface 20-48 mpc823e reference manual motorola development 20 capabilities & interface 20.6.2.6 load/store support comparators control register. the load/store support comparators control (lctrl1) register controls the load/store breakpoint and watchpoint operation. ctecompare type, comparator e 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. ctfcompare type, comparator f 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. ctgcompare type, comparator g 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. lctrl1 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cte ctf ctg cth crwe crwf reset 00 0 000 r/w r/w r/w r/w r/w r/w r/w spr 156 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field csg csh susg sush cgbmsk chbmsk reserved reset 0000 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w spr 156
development capabilities and interface motorola mpc823e reference manual 20-49 development 20 capabilities & interface cthcompare type, comparator h 0xx = not active (reset value). 100 = equal to. 101 = less than. 110 = greater than. 111 = not equal to. crweselect match on read/write of comparator e 0x = dont care (reset value). 10 = match on read. 11 = match on write. crwfselect match on read/write of comparator f 0x = dont care (reset value). 10 = match on read. 11 = match on write. csgcompare size, comparator g 00 = reserved. 01 = word. 10 = half-word. 11 = byte. cshcompare size, comparator h 00 = reserved. 01 = word. 10 = half-word. 11 = byte. susgsigned/unsigned operating mode for comparator g 0 = signed. 1 = unsigned. sushsigned/unsigned operating mode for comparator h 0 = signed. 1 = unsigned. cgbmskbyte mask for comparator g 0000 = all bytes are not masked. 0001 = last byte of the word is masked. ? ? ? 1111 =all bytes are masked.
development capabilities and interface 20-50 mpc823e reference manual motorola development 20 capabilities & interface chbmskbyte mask for comparator h 0000 = all bytes are not masked. 0001 = last byte of the word is masked. ? ? ? 1111 = all bytes are masked. bits 30C31reserved these bits are reserved and must be set to 0. 20.6.2.7 load/store support and-or control register. the load/store support and-or control (lctrl2) register is used to control the bit masks for load/store data comparisons. watchpoint programming consists of three control register fields lwxia, lwxla, and lwxld. all three conditions must be detected to assert a watchpoint. the reset value of this register is 0x00000000. lw0enfirst load/store watchpoint enable 0 = watchpoint not enabled (reset value). 1 = watchpoint enabled. lw0iafirst load/store watchpoint i-address watchpoint selection 00 = first instruction watchpoint. 01 = second instruction watchpoint. 10 = third instruction watchpoint. 11 = fourth instruction watchpoint. lctrl2 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field lw0e n lw0ia lw0ia dc lw0la lw0l adc lw0ld lw0l ddc lw1e n lw1ia lw1ia dc lw1la reset 00000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spr 157 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field lw1l adc lw1ld lw1l ddc brkn omsk reserved dlw0 en dlw1 en slw0 en slw1 en reset 0000 0 0000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spr 157
development capabilities and interface motorola mpc823e reference manual 20-51 development 20 capabilities & interface lw0iadcfirst load/store watchpoint care/dont care i-address events 0 = dont care. 1 = care. lw0lafirst load/store watchpoint l-address events selection 00 = match from comparator e. 01 = match from comparator f. 10 = match from comparators e & f. 11 = match from comparators e | f. lw0ladcfirst load/store watchpoint care/dont care l-address events 0 = dont care. 1 = care. lw0ldfirst load/store watchpoint l-data events selection 00 = match from comparator g. 01 = match from comparator h. 10 = match from comparators g & h. 11 = match from comparators g | h. lw0lddcfirst load/store watchpoint care/dont care l-data events 0 = dont care. 1 = care. lw1ensecond load/store watchpoint enable 0 = watchpoint not enabled (reset value). 1 = watchpoint enabled. lw1iasecond load/store watchpoint i-address watchpoint selection 00 = first instruction watchpoint. 01 = second instruction watchpoint. 10 = third instruction watchpoint. 11 = fourth instruction watchpoint. lw1iadcsecond load/store watchpoint care/dont care i-address event 0 = dont care. 1 = care. lw1lasecond load/store watchpoint l-address events selection 00 = match from comparator e. 01 = match from comparator f. 10 = match from comparators e & f. 11 = match from comparators e | f. lw1ladcsecond load/store watchpoint care/dont care l-address events 0 = dont care. 1 = care.
development capabilities and interface 20-52 mpc823e reference manual motorola development 20 capabilities & interface lw1ldsecond load/store watchpoint l-data events selection 00 = match from comparator g. 01 = match from comparator h. 10 = match from comparators g & h. 11 = match from comparator g | h. lw1lddcsecond load/store watchpoint care/dont care l-data events 0 = dont care. 1 = care. brknomskinternal breakpoints nonmask bit controls both instruction breakpoints and load/store breakpoints 0 = masked mode, breakpoints are recognized only when msr ri =1 (reset value). 1 = nonmasked mode, breakpoints are always recognized. bits 21C27reserved these bits are reserved and must be set to 0. dlw0endevelopment port trap enable selection of the first load/store watchpoint (read-only bit) 0 = trap disabled (reset value). 1 = trap enabled. dlw1endevelopment port trap enable selection of the second load/store watchpoint (read-only bit) 0 = trap disabled (reset value). 1 = trap enabled. slw0ensoftware trap enable selection of the first load/store watchpoint 0 = trap disabled (reset value). 1 = trap enabled. slw1ensoftware trap enable selection of the second load/store watchpoint 0 = trap disabled (reset value). 1 = trap enabled.
development capabilities and interface motorola mpc823e reference manual 20-53 development 20 capabilities & interface 20.6.2.8 breakpoint counter a value and control register. the breakpoint counter a value and control (counta) register is used to count watchpoint events and to generate breakpoints a programmable amount of time after a watchpoint occurs. cntvcounter preset value this field contains the number of watchpoint events to be encountered before a breakpoint is generated. bits 16C29reserved these bits are reserved and must be set to 0. cntccounter source select 00 = not active (reset value). 01 = instruction first watchpoint. 10 = load/store first watchpoint. 11 = reserved. counta bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cntv reset r/w r/w spr 150 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved cntc reset 00 r/w r/w r/w spr 150 note: = undefined.
development capabilities and interface 20-54 mpc823e reference manual motorola development 20 capabilities & interface 20.6.2.9 breakpoint counter b value and control register. the breakpoint counter b value and control (countb) register is used to count watchpoint events and to generate breakpoints a programmable amount of time after a watchpoint occurs. cntvcounter preset value this field contains the number of watchpoint events to be encountered before a breakpoint is generated. bits 16C29reserved these bits are reserved and must be set to 0. cntccounter source select 00 = not active (reset value). 01 = instruction second watchpoint. 10 = load/store second watchpoint. 11 = reserved. countb bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cntv reset r/w r/w spr 151 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field reserved cntc reset r/w r/w r/w spr 151 note: = undefined.
development capabilities and interface motorola mpc823e reference manual 20-55 development 20 capabilities & interface 20.6.3 debug mode registers 20.6.3.1 interrupt cause register. the interrupt cause register (icr) provides the reason for entering debug mode. all bits are set by the hardware, cleared when the register is read, and cleared to zero when exiting reset. any attempt to write to this register is ignored. the reset value for this register is 0x00000000. bits 0, 4, and 5reserved these bits are reserved and must be set to 0. rstreset interrupt this bit is set when the system reset pin is asserted. this pin is not implemented in the core. chstpcheck stop this bit is set when the machine check interrupt is asserted and msr me =0. the core enters debug mode if enabled and the chstpe bit in the der is set. otherwise, the processor enters the check stop state. mcimachine check interrupt this bit is set when the machine check interrupt is asserted and msr me =1. the core enters debug mode if enabled and the mcie bit in the der is set. extiexternal interrupt this bit is set when the external interrupt is asserted. the core enters debug mode if enabled and the extie bit in the dir is set. alialignment interrupt this bit is set when the alignment interrupt is asserted. the core enters debug mode if enabled and the alie bit in the dir is set. icr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res rst chstp mci reserved exti ali pri fpuvi deci reserved sysi tr res reset 0 0 0 0 0 00000 0 0 00 r/w r r r r r rrrrr r r rr spr 148 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field res sei itlbms dtlbms itlber dtlber reserved lbrk ibrk ebrk dpi reset 000 0 0 0 0 0000 r/w rrr r r r r rrrr spr 148
development capabilities and interface 20-56 mpc823e reference manual motorola development 20 capabilities & interface priprogram interrupt this bit is set when the program interrupt is asserted.the core enters in debug mode if enabled and the prie bit in the der is set. fpuvifloating-point unavailable interrupt this bit is set when the floating-point unavailable interrupt is asserted. the core enters debug mode if enabled and the fpuvie bit in the der is set. decidecrementer interrupt this bit is set when the decrementer interrupt is asserted. the core enters debug mode if enabled and the decie bit in the der is set. bits 11C12, 15C16reserved these bits are reserved and must be set to 0. sysisystem call interrupt this bit is set when the system call interrupt is asserted. the core enters debug mode if enabled and the sysie bit in the der is set. trtrace interrupt this bit is set when in single-step mode or when in branch trace mode. the core enters debug mode if enabled and the tre bit in the der is set. seiimplementation dependent software emulation interrupt this bit is set when the floating-point assist interrupt is asserted. the core enters debug mode if enabled and the seie bit in the der is set. itlbmsimplementation specific instruction tlb miss this bit is set as a result of an instruction tlb miss.the core enters debug mode if enabled and the itlbmse bit in the der is set. dtlbmsimplementation specific data tlb miss this bit is set as a result of an data tlb miss. the core enters debug mode if enabled and the dtlbmse bit in the der is set. itlberimplementation specific instruction tlb error this bit is set as a result of an instruction tlb error. the core enters debug mode if enabled and the itlbere bit in the der is set. dtlberimplementation specific data tlb error this bit is set as a result of an data tlb error. the core enters debug mode if enabled and the dtlbere bit in the der is set. bits 22C27reserved these bits are reserved and must be set to 0.
development capabilities and interface motorola mpc823e reference manual 20-57 development 20 capabilities & interface lbrkload/store breakpoint interrupt this bit is set as a result of the assertion of an load/store breakpoint. the core enters debug mode if enabled and the lbrke bit in the der is set. ibrkinstruction breakpoint interrupt this bit is set as a result of the assertion of an instruction breakpoint. the core enters debug mode if enabled and the ibrke bit in the der is set. ebrkexternal breakpoint interrupt this bit is set as a result of the assertion of an external breakpoint. the core enters debug mode if enabled and the ebrke bit in the der is set. dpidevelopment port interrupt this bit is set by the development port as a result of a debug station nonmaskable request or when entering debug mode immediately out of reset. the core enters debug mode if enabled and the dpie bit in the der is set. 20.6.3.2 debug enable register. the debug enable register (der) allows the enabling of events that cause the processor to enter debug mode. bits 0, 4, and 5reserved these bits are reserved and must be set to 0. rstereset interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. der bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field res rste chstp e mcie reserved extie alie prie fpuvi e decie reserved sysie tre res reset 0010 0 00000 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spr 149 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field res seie itlbms e dtlbm se itlbere dtlber e reserved lbrke ibrke ebrke dpie reset 0000 0 0 0 1111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spr 149
development capabilities and interface 20-58 mpc823e reference manual motorola development 20 capabilities & interface chstpecheck stop enable 0 = debug mode entry is disabled. 1 = debug mode entry is enabled (reset value). mciemachine check interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. extieexternal interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. aliealignment interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. prieprogram interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. fpuviefloating-point unavailable interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. deciedecrementer interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. bits 11C12 and 15C16reserved these bits are reserved and must be set to 0. sysiesystem call interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. tretrace interrupt enable 0 = debug mode entry is disabled. 1 = debug mode entry is enabled (reset value). seiesoftware emulation interrupt enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. itlbmseimplementation specific instruction tlb miss enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled.
development capabilities and interface motorola mpc823e reference manual 20-59 development 20 capabilities & interface itlbereimplementation specific instruction tlb error enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. dtlbmseimplementation specific data tlb miss enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. dtlbereimplementation specific data tlb error enable 0 = debug mode entry is disabled (reset value). 1 = debug mode entry is enabled. bits 22C27reserved these bits are reserved and must be set to 0. lbrkeload/store breakpoint interrupt enable 0 = debug mode entry is disabled. 1 = debug mode entry is enabled (reset value). ibrkeinstruction breakpoint interrupt enable 0 = debug mode entry is disabled. 1 = debug mode entry is enabled (reset value). ebrkeexternal breakpoint interrupt enable 0 = debug mode entry is disabled. 1 = debug mode entry is enabled (reset value). dpiedevelopment port nonmaskable request enable 0 = debug mode entry is disabled. 1 = debug mode entry is enabled (reset value).
development capabilities and interface 20-60 mpc823e reference manual motorola development 20 capabilities & interface 20.6.4 development port data register the special-purpose development port data register (dpdr) physically resides in the development port logic. it is used for data interchange between the core and development system. an access to this register is initiated using the mtspr and mfspr instructions and it is implemented using a special bus cycle on the internal bus. for details, see table 6-9. dpdvdevelopment port data value this field contains the data to be transferred between the core and the development system. dpivdevelopment port instruction value this field is used to fetch an instruction supplied by the development system. dpdr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field dpdv reset r/w r/w spr 630 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dpdv reset r/w r/w spr 630 note: = undefined. dpir bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field dpiv reset r/w r spr 631 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dpiv reset r/w r spr 631 note: = undefined.
motorola mpc823e reference manual 21-1 ieee 1149.1 test 21 access port section 21 ieee 1149.1 test access port the mpc823e provides a dedicated user-accessible test access port (tap) that is fully compatible with the ieee 1149.1 standard test access port and boundary scan architecture . problems associated with testing high-density circuit boards have led tothe development of this proposed standard under the sponsorship of the test technology committee of ieee and the joint test action group (jtag). the mpc823e implementation supports circuit board test strategies based on this standard. the tap consists of five dedicated signal pins, a 16-state tap controller, and two test data registers. a boundary scan register links all the device signal pins into a single shift register. the test logic, which is implemented using static logic design, is independent of the device system logic. the mpc823e implementation provides the capability to: ? perform boundary scan operations to check circuit board electrical continuity. ? bypass the mpc823e for a given circuit board test by effectively reducing the boundary scan register to a single cell. ? sample the mpc823e system pins during operation and transparently shift out the result in the boundary scan register. ? disable the output drive to pins during circuit board testing. note: certain precautions must be observed to ensure that the ieee 1149.1-like test logic does not interfere with nontest operation.
ieee 1149.1 test access port 21-2 mpc823e reference manual motorola ieee 1149.1 test 21 access port the mpc823e implementation includes a tap controller, a 4-bit instruction register, and two test registers (a 1-bit bypass register and a 397-bit boundary scan register). an overview of the mpc823e scan chain implementation is illustrated in the figure below. the tap controller consists of the following signals: ? tcka test clock input to synchronize the test logic. ? tmsa test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of tck to sequence the tap controllers state machine. ? tdia test data input (with an internal pull-up resistor) that is sampled on the rising edge of tck. ? tdoa three-stateable test data output that is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. ? trst an asynchronous reset with an internal pull-up resistor that provides tap controller initialization and other logic required by the standard. for normal operation of the mpc823e, this signal pin must make a level transition to low before initialization begins. typically, if the tap is used, connect the trst signal to the poreset through a diode (cathode to poreset ). figure 21-1. test logic block diagram boundary scan register bypass m u x instruction apply & decode register 4-bit instruction register m u x tdo tdi tms tck trst 0 1 2 tap controller 3
ieee 1149.1 test access port motorola mpc823e reference manual 21-3 ieee 1149.1 test 21 access port 21.1 the tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. the value shown adjacent to each bubble in the figure below represents the value of the tms signal sampled on the rising edge of the tck signal. figure 21-2. tap controller state machine test logic reset runtest/idle selectdr_scan capturedr shiftdr exit1dr pausedr exit2dr updatedr selectir_scan captureir shiftir exit1ir pauseir exit2ir updateir 00 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1
ieee 1149.1 test access port 21-4 mpc823e reference manual motorola ieee 1149.1 test 21 access port 21.2 the boundary scan register the mpc823e scan chain implementation has a 397-bit boundary scan register that contains bits for all device signal, clock pins, and associated control signals. however, the xtal, extal, and xfc pins are associated with analog signals and are not included in the boundary scan register. an ieee-1149.1-compliant boundary scan register has been included on the mpc823e. this 397-bit boundary scan register can be connected between the tdi and tdo signals when the extest or sample / preload instructions are selected. it is used for capturing signal pin data on the input pins, forcing fixed values on the output signal pins, and selecting the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins. figure 21-3 through figure 21-6 depict the various cell types. figure 21-3. output pin cell (o.pin) 1 1 mux g1 1 1 mux g1 c d c d from last cell clock dr update dr shift dr 1 extest | clamp data from to output buffer 0 otherwise logic system to next cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-5 ieee 1149.1 test 21 access port figure 21-4. observe-only input pin cell (i.obs) figure 21-5. output control cell (io.ctl) 1 1 mux g1 c d data to system logic input pin s to next cell 1 1 mux g1 1 1 mux g1 c d c d from last cell clock dr update dr shift dr 1 extest | clamp to outpu t buffer 0 otherwise to next cell o utput control logic from system
ieee 1149.1 test access port 21-6 mpc823e reference manual motorola ieee 1149.1 test 21 access port the value of the control bit controls the output function of the bidirectional pin. one or more bidirectional data cells can be serially connected to a control cell. bidirectional pins include two scan cell for data (io.cell) as illustrated in figure 21-6 and these bits are controlled by the cell illustrated in figure 21-5. it is important to know the boundary scan bit order and the pins that are associated with them. the bit order starting with the tdo output and ending with the tdi input is shown in table 21-1. the first column of the table defines the bits ordinal position in the boundary scan register. the shift register cell nearest tdo (first to be shifted in) is defined as bit 0 and the last bit to be shifted in is bit 396. the second column references one of the three mpc823e cell types depicted in figure 21-3 through figure 21-6 that describe the cell structure for each type. the third column lists the pin name for all pin-related cells and defines the name of the bidirectional control register bits. the fourth column lists the pin type and the last column indicates the associated boundary scan register control bit for the bidirectional output pins. figure 21-6. general arrangement of bidirectional pin cells i/o pin from last cell output data input data output enable i.obs en from system logic o.pin i/o.ctl to next pin pair to next cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-7 ieee 1149.1 test 21 access port table 21-1. boundary scan bit definition bit cell type pin/cell name pin type output ctl cell 1 i.obs pb[26] io 2 o.pin pb[26] io g56.ctl 3 io.ctl g56.ctl 4 i.obs pc[12] io 5 o.pin pc[12] io g34.ctl 6 io.ctl g34.ctl 7 i.obs pa[12] io 8 o.pin pa[12] io g74.ctl 9 io.ctl g74.ctl 10 i.obs pb[27] io 11 o.pin pb[27] io g57.ctl 12 io.ctl g57.ctl 13 i.obs pc[13] io 14 o.pin pc[13] io g35.ctl 15 io.ctl g35.ctl 16 i.obs pa[13] io 17 o.pin pa[13] io g75.ctl 18 io.ctl g75.ctl 19 i.obs pb[28] io 20 o.pin pb[28] io g58.ctl 21 io.ctl g58.ctl 22 i.obs pc[14] io 23 o.pin pc[14] io g36.ctl 24 io.ctl g36.ctl 25 i.obs pa[14] io 26 o.pin pa[14] io g76.ctl 27 io.ctl g76.ctl 28 i.obs pb[29] io 29 o.pin pb[29] io g59.ctl 30 io.ctl g59.ctl 31 i.obs pc[15] io 32 o.pin pc[15] io g37.ctl
ieee 1149.1 test access port 21-8 mpc823e reference manual motorola ieee 1149.1 test 21 access port 33 io.ctl g37.ctl 34 i.obs pb[30] io 35 o.pin pb[30] io g60.ctl 36 io.ctl g60.ctl 37 i.obs pa[15] io 38 o.pin pa[15] io g77.ctl 39 io.ctl g77.ctl 40 i.obs pb[31] io 41 o.pin pb[31] io g61.ctl 42 io.ctl g61.ctl 43 i.obs a[6] io 44 o.pin a[6] io g203.ctl 45 io.ctl g203.ctl 46 i.obs a[7] io 47 o.pin a[7] io g203.ctl 48 i.obs a[8] io 49 o.pin a[8] io g202.ctl 50 io.ctl g202.ctl 51 i.obs a[9] io 52 o.pin a[9] io g202.ctl 53 i.obs a[10] io 54 o.pin a[10] io g202.ctl 55 i.obs a[11] io 56 o.pin a[11] io g202.ctl 57 i.obs a[12] io 58 o.pin a[12] io g202.ctl 59 i.obs a[13] io 60 o.pin a[13] io g202.ctl 61 i.obs a[14] io 62 o.pin a[14] io g202.ctl 63 i.obs a[15] io 64 o.pin a[15] io g202.ctl 65 i.obs a[16] io 66 o.pin a[16] io g201.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-9 ieee 1149.1 test 21 access port 67 io.ctl g201.ctl 68 i.obs a[17] io 69 o.pin a[17] io g201.ctl 70 i.obs a[19] io 71 o.pin a[19] io g201.ctl 72 i.obs a[27] io 73 o.pin a[27] io g201.ctl 74 i.obs a[20] io 75 o.pin a[20] io g201.ctl 76 i.obs a[21] io 77 o.pin a[21] io g201.ctl 78 i.obs a[24] io 79 o.pin a[24] io g201.ctl 80 i.obs a[23] io 81 o.pin a[23] io g201.ctl 82 i.obs a[29] io 83 o.pin a[29] io g200.ctl 84 io.ctl g200.ctl 85 i.obs a[25] io 86 o.pin a[25] io g200.ctl 87 i.obs a[30] io 88 o.pin a[30] io g200.ctl 89 i.obs a[18] io 90 o.pin a[18] io g200.ctl 91 i.obs a[28] io 92 o.pin a[28] io g200.ctl 93 i.obs a[22] io 94 o.pin a[22] io g200.ctl 95 i.obs a[26] io 96 o.pin a[26] io g200.ctl 97 i.obs a[31] io 98 o.pin a[31] io g200.ctl 99 i.obs tsiz0_reg_b io 100 o.pin tsiz0_reg_b io g204.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port 21-10 mpc823e reference manual motorola ieee 1149.1 test 21 access port 101 i.obs tsiz1 io 102 o.pin tsiz1 io g204.ctl 103 io.ctl g204.ctl 104 o.pin we3_b_bsab3_b_pcweb o 105 o.pin we1_b_bsab1_b_iowr_b o 106 o.pin we2_b_bsab2_b_pcoe_b o 107 o.pin we0_b_bsab0_b_iord_b o 108 o.pin gpla0_b_gplb0_b o 109 o.pin oe_b_gplab1_b o 110 o.pin gplab2_b_cs2_b o 111 o.pin gplab3_b_cs3_b o 112 o.pin cs4_b o 113 o.pin cs5_b o 114 o.pin cs6_b_ce1b_b o 115 o.pin cs7_b_ce2b_b o 116 o.pin cs3_b o 117 o.pin cs2_b o 118 o.pin cs1_b o 119 o.pin cs0_b o 120 i.obs wr_b io 121 o.pin wr_b io g96.ctl 122 io.ctl g96.ctl 123 i.obs gplb4_b_upwaitb io 124 o.pin gplb4_b_upwaitb io g24.ctl 125 io.ctl g24.ctl 126 o.pin gpla5_b o 127 i.obs gpla4_b_upwaita io 128 o.pin gpla4_b_upwaita io g25.ctl 129 io.ctl g25.ctl 130 o.pin bdip_b_gplb5_b o 131 i.obs bi_b io 132 o.pin bi_b io g23.ctl 133 io.ctl g23.ctl 134 i.obs ta_b io table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-11 ieee 1149.1 test 21 access port 135 o.pin ta_b io g22.ctl 136 io.ctl g22.ctl 137 i.obs tea_b io 138 o.pin tea_b io g89.ctl 139 io.ctl g89.ctl 140 i.obs ts_b io 141 o.pin ts_b io g97.ctl 142 io.ctl g97.ctl 143 i.obs br_b io 144 o.pin br_b io g21.ctl 145 io.ctl g21.ctl 146 i.obs bg_b io 147 o.pin bg_b io g20.ctl 148 io.ctl g20.ctl 149 i.obs bb_b io 150 o.pin bb_b io g11.ctl 151 io.ctl g11.ctl 152 i.obs frz_irq6_b io 153 o.pin frz_irq6_b io g90.ctl 154 io.ctl g90.ctl 155 i.obs burst_b io 156 o.pin burst_b io g205.ctl 157 io.ctl g205.ctl 158 i.obs rsv_b_irq2_b io 159 o.pin rsv_b_irq2_b io g17.ctl 160 io.ctl g17.ctl 161 i.obs ipb5_lwp1_vf1 io 162 o.pin ipb5_lwp1_vf1 io g15.ctl 163 io.ctl g15.ctl 164 i.obs ipb4_lwp0_vf0 io 165 o.pin ipb4_lwp0_vf0 io g150.ctl 166 io.ctl g150.ctl 167 i.obs ipb3_iwp2_vf2 io 168 o.pin ipb3_iwp2_vf2 io g151.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port 21-12 mpc823e reference manual motorola ieee 1149.1 test 21 access port 169 io.ctl g151.ctl 170 i.obs ipb1_iwp1_vfls1 io 171 o.pin ipb1_iwp1_vfls1 io g150.ctl 172 i.obs ipb0_iwp0_vfls0 io 173 o.pin ipb0_iwp0_vfls0 io g150.ctl 174 i.obs ipb7_ptr_at3 io 175 o.pin ipb7_ptr_at3 io g13.ctl 176 io.ctl g13.ctl 177 i.obs ipb2_iois16b_b_at2 io 178 o.pin ipb2_iois16b_b_at2 io g41.ctl 179 io.ctl g41.ctl 180 i.obs aleb_dsck_at1 io 181 o.pin aleb_dsck_at1 io g16.ctl 182 io.ctl g16.ctl 183 i.obs ipb6_dsdi_at0 io 184 o.pin ipb6_dsdi_at0 io g14.ctl 185 io.ctl g14.ctl 186 i.obs kr_b_irq4_b_spkrout io 187 o.pin kr_b_irq4_b_spkrout io g95.ctl 188 io.ctl g95.ctl 189 i.obs op2_modck1_sts_b io 190 o.pin op2_modck1_sts_b io g92.ctl 191 io.ctl g92.ctl 192 i.obs op3_modck2_dsdo io 193 o.pin op3_modck2_dsdo io g91.ctl 194 io.ctl g91.ctl 195 i.obs clk4in i 196 o.pin texp o 197 i.obs hreset_b io 198 o.pin hreset_b io g94.ctl 199 io.ctl g94.ctl 200 i.obs sreset_b io 201 o.pin sreset_b io g93.ctl 202 io.ctl g93.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-13 ieee 1149.1 test 21 access port 203 i.obs rstconf_b i 204 i.obs poreset_b i 205 i.obs waitb_b i 206 o.pin clkout o 207 i.obs dp0_irq3_b io 208 o.pin dp0_irq3_b io g18.ctl 209 i.obs dp3_irq6_b io 210 o.pin dp3_irq6_b io g18.ctl 211 io.ctl g18.ctl 212 i.obs dp2_irq5_b io 213 o.pin dp2_irq5_b io g18.ctl 214 i.obs dp1_irq4_b io 215 o.pin dp1_irq4_b io g18.ctl 216 i.obs d[31] io 217 o.pin d[31] io g103.ctl 218 io.ctl g103.ctl 219 i.obs d[30] io 220 o.pin d[30] io g103.ctl 221 i.obs d[29] io 222 o.pin d[29] io g103.ctl 223 i.obs d[7] io 224 o.pin d[7] io g103.ctl 225 i.obs d[28] io 226 o.pin d[28] io g103.ctl 227 i.obs d[26] io 228 o.pin d[26] io g103.ctl 229 i.obs d[25] io 230 o.pin d[25] io g103.ctl 231 i.obs d[24] io 232 o.pin d[24] io g103.ctl 233 i.obs d[21] io 234 o.pin d[21] io g102.ctl 235 io.ctl g102.ctl 236 i.obs d[22] io table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port 21-14 mpc823e reference manual motorola ieee 1149.1 test 21 access port 237 o.pin d[22] io g102.ctl 238 i.obs d[6] io 239 o.pin d[6] io g102.ctl 240 i.obs d[20] io 241 o.pin d[20] io g102.ctl 242 i.obs d[19] io 243 o.pin d[19] io g102.ctl 244 i.obs d[18] io 245 o.pin d[18] io g102.ctl 246 i.obs d[15] io 247 o.pin d[15] io g102.ctl 248 i.obs d[16] io 249 o.pin d[16] io g102.ctl 250 i.obs d[5] io 251 o.pin d[5] io g101.ctl 252 io.ctl g101.ctl 253 i.obs d[3] io 254 o.pin d[3] io g101.ctl 255 i.obs d[14] io 256 o.pin d[14] io g101.ctl 257 i.obs d[2] io 258 o.pin d[2] io g101.ctl 259 i.obs d[11] io 260 o.pin d[11] io g101.ctl 261 i.obs d[10] io 262 o.pin d[10] io g101.ctl 263 i.obs d[9] io 264 o.pin d[9] io g101.ctl 265 i.obs d[17] io 266 o.pin d[17] io g101.ctl 267 i.obs d[27] io 268 o.pin d[27] io g100.ctl 269 io.ctl g100.ctl 270 i.obs d[23] io table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-15 ieee 1149.1 test 21 access port 271 o.pin d[23] io g100.ctl 272 i.obs d[1] io 273 o.pin d[1] io g100.ctl 274 i.obs d[4] io 275 o.pin d[4] io g100.ctl 276 i.obs d[0] io 277 o.pin d[0] io g100.ctl 278 i.obs d[12] io 279 o.pin d[12] io g100.ctl 280 i.obs d[8] io 281 o.pin d[8] io g100.ctl 282 i.obs d[13] io 283 o.pin d[13] io g100.ctl 284 i.obs irq0_b i 285 i.obs irq1_b i 286 i.obs irq7_b i 287 i.obs spare3 io 288 o.pin spare3 io g10.ctl 289 io.ctl g10.ctl 290 i.obs pd[3] io 291 o.pin pd[3] io g9.ctl 292 io.ctl g9.ctl 293 i.obs pd[5] io 294 o.pin pd[5] io g8.ctl 295 io.ctl g8.ctl 296 i.obs pd[6] io 297 o.pin pd[6] io g7.ctl 298 io.ctl g7.ctl 299 i.obs pd[4] io 300 o.pin pd[4] io g6.ctl 301 io.ctl g6.ctl 302 i.obs pd[7] io 303 o.pin pd[7] io g5.ctl 304 io.ctl g5.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port 21-16 mpc823e reference manual motorola ieee 1149.1 test 21 access port 305 i.obs pd[8] io 306 o.pin pd[8] io g4.ctl 307 io.ctl g4.ctl 308 i.obs pd[9] io 309 o.pin pd[9] io g3.ctl 310 io.ctl g3.ctl 311 i.obs pd[10] io 312 o.pin pd[10] io g2.ctl 313 io.ctl g2.ctl 314 i.obs pd[11] io 315 o.pin pd[11] io g1.ctl 316 io.ctl g1.ctl 317 i.obs pd[12] io 318 o.pin pd[12] io g81.ctl 319 io.ctl g81.ctl 320 i.obs pd[13] io 321 o.pin pd[13] io g80.ctl 322 io.ctl g80.ctl 323 i.obs pd[14] io 324 o.pin pd[14] io g79.ctl 325 io.ctl g79.ctl 326 i.obs pd[15] io 327 o.pin pd[15] io g78.ctl 328 io.ctl g78.ctl 329 i.obs pc[4] io 330 o.pin pc[4] io g26.ctl 331 io.ctl g26.ctl 332 i.obs pc[5] io 333 o.pin pc[5] io g27.ctl 334 io.ctl g27.ctl 335 i.obs pb[16] io 336 o.pin pb[16] io g40.ctl 337 io.ctl g40.ctl 338 i.obs pc[6] io table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-17 ieee 1149.1 test 21 access port 339 o.pin pc[6] io g28.ctl 340 io.ctl g28.ctl 341 i.obs pb[17] io 342 o.pin pb[17] io g47.ctl 343 io.ctl g47.ctl 344 i.obs pc[7] io 345 o.pin pc[7] io g29.ctl 346 io.ctl g29.ctl 347 i.obs pa[4] io 348 o.pin pa[4] io g66.ctl 349 io.ctl g66.ctl 350 i.obs pb[18] io 351 o.pin pb[18] io g48.ctl 352 io.ctl g48.ctl 353 i.obs pa[5] io 354 o.pin pa[5] io g67.ctl 355 io.ctl g67.ctl 356 i.obs pb[19] io 357 o.pin pb[19] io g49.ctl 358 io.ctl g49.ctl 359 i.obs pa[6] io 360 o.pin pa[6] io g68.ctl 361 io.ctl g68.ctl 362 i.obs pc[8] io 363 o.pin pc[8] io g30.ctl 364 io.ctl g30.ctl 365 i.obs pa[7] io 366 o.pin pa[7] io g69.ctl 367 io.ctl g69.ctl 368 i.obs pc[9] io 369 o.pin pc[9] io g31.ctl 370 io.ctl g31.ctl 371 i.obs pa[8] io 372 o.pin pa[8] io g70.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port 21-18 mpc823e reference manual motorola ieee 1149.1 test 21 access port 373 io.ctl g70.ctl 374 i.obs pb[22] io 375 o.pin pb[22] io g52.ctl 376 io.ctl g52.ctl 377 i.obs pc[10] io 378 o.pin pc[10] io g32.ctl 379 io.ctl g32.ctl 380 i.obs pa[9] io 381 o.pin pa[9] io g71.ctl 382 io.ctl g71.ctl 383 i.obs pb[23] io 384 o.pin pb[23] io g53.ctl 385 io.ctl g53.ctl 386 i.obs pc[11] io 387 o.pin pc[11] io g33.ctl 388 io.ctl g33.ctl 389 i.obs pb[24] io 390 o.pin pb[24] io g54.ctl 391 io.ctl g54.ctl 392 i.obs pb[25] io 393 o.pin pb[25] io g55.ctl 394 io.ctl g55.ctl 395 i.obs spare2 io 396 o.pin spare2 io g88.ctl 397 io.ctl g88.ctl table 21-1. boundary scan bit definition (continued) bit cell type pin/cell name pin type output ctl cell
ieee 1149.1 test access port motorola mpc823e reference manual 21-19 ieee 1149.1 test 21 access port 21.3 the instruction register the mpc823e jtag implementation includes the public instructions extest , sample / preload , bypass , and clamp . one additional public instruction hi-z is capable of disabling all device output drivers. the mpc823e includes a 4-bit instruction register that consists of a shift register with four parallel outputs. data is transferred from the shift register to the parallel outputs during the update-ir controller state. the four bits are used to decode the five unique instructions listed in table 21-2. the parallel output of the instruction register is reset to all ones in the test-logic-reset controller state. notice that this preset state is equivalent to the bypass instruction. during the capture-ir controller state, the parallel inputs to the instruction shift register are loaded with the clamp command code. 21.3.1 the external test instruction the external test ( extest ) instruction selects the 397-bit boundary scan register and asserts an internal reset for the mpc823e system logic to force a known beginning internal state while performing external boundary scan operations. by using the tap controller, the register is capable of scanning user-defined values into the output buffers, capturing values presented to the input pins, and controlling the output drive of three-stateable output or bidirectional pins. for more details on the function and use of extest , refer to the ieee 1149.1 standard. table 21-2. instruction decoding code instruction b3 b2 b1 b0 0000 extest 0001 sample/preload 0x1x bypass 0100 hi-z 101 clamp and bypass note: b0 (lsb) is shifted first.
ieee 1149.1 test access port 21-20 mpc823e reference manual motorola ieee 1149.1 test 21 access port 21.3.2 the sample/preload instruction the sample / preload instruction initializes the boundary scan register output cells before extest is selected. this initialization ensures that known data will appear on the outputs when entering the extest instruction. the sample / preload instruction also provides an opportunity to obtain a snapshot of system data and control signals. 21.3.3 the bypass instruction the bypass instruction creates a shift register path from tdi to the bypass register and, finally, to the tdo pins, thus circumventing the 397-bit boundary scan register. this instruction is used to enhance test efficiency when a component other than the mpc823e is the device being tested. it selects the single-bit bypass register as illustrated in figure 21-7. when the bypass register is selected by the current instruction, the shift register stage is set to a logic zero on the rising edge of the tck pin in the capture-dr controller state. therefore, the first bit to be shifted out after selecting the bypass register is always a logic zero. 21.3.4 the clamp instruction the clamp instruction selects the single-bit bypass register as illustrated in figure 21-7 above, and the state of all signals driven from the system output pins is completely defined by the data previously shifted into the boundary scan register. 21.3.5 the hi-z instruction the hi-z instruction is provided as a manufacturers optional public instruction/on to avoid back driving the output pins during circuit board testing. when hi-z is invoked all output drivers, including the two-state drivers, are turned off (high impedance). the instruction selects the bypass register. note: since there is no internal synchronization between the tck and clkout, you must provide some form of external synchronization between the jtag operation tck frequency and system operation clkout frequency to achieve meaningful results. figure 21-7. bypass register 1 1 mux g1 c d to tdo from tdi 0 shift dr clock dr
ieee 1149.1 test access port motorola mpc823e reference manual 21-21 ieee 1149.1 test 21 access port 21.4 mpc823e restrictions the control afforded by the output enable signals using the boundary scan register and the extest instruction requires a compatible circuit board test environment to avoid device-destructive configurations. you must avoid situations in which the mpc823e output drivers are enabled into actively driven networks. the mpc823e features a low-power stop mode. the interaction of the scan chain interface with low-power stop mode is as follows: 1. the tap controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. leaving the tap controller in the test-logic-reset state negates its ability to achieve low power, but does not otherwise affect device functionality. 2. the tck input is not disabled in low-power stop mode. to consume minimal power, the tck input must be externally connected to v cc or ground while in low-power or normal mode (nonscan chain). 3. the tms, tdi, and trst pins include on-chip pull-up resistors. in low-power stop mode, the tms and tdi pins must remain either unconnected or connected to v cc to achieve minimal power consumption. for proper reset of the scan chain test logic, the best approach is to pull active trst at power-on reset. the easiest way to do this and reset the scan chain logic is to connect trst to poreset through a diode (cathode to poreset). in power-down mode, you must ensure that the xreset line is low during power-down so that you can conserve power. if the tap controller is not used, you must ground the trst signal. if, for some reason, the hreset signal that you connected to trst is high during power-down, the kapwr supply will propagate through the trst pin to undesired internal circuits and will increase power consumption. ] note: we recommend that you connect trst to ground (if you don't use jtag) or to poreset through a diode. the problem with the connection to hreset is that if at power up the jtag logic blocks the poreset signal from propagating into the chip (since the logic is not initialized yet), this will prevent hreset from asserting, which leaves the jtag logic (and the whole device) uninitialized.
motorola mpc823e reference manual 22-1 electrical 22 characteristics section 22 dc electrical characteristics this section contains basic information about power considerations, thermal characteristics, layout practices, and dc timing specifications for the mpc823e. 22.1 maximum ratings (gnd = 0v) note: so that we may provide you with the most current information, the mpc823e ac electrical characteristics (part number mpc823eele/d) can be accessed from our website at www.motorola.com . if you do not have internet access, please contact your local motorola sales office for a printed copy. rating symbol value unit supply voltage vddh -0.3 to 4.0 v vdd -0.3 to 4.0 v kapwr -0.3 to 4.0 v vddsyn -0.3 to 4.0 v input voltage (jtag and gpio) vin -0.3 to 5.8 v input voltage (all other pins) vin -0.3 to 3.3 v operating temperature t a 0 to 70? or -40? to 85? ?c storage temperature range t stg -55 to +150 ?c 1. functional operating conditions are given in section 22.4 dc electrical characteristics (vcc = 3.0 - 3.6 v) . absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : the jtag and gpio input voltages cannot be more than 2.5 v greater than supply voltage, this restriction applies also on power-on as well as on normal operation. 3. 5 volt friendly inputs are inputs that tolerate 5 volts for jtag and gpio pins.
dc electrical characteristics 22-2 mpc823e reference manual motorola electrical 22 characteristics this device contains circuitry protecting against damage from high-static voltage or electrical fields. however, it is advised that precautions be taken to avoid application of any voltages higher than the maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either gnd or v cc ). 22.2 thermal characteristics 22.3 power considerations the average chip-junction temperature , t j , in c can be obtained from t j = t a + (p d ? q ja ) (1) where t a = ambient temperature , c q ja = package thermal resistance , junction to ambient , c/w p d =p int + p i/o p int =i dd x v dd , wattschip internal power p i/o = power dissipation on input and output pinsuser determined for most applications p i/o < 0.3 ? p int and can be neglected. if p i/o is neglected , an approximate relationship between p d and t j is: p d =k ? (t j + 273 c) (2) solving equations (1) and (2) for k gives k = p d ? (t a + 273 c) + q ja ? p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . characteristic symbol value unit thermal resistance for bga q ja ~30 c/w
dc electrical characteristics motorola mpc823e reference manual 22-3 electrical 22 characteristics 22.3.1 layout practices each v cc pin on the mpc823e must be provided with a low-impedance path to the boards supply. each gnd pin must be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply must be bypassed to ground using at least four 0.1 m f bypass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and gnd must be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the mpc823e have fast rise and fall times. printed circuit (pc) trace interconnection length must be reduced to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations must consider all device loads, as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. try to minimize the noise levels on the pll supply pins.
dc electrical characteristics 22-4 mpc823e reference manual motorola electrical 22 characteristics 22.4 dc electrical characteristics (v cc = 3.0 - 3.6 v) characteristic symbol min max unit input high voltage (for jtag and gpio) v ih 2.0 5.5 v input high voltage (all other pins) v ih 2.0 3.6 v input low voltage v il gnd 0.8 v extal and extclk input high voltage v ihc 0.7*(v cc )v cc +0.3 v input leakage current, v in = 5.5 v i in 10 a hi-z (off state) leakage current, v in = 3.5v i oz 10 a signal low input current, v il = 0.8 v i l 10 a signal high input current, v ih = 2.0 v i h 10 a output high voltage, i oh = C2.0 ma , v ddh = 3.0v except xtal, xfc, and open-drain pins v oh 2.4 v output low voltage iol = 2.0 ma clkout iol = 3.2 maa[6:31], tsiz0/reg , tsiz1, d(0:31), dp[0:3]/irq [3:6], rd/wr , burst , rsv /irq2 , ip_b[0:1]/iwp[0:1]/vfls[0:1], ip_b2/ iois16_b /at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/ vf1, ip_b6/dsdi/at0, ip_b7/ptr /at3, usbrxd/pa15, rxd2/ pa13, smrxd2/l1txda/pa9, smtxd2/l1rxda/pa8, irq4 /kr / spkrout, tin1/l1rclka/brgo1/clk1/pa7, tin3/l1rclkb/ tout1 /clk2/pa6, tin2/l1tclka/brgo2/clk3/pa5, tin4/ l1tclkb/tout2 /clk4/pa4, lcd_a/spisel /pb31, spiclk/ txd3/pb30, spimosi/rxd3/pb29, brgo3/spimiso/pb28, brgo1/i2csda/pb27, brgo2/i2cscl/pb26, smtxd1/txd3/ pb25, smrxd1/l1rxdb/rxd3/pb24, smsyn1 /sdack1 / l1tsyncb/cts3 /pb23, smsyn2 /sdack2 /l1rsyncb/pb22, lcd_b/l1st1/pb19, l1st2/rts2 /pb18, lcd_c/l1st3/pb17, l1st4/l1rqa/pb16, l1st5/l1txdb/dreq1 /pc15, l1st6/rts2 / dreq2 /pc14, l1st7/rts3 /pc13, l1st8/l1rqa/pc12, usbrxp/ pc11, usbrxn/tgate1 /pc10, cts2 /pc9, tgate1 /cd2 /pc8, usbtxp/pc7, usbtxn/pc6, sdack1 /l1tsynca/pc5, l1rsynca/cd3 /pc4, ld8/vd7/pd15, ld7/vd6/pd14, ld6/vd5/ pd13, ld5/vd4/pd12, ld4/vd3/pd11, ld3/vd2/pd10, ld2/vd1/ pd9, ld1/vd0/pd8, frame/vsync/pd5, lcd_ac/loe/blank/ pd6, ld0/field/pd7, load/hsync/pd4, shift/clk/pd3 v ol 0.5 v iol = 5.3 mabdip /gpl_b 5 , br , bg , frz/irq6 , cs [0:5], cs 6 / ce 1_b , cs 7 /ce 2_b , we0 /bs_ab0 /iord , we1 /bs_ab1 /iowr , we2 /bs_ab2 /pcoe , we3 /bs_ab3 /pcwe , gpl_a 0 /gpl_b 0 , oe / gpl_a 1 /gpl_b 1 , gpl_a [2:3]/gpl_b [2:3]/cs [2:3], upwaita/ gpl_a 4 /as , upwaitb/gpl_b 4 , gpl_a 5 , ale_b/dsck/at1, op2/modck1/sts , op3/modck2/dsdo iol = 7.0 ma usboe /pa14, txd2/pa12 iol = 8.9 mats , ta , tea , bi , bb , hreset , sreset note: input pin voltage specifications are v cc = +4 v or 5.8 v, whichever is less. ac timings are based on a 50 p | load.
motorola mpc823e reference manual 23-1 mechanical data and 23 ordering information section 23 mechanical data and ordering information 23.1 ordering information contact your local motorola sales office for the latest information on speed grades and part numbers. package type frequency temperature order number 256 lead pbga 23x23 1.27mm pitch 66 mhz 75 mhz 0 c to 95 c* 0 c to 95 c* xpc823ezt66b2 xpc823ezt75b2 256 lead pbga 23x23 1.27mm pitch 66 mhz -40 c to 95 c** xpc823eczt66b2 * ta = 0 c to tj = +95 c ** ta = -40 c to tj = +95 c
mechanical data and ordering information 23-2 mpc823e reference manual motorola mechanical data and 23 ordering information 23.2 pin assignmentspbgatop view pc14 pb28 pb27 pc12 tck pb24 pb23 pa8 pa7 vddl pa5 pc7 pc4 pd14 pd10 pd8 pc15 pa14 pa13 pa12 tms pb26 pa15 pb30 pb29 pc13 trst n/c pc10 pa6 pb18 pc5 pd13 pd9 pd4 pd5 a8 a7 pb31 tdo tdi pc11 pb22 pc9 pb25 pa9 pc8 a11 a9 a12 pb19 pa4 pb16 pd15 pd12 pd7 pd6 pb17 pc6 pd11 pd3 irq7 irq1 irq0 t r p n m a15 a14 a13 a27 a19 a16 vddl a20 a21 a29 a23 a25 a28 a30 a22 a31 tsiz0 a26 we1 tsiz1 we0 we2 gpla3 gpla1 gpla2 cs6 d8 d0 d4 d1 d9 d11 d2 d3 k j h l d16 d5 d19 vddl d21 d6 d29 d7 d30 clkout dp3 n/c gnd g f vddh e d cs4 cs7 cs2 xfc vddsyn bi n/c cs3 cs1 bdip burst ipb4 aleb irq4 modck2 hreset sreset poreset vsssyn1 vsssyn br bb irq6 ipb3 ipb0 vddl extclk extal xtal kapwr c b a ta 16 15 14 13 12 11 10 9 876 54321 a6 a10 a17 a24 a18 we3 gpla0 cs5 wr gplb4 cs0 ts irq2 ipb7 ipb2 modck1 texp dp1 dp2 gpla4 tea bg ipb5 ipb1 ipb6 rstconf waitb dp0 gpla5 d12 d13 d23 d27 d17 d10 d15 d14 d22 d18 d25 d20 d28 d24 d26 d31 n/c n/c n/c n/c n/c n/c
mechanical data and ordering information motorola mpc823e reference manual 23-3 mechanical data and 23 ordering information 23.3 pbga package dimensions the following figure is a 23x23mm package, which has 1.27mm spacing between pads. the device designator for the mpc823e in this package is zt. for more information on the printed circuit board layout of the plastic ball grid array (pbga) package, including thermal via design and suggested pad layout, please refer to an-1231/d, plastic ball grid array application note available from your local motorola sales office. case 1130-01 issue a a b c d e f g h j k l m n p r t 256x bottom view e 0.20 7 6 5 4 3 2 b 0.15 c d d2 e2 a b 0.30 c ab side view dim min max millimeters a 1.91 2.35 a1 0.50 0.70 a2 1.12 1.22 a3 0.29 0.43 b 0.60 0.90 d 23.00 bsc d1 19.05 ref d2 e 23.00 bsc e1 19.05 ref e2 19.00 20.00 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and the seating plane are defined by the spherical crowns of the solder balls. 4x 8 9 10 11 12 13 14 15 16 m m top view (d1) 15x e 15x e (e1) 4x e /2 0.20 c 0.35 c a3 256x c a a1 a2 seating plane e 1.27 bsc 19.00 20.00 1
motorola mpc823e reference manual 24-1 terminology 24 section 24 terminology acronyms, mnemonics, and units of measure smicrosecond apgaccess protection group asidaddress space id bdbuffer descriptor brgbaud rate generator ccittinternational telegraph and telephone consultative committee c/icommand/indication cpmcommunication processor module crccyclic redundancy check disfcdiscarded frame counter ebiexternal bus interface fcsframe check sequence fdfunction descriptor ggigabyte gcigeneral circuit interface gpcmgeneral-purpose chip-select machine hdlchigh-level data link control i 2 cinter-integrated circuit idginterdialog gap idlinterchip digital link idmaindependent direct memory access idnintegrated digital network ifginterframe gap immrinternal memory map register irdainfra-red irlapinfra-red link access protocol jtagjoint test action group kapwrkeep-alive power kkilobyte kbdkilobaud kbpskilobytes per second kbpskilobits per second
terminology 24-2 mpc823e reference manual motorola terminology 24 khzkilohertz lap-blink access protocol-balanced lap-dlink access protocol-d channel lruleast recently used mmegabyte macmultiply accumulate mbmegabit mbpsmegabits per second mfmultiplication factor mhzmegahertz mipsmillions of instructions per second mmumemory management unit nminonmaskable interrupt nmsinonmaskable serial interrupt ntscnational television standards committee oscmmain crystal oscillator osiopen systems interconnection palphase alternation line pbgaplastic ball grid array pciperipheral component interconnect pcmpulse-code modulation pllphase-locked loop porpower-on reset ppppoint-to-point protocol pwmpulse-width modulation rmsroot mean squared rxreceive or reception sccserial communication controller sdmaserial direct memory access sdnsoftware defined network smcserial management controller spiserial peripheral interface ss7signaling system number 7 taptest access port tdmtime-division multiplex tftthin film transistor tlbtranslation lookaside buffer tsatime-slot assigner txtransmit or transmission uartuniversal asynchronous receiver/transmitter upmuser-programmable machine usbuniversal serial bus
terminology motorola mpc823e reference manual 24-3 terminology 24 terminology atomic cycle if multiple bus transactions by a bus master occur in a sequence where the master retains ownership of the bus during the duration of the sequence, thus preventing other master(s) from transferring in the middle of the sequence, the sequence is considered atomic. autobaud the process of determining a serial data rate by timing the width of a single bit. big-endian big-endian ordering assigns the lowest address to the highest order (leftmost) eight bits of the scalar. this called big-endian because the big end of the scalar, considered a binary number, comes first in memory. breakpoint an event that forces the machine to branch into a breakpoint exception routine. burst a bus transfer that has more than one piece of data associated with it. burst length the number of data associated with a burst cycle. for example, a burst length of four has four data pieces (four beats) associated with it. copyback updates to external memory are delayed until forced by the user program or a transfer of bus control to an external master. at the time of forced update or relinquishment of the bus, all changes to the cache are written to external memory. until that time, cache and external memory are not coherent. critical-data first this feature allows the data transferred during the burst cycle to be organized where the word or data needed first is the first one to transfer within the burst-data block. the order of transferring can be sequential and usually wraps back to the word (or data) zero. for example, 1 ? 2 ? 3 ? 0 for a sequence of four data with data 1 as the critical data. critical-word first the word that the processor wants first. datastream a sequence of information to be processed by the core.
terminology 24-4 mpc823e reference manual motorola terminology 24 exception an error, unusual condition, or external signal that can set a status bit. it may or may not cause an interrupt, depending on whether or not the corresponding interrupt is enabled. execution serialization instruction issue is halted until all instructions that are currently in progress complete execution, all internal pipeline stages and instruction buffers have emptied, and all outstanding memory transactions have completed. execution stream the combination of instructions and data on which the core operates. fetch serialization instruction fetch is halted until all instructions currently in the processor have completed execution, including the prefetched instructions waiting to be issued. the machine after fetch serialization is said to be completely synchronized. half-word a half-word consists of 2 bytes or 16 bits. internal bus the bus connecting the core and system interface unit. interrupt the act of changing the machine state register and other parts of the machine state in response to an exception. latency the interval from the time an instruction begins execution until it produces a result that is available for use by a subsequent instruction. little-endian little-endian byte ordering assigns the lowest address to the lowest-order (rightmost) eight bits of the scalar. the little end of the scalar, considered a binary number, comes first in memory. master a device on the bus that requests bus ownership and initiates the bus cycles. memory controller a functional logic section of the mpc823e. its primary function is to provide the controls for the external bus memories and i/o devices.
terminology motorola mpc823e reference manual 24-5 terminology 24 no operation (nop) an instruction whose sole function is to increment the program counter, but which affects no changes to any registers or memory. scoreboard a register tracking system that ensures that values are not pulled from a register before they are updated by a previous instruction. sequential instruction any instruction that is not a flow control instruction and not isync. slave a device that responds to the masters address. a slave receives data on a write cycle and gives data to the master on a read cycle. snoop the act of monitoring external bus activity by alternate bus masters. by snooping these external accesses, a core can identify accesses to memory locations that contain dirty data and possibly halt activity to supply correct data. swap four byte lanes, reversing (lane 0 to lane 3, lane 1 to lane 2, lane 2 to lane 1 and lane 3 to lane 0). tablewalk an index value is used to identify an entry point in a tree structure that is traversed until a pointer is found. the system walks through a table of pointers to its end. transaction a bus transaction consists of an address transfer (address phase) and data transfers (data phase). time-division multiplex (tdm) any serial channel that is divided into channels separated by time. watchpoint an event that is reported, but does not change the timing of the machine. word a word consists of 4 bytes or 32 bits. writethrough continuous updates, as they occur, of external memory so that cache and memory maintain coherency at all times.
motorola mpc823e reference manual a-1 serial communication a performance appendix a serial communication performance operating at 25mhz, the mpc823e is designed to support unrestricted operation of the high-level data link control (hdlc) or transparent protocol running on the serial communication controllers at 2.048mbps. the mpc823e can also support one ethernet channel at 10mbps and one hdlc or transparent channel at 1mbps. the physical clocking limit of the serial communication controllers is higher than the sustained serial bit rate. this limit is given as a 1:2.25 ratio between the sync clock, which is a clock generated in the clock synthesizer that can be as fast as the 25mhz system clock and the serial clock. for example, with a sync clock of 25mhz, the serial communication controllers can be clocked at 11.1mhz. this clocking scheme allows the serial communication controllers to handle high-speed bursts of data bits for short periods of time subject to the fifo sizes. when the serial communication controllers are connected to a time-division multiplexed channel using the time-slot assigner on the mpc823e, a serial communication controllers physical clocking limit is a 1:2.5 ratio between the sync clock and serial clock. therefore, the serial communication controllers can be connected to a 10.0mhz time-division multiplexed channel with a 25mhz mpc823e. this clocking scheme allows it to handle high-speed bursts of data bits for short periods of time subject to the fifo sizes. other devices that offer a higher hdlc performance than the mpc823e are the motorola mc68605 1984 ccitt x.25 lapb controller and mc68606 ccitt q.921 multilink lapd controller. the mc68605 and mc68606 perform the full data-link layer protocol and support various transparent modes within hdlc-framed operation at a minimum 10mbps. the performance figures listed in table a-1 are for a 25mhz system clock. notice that, in general, performance scales linearly with the frequency, so that a combination of protocols over the mpc823es performance limitation at 25mhz can occur at 50mhz.
serial communication performance a-2 mpc823e reference manual motorola serial communication a performance a.1 channel combinations when operating the multiple hdlc/transparent channel protocol, most of the processing load falls on the communication processor module. protocols other than the multiple hdlc and transparent protocol rely on the hardware support built into the serial channels. combining the serial communication controllers and the microcontroller allows you to attain throughput rates of up to 8mbps in hdlc and transparent mode. the multiple channel protocol does not rely on the serial communication controllers and operates transparently when you perform serial-to-parallel conversion and vice versa. all bit manipulation is performed in the microcontroller software or hardware, which causes the communication processor module to have a heavier load when operating in multiple channel mode. the heavier load occurs even if all time-slots are concatenated to one logical channel. the following equation and table a-1 can be used as a guide for calculating the communication processor modules load. the cpm load estimation is not truly linear, so there is a gray area near the maximum limit (defined as 1). to determine the exact load, you must test your operations on target hardware. the cpm load (l) is approximated by the following equation: where: di is the user-targeted data rate for the particular cpm controller or protocol. pi is the cpm performance factor for the particular cpm controller or protocol. see table a-1 for specific values. f is the actual cpm system frequency in megahertz. since the equation and table estimates the feasibility of an application used only by the cpm, it is your responsibility to verify the application against other issues (pin multiplexing, parameter ram, or microcode availability). the motorola website ( www.motorola.com ) contains a spreadsheet that performs the calculation of the cpm load. l s i = d i p i ----- 25 f ------ 1 <
serial communication performance motorola mpc823e reference manual a-3 serial communication a performance table a-1. mpc823e performance table controller/protocol cpm performance factor scc ethernet (half-duplex) 22,000 kbps ethernet (full-duplex) 11,000 kbps hdlc (full-duplex) 8,000 kbps transparent (full-duplex) 8,000 kbps uart (full-duplex) 2,400 kbd async hdlc (full-duplex) 3,000 kbps irda high-speed 1 16,000 kbps irda medium-speed 2 16,000 kbps irda low-speed 3 6,000 kbps spi (half-duplex) spi byte 500 kbps spi word 4 3,125 kbps smc transparent (full-duplex) 1,500 kbps uart (half-duplex) 440 kbd uart (full-duplex) 220 kbd idma 5 memory->peripheral (dual-address mode) 5 1,600 kbps peripheral->memory (dual-address mode) 5 2,200 kbps memory->memory 6 5,700 kbps memory->memory (burst) 6 10,400 kbps memory->peripheral (single-address mode) 6 5,000 kbps peripheral->memory (single-address mode) 6 5,000 kbps i 2 c (half-duplex) i 2 c 2,080 kbps usb usb high-speed 24,000 kbps usb low-speed 24,000 kbps 1. same as transparent half-duplex. 2. same as hdlc half-duplex. 3. same as asynchronous hdlc half-duplex. 4. the spi controller is in word mode if the data character is greater than 8 bits in length. 5. the cpm performance factor assumes a 32-bit peripheral port size. the cpm performance for 16- and 8-bit port sizes would be one-quarter and one-half of those listed. 6. the cpm performance factor is independent of port size. the cpm performance factor is identical for 8-, 16-, and 32-bit port sizes. however, if the bus cycle is slow enough (more than 13 clocks), performance will be degraded.
serial communication performance a-4 mpc823e reference manual motorola serial communication a performance a.2 example #1 if the mpc823e is operating at 25mhz with one ethernet line in half-duplex at 10mbps, one 38.4kbd smc uart, one 57.6kbd smc uart, and one usb at 1.5 mbps, then the following equation applies. any calculation such as this, which is close to one, is considered to be in a gray area and must be tested with hardware before it is implemented. a.3 example #2 if a block of 512k is transferred by idma in single address mode from memory to a peripheral, one async hdlc at 1mbps, and one smc uart at 38.4kbd, then the following equation applies when the mpc823e is running at 25mhz. a.4 example #3 for one half-duplex ethernet channel at 10mbps and one smc uart at 115.2kbd with the mpc823e running at 40mhz, the following equation applies. note: with idma, this process calculates peak communication processor module usage, not the sustained rate. by nature, idma transfers occur in random intervals and are not consistent bit rates when compared to the serial channel operation. 10 22 ------ 38.4 220 ----------- 57.6 220 ----------- 1.5 24 ------- - 0.953 = ++++ 512 5000 ------------ - 1000 3000 ------------ - 38.4 220 ----------- 0.69 = +++ 10 22 ------ 115.2 220 -------------- - + 25 40 ------ 0.611 =
motorola mpc823e reference manual b-1 instruction set b appendix b mpc823e instruction set this section lists the mpc823e instruction set in alphabetical order by mnemonic. each entry includes the instruction formats and a quick reference legend that provides information, such as the level(s) of the powerpc ? architecture in which the instruction can be found, user- or supervisor-level (an instruction is user-level unless the legend specifies otherwise), and the instruction formats. the format diagrams show all valid combinations of the instruction fields. the architecture specification refers to user- and supervisor-level as problem state and privileged state, respectively. b.1 instruction formats instructions are four bytes long and word-aligned, so when instruction addresses are presented to the processor (as in branch instructions) the two low-order bits are ignored. similarly, when the processor develops an instruction address, its two low-order bits are zero. bits 0C5 always specify the primary opcode and many instructions also have an extended opcode. the remaining bits of the instruction contains one or more fields for the different instruction formats. some instruction fields are reserved or must contain a predefined value as shown in the individual instruction layouts. if a reserved field does not have all bits cleared, or if a field that must contain a particular value does not contain that value, the instruction form is invalid. b.2 split-field notation some instruction fields occupy more than one contiguous sequence of bits or a contiguous sequence of bits used in permuted order. these fields are called split fields. the lowercase split fields represent the concatenation of the sequences from left to right. for instance, spr and tbr are shown in the following table. split fields that represent the concatenation of the sequences in some order, which need not be left to right are shown in uppercase letters. for instance, mb, me, and sh are shown in the following table. field description spr (11C20) this field is used to specify a special-purpose register for the mtspr and mfspr instructions. tbr (11C20) this field is used to specify either the time base lower (tbl) or time base upper (tbu).
mpc823e instruction set b-2 mpc823e reference manual motorola instruction set b b.3 instruction fields the table below shows the instruction fields used in the various instruction formats. field description aa (30) absolute address bit. 0 the immediate field represents an address relative to the current instruction address (cia). the effective (logical) address of the branch is either the sum of the li field sign-extended to 32 bits and the address of the branch instruction or the sum of the bd field sign-extended to 32 bits and the address of the branch instruction. 1 the immediate field represents an absolute address. the effective address (ea) of the branch is the li field sign-extended to 32 bits or the bd field sign-extended to 32 bits. the li and ld fields are sign-extended to 32. bd (16C29) immediate field specifying a 14-bit signed two's complement branch displacement that is concatenated on the right with 0b00 and sign-extended to 32 bits. bi (11C15) this field is used to specify a bit in the cr to be used as the condition of a branch conditional instruction. bo (6C10) this field is used to specify options for the branch conditional instructions. crb a (11C15) this field is used to specify a bit in the cr to be used as a source. crb b (16C20) this field is used to specify a bit in the cr to be used as a source. crm (12C19) this field mask is used to identify the cr fields that are to be updated by the mtcrf instruction. d (16C31) immediate field specifying a 16-bit signed two's complement integer that is sign-extended to 32 bits. fr c (21C25) not used by mpc823e. fr d (6C10) not used by mpc823e. fr s (6C10) not used by mpc823e. imm (16C19) not used by mpc823e. li (6C29) immediate field specifying a 24-bit signed two's complement integer that is concatenated on the right with 0b00 and sign-extended to 32 bits. lk (31) link bit. 0 does not update the link register (lr). 1 updates the lr. if the instruction is a branch instruction, the address of the instruction following the branch instruction is placed into the lr. mb (21C25) and me (26C30) these fields are used in rotate instructions to specify a 32 bit mask. nb (16C20) this field is used to specify the number of bytes to move in an immediate string load or store. oe (21) this field is used for extended arithmetic to enable setting ov and so in the xer. opcd (0C5) primary opcode field r a (11C15) this field is used to specify a gpr to be used as a source or destination. r b (16C20) this field is used to specify a gpr to be used as a source. rc (31) record bit. 0 does not update the condition register (cr). 1 updates the cr to reflect the result of the operation. for integer instructions, cr bits 0C2 are set to reflect the result as a signed quantity and cr bit 3 receives a copy of the summary overflow bit, xer[so]. the result as an unsigned quantity or a bit string can be deduced from the eq bit. exceptions are referred to as interrupts in the architecture specification.) r d (6C10) this field is used to specify a gpr to be used as a destination. r s (6C10) this field is used to specify a gpr to be used as a source.
mpc823e instruction set motorola mpc823e reference manual b-3 instruction set b b.4 notations and conventions the operation of some instructions is described by a semiformal language or pseudocode. the table below contains a list of pseudocode notations and conventions used throughout this appendix. sh (16C20) this field is used to specify a shift amount. simm (16C31) this immediate field is used to specify a 16-bit signed integer. sr (12C15) this field is used to specify one of the 16 segment registers. to (6C10) this field is used to specify the conditions on which to trap. uimm (16C31) this immediate field is used to specify a 16-bit unsigned integer. xo (21C30, 22C30, 26C30) extended opcode field. notation/ convention definition ? assignment ? iea assignment of an instruction effective address. ? not logical operator * multiplication ? division (yielding quotient) + twos-complement addition C twos-complement subtraction, unary minus =, 1 equals and not equals relations <, , >, 3 signed comparison relations . (period) update. when used as a character of an instruction mnemonic, a period (.) means that the instruction updates the condition register field. c carry. when used as a character of an instruction mnemonic, a c indicates a carry out in xer[ca]. e extended precision. when used as the last character of an instruction mnemonic, an e indicates the use of xer[ca] as an operand in the instruction and records a carry out in xer[ca]. o overflow. when used as a character of an instruction mnemonic, an o indicates the record of an overflow in xer[ov] and cr0[so] for integer instructions. u unsigned comparison relations ? unordered comparison relation &, | and, or logical operators || used to describe the concatenation of two values (that is, 010 || 111 is the same as 010111) ? , o exclusive-or, equivalence logical operators (for example, (a b) = (a ? ? b)) field description
mpc823e instruction set b-4 mpc823e reference manual motorola instruction set b 0b nnnn a number expressed in binary format. 0x nnnn a number expressed in hexadecimal format. ( n )x the replication of x, n times (that is, x concatenated to itself n C 1 times). (n)0 and (n)1 are special cases. a description of the special cases follows: ? (n)0 means a field of n bits with each bit equal to 0. thus (5)0 is equivalent to 0b00000. ? (n)1 means a field of n bits with each bit equal to 1. thus (5)1 is equivalent to 0b11111. ( r a|0) the contents of ra if the ra field has the value 1C31, or the value 0 if the ra field is 0. ( r x) the contents of rx x[ n ] n is a bit or field within x, where x is a register x n x is raised to the nth power abs(x) absolute value of x ceil(x) least integer 3 x characterization reference to the setting of status bits in a standard way that is explained in the text. cia current instruction address. the 32-bit address of the instruction being described by a sequence of pseudocode. used by relative branches to set the next instruction address (nia) and by branch instructions with lk = 1 to set the link register. does not correspond to any architected register. clear clear the leftmost or rightmost n bits of a register to 0. this operation is used for rotate and shift instructions. clear left and shift left clear the leftmost b bits of a register, then shift the register left by n bits. this operation can be used to scale a known non-negative array index by the width of an element. these operations are used for rotate and shift instructions. cleared bits are set to 0. do do loop. ? indenting shows range. ? to and/or by clauses specify incrementing an iteration variable. ? while clauses give termination conditions. extract select a field of n bits starting at bit position b in the source register, right or left justify this field in the target register, and clear all other bits of the target register to zero. this operation is used for rotate and shift instructions. exts(x) result of extending x on the left with sign bits gpr(x) general-purpose register x if...then...else... conditional execution, indenting shows range, else is optional. insert select a field of n bits in the source register, insert this field starting at bit position b of the target register, and leave other bits of the target register unchanged. (no simplified mnemonic is provided for insertion of a field when operating on double words; such an insertion requires more than one instruction.) this operation is used for rotate and shift instructions. (note that simplified mnemonics are referred to as extended mnemonics in the architecture specification.) leave leave innermost do loop, or the do loop described in leave statement. mask(x, y) mask having ones in positions x through y (wrapping if x > y) and zeros elsewhere. mem(x, y) contents of y bytes of memory starting at address x. notation/ convention definition
mpc823e instruction set motorola mpc823e reference manual b-5 instruction set b the table below describes instruction field notation conventions used in this appendix. nia next instruction address, which is the 32-bit address of the next instruction to be executed (the branch destination) after a successful branch. in pseudocode, a successful branch is indicated by assigning a value to nia. for instructions which do not branch, the next instruction address is cia + 4. does not correspond to any architected register. oea powerpc operating environment architecture rotate rotate the contents of a register right or left n bits without masking. this operation is used for rotate and shift instructions. set bits are set to 1. shift shift the contents of a register right or left n bits, clearing vacated bits (logical shift). this operation is used for rotate and shift instructions. spr(x) special-purpose register x trap invoke the system trap handler. undefined an undefined value. the value may vary from one implementation to another, and from one execution to another on the same implementation. uisa powerpc user instruction set architecture vea powerpc virtual environment architecture the architecture specification equivalent ba, bb, bt crb a, crb b, crb d (respectively) dd ds ds fxm crm ra, rb, rt, rs r a, r b, r d, r s (respectively) si simm u imm ui uimm /, //, /// 0...0 (shaded) notation/ convention definition
mpc823e instruction set b-6 mpc823e reference manual motorola instruction set b precedence rules for pseudocode operators are summarized in the following table. operators in the top part of the table above are applied before those in the lower part. operators at the same level in the table associate from left to right, from right to left, or not at all. for example, C (unary minus) associates from left to right, so a C b C c = (a C b) C c. parentheses are used to override the evaluation order implied by the table above, or to increase clarity and parenthesized expressions are evaluated before serving as operands. b.5 the mpc823e instruction set the remainder of this section lists and describes the mpc823e instruction set. the instructions are listed in alphabetical order by their mnemonic. operators associativity x[ n ], function evaluation left to right ( n )x or replication, x( n ) or exponentiation right to left unary C, ? right to left * , ? left to right +, C left to right || left to right =, 1 , <, , >, 3 , u, ? left to right &, ? , o left to right | left to right C (range) none ?, ? iea none note: the execution unit that executes the instruction may not be the same for all powerpc processors.
mpc823e instruction setadd motorola mpc823e reference manual b-7 instruction set b add assembler syntax add r d, r a, r b (oe = 0 rc = 0) add. r d, r a, r b (oe = 0 rc = 1) addo r d, r a, r b (oe = 1 rc = 0) addo. r d, r a, r b (oe = 1 rc = 1) operation rd " (ra) + (rb) description the sum ( r a) + ( r b) is placed into r d. the add instruction is preferred for addition because it sets few status bits. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b oe 266 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setaddc b-8 mpc823e reference manual motorola instruction set b addc assembler syntax addc r d, r a, r b (oe = 0 rc = 0) addc. r d, r a, r b (oe = 0 rc = 1) addco r d, r a, r b (oe = 1 rc = 0) addco. r d, r a, r b (oe = 1 rc = 1) definition add carrying operation rd " (ra) + (rb) description the sum ( r a) + ( r b) is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) if the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field boe 10 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setadde motorola mpc823e reference manual b-9 instruction set b adde assembler syntax adde r d ,r a ,r b (oe = 0 rc = 0) adde.r d ,r a ,r b (oe = 0 rc = 1) addeor d ,r a ,r b (oe = 1 rc = 0) addeo. r d ,r a ,r b (oe = 1 rc = 1) definition add extended operation rd " (ra) + (rb) + xer[ca] description the sum ( r a) + ( r b) + xer[ca] is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b oe 138 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setaddi b-10 mpc823e reference manual motorola instruction set b addi assembler syntax addi rd,ra,simm) definition add immediate operation if ra = 0 then rd " exts(simm) else rd " ra + exts(simm) description the sum ( r a|0) + simm is placed into r d. the addi instruction is preferred for addition because it sets few status bits. note that addi uses the value 0, not the contents of gpr0, if r a = 0. other registers altered: o none simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 14 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm li r d , value equivalent to addi r d ,0, value la r d , disp( r a) equivalent to addi r d ,r a , disp subi r d ,r a , value equivalent to addi r d ,r a , Cvalue powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setaddic motorola mpc823e reference manual b-11 instruction set b addic assembler syntax addic r d, r a,simm) definition add immediate carrying operation rd " (ra) + exts(simm) description the sum ( r a) + simm is placed into r d. other registers altered: o xer: affected: ca simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 12 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm subic r d ,r a , value equivalent to addic r d ,r a , Cvalue powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setaddic. b-12 mpc823e reference manual motorola instruction set b addic. assembler syntax addic. rd,ra,simm) definition add immediate carrying and record operation rd " (ra) + exts(simm) description the sum ( r a) + simm is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 13 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm subic. r d ,r a , value equivalent to addic. r d ,r a , Cvalue powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setaddis motorola mpc823e reference manual b-13 instruction set b addis assembler syntax addis rd,ra,simm) definition add immediate shifted operation if ra = 0 then rd " exts(simm || (16)0) else rd " (ra) + exts(simm || (16)0) description the sum ( r a|0) + (simm || 0x0000) is placed into r d. the addis instruction is preferred for addition because it sets few status bits. note that addis uses the value 0, not the contents of gpr0, if r a = 0. other registers altered: o none simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 15 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm lis r d , value equivalent to addis r d ,0, value subis r d ,r a , value equivalent to addis r d ,r a , Cvalue powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setaddme b-14 mpc823e reference manual motorola instruction set b addme assembler syntax addme rd,ra (oe = 0 rc = 0) addme. rd,ra (oe = 0 rc = 1) addmeo rd,ra (oe = 1 rc = 0) addmeo. rd,ra (oe = 1 rc = 1) definition add to minus one extended operation rd " (ra) + xer[ca] C 1 description the sum ( r a) + xer[ca] + 0xffff_ffff_ffff_ffff is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 oe 234 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setaddze motorola mpc823e reference manual b-15 instruction set b addze assembler syntax addze rd,ra (oe = 0 rc = 0) addze. rd,ra (oe = 0 rc = 1) addzeo rd,ra (oe = 1 rc = 0) addzeo. rd,ra (oe = 1 rc = 1) definition add to zero extended operation rd " (ra) + xer[ca] description the sum ( r a) + xer[ca] is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 oe 202 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setand b-16 mpc823e reference manual motorola instruction set b and asembler syntax and ra,rs,rb (rc = 0) and. ra,rs,rb (rc = 1) definition and operation r a ? ( r s) & ( r b) description the contents of r s are anded with the contents of r b and the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b28rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setandc motorola mpc823e reference manual b-17 instruction set b andc assembler syntax andc ra,rs,rb (rc = 0) andc. ra,rs,rb (rc = 1) definition and with complement operation r a ? ( r s) + ? ( r b) description the contents of r s are anded with the ones complement of the contents of r b and the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b60rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setandi. b-18 mpc823e reference manual motorola instruction set b andi. assembler syntax andi. ra,rs,uimm definition and immediate operation r a ? ( r s) & ((16)0 || uimm) description the contents of r s are anded with 0x0000 || uimm and the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 28 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setandis. motorola mpc823e reference manual b-19 instruction set b andis. assembler syntax andis. ra,rs,uimm definition and immediate shifted operation r a ? ( r s) + (uimm || (16)0) description the contents of r s are anded with uimm || 0x0000 and the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 29 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setb b-20 mpc823e reference manual motorola instruction set b b assembler syntax b target_addr (aa = 0 lk = 0) ba target_addr (aa = 1 lk = 0) bl target_addr (aa = 0 lk = 1) bla target_addr (aa = 1 lk = 1) definition branch operation if aa then nia ? iea exts(li || 0b00) else nia ? iea cia + exts(li || 0b00) if lk then lr ? iea cia + 4 description target_addr specifies the branch target address. if aa = 0, then the branch target address is the sum of li || 0b00 sign-extended and the address of this instruction. if aa = 1, then the branch target address is the value li || 0b00 sign-extended. if lk = 1, then the effective address of the instruction following the branch instruction is placed into the link register. other registers altered: affected: link register (lr) (if lk = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 18 li bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field li aa lk powerpc architecture level supervisor level optional form uisa i
mpc823e instruction setbc motorola mpc823e reference manual b-21 instruction set b bc assembler syntax bc bo,bi,target_addr (aa = 0 lk = 0) bca bo,bi,target_addr (aa = 1 lk = 0) bcl bo,bi,target_addr (aa = 0 lk = 1) bcla bo,bi,target_addr (aa = 1 lk = 1) definition branch conditional operation m ? 32 if ? bo[2] then ctr ? ctr C 1 ctr_ok ? bo[2] | (bo[3]) cond_ok ? bo[0] | (cr[bi] o bo[1]) if ctr_ok & cond_ok then if aa then nia ? iea exts(bd || 0b00) else nia ? iea cia + exts(bd || 0b00) if lk then lr ? iea cia + 4 description the bi field specifies the bit in the condition register (cr) to be used as the condition of the branch. the bo field is encoded as described in the table below. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 16 bo bi bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field bd aa lk bo description 0000 y decrement the count register (ctr), then branch if the condition is false. 0001 y decrement the ctr, then branch if the condition is false. 001 zy branch if the condition is false. 0100 y decrement the ctr, then branch if the condition is true. 0101 y decrement the ctr, then branch if the condition is true. 011 zy branch if the condition is true. 1 z 00 y decrement the ctr, then branch if the decremented ctr 1 0 . 1 z 01 y decrement the ctr, then branch if the decremented ctr = 0 . 1 z 1 zz branch always. note: in this table, z indicates a bit that is ignored. the z bits must be cleared. the y bit has a hint about whether a conditional branch is likely to be taken.
mpc823e instruction setbc b-22 mpc823e reference manual motorola instruction set b target_addr specifies the branch target address. if aa = 0, the branch target address is the sum of bd || 0b00 sign-extended and the address of this instruction. if aa = 1, the branch target address is the value bd || 0b00 sign-extended. if lk = 1, the effective address of the instruction following the branch instruction is placed into the link register. other registers altered: affected: count register (ctr) (if bo[2] = 0) affected: link register (lr) (if lk = 1) simplified mnemonics: blt target equivalent to bc 12,0, target bne cr2 ,target equivalent to bc 4,10, target bdnz target equivalent to bc 16,0, target powerpc architecture level supervisor level optional form uisa b
mpc823e instruction setbcctr motorola mpc823e reference manual b-23 instruction set b bcctr assembler syntax bcctr bo,bi (lk = 0) bcctrl bo,bi (lk = 1) definition branch conditional to count register operation cond_ok ? bo[0] | (cr[bi] o bo[1]) if cond_ok then nia ? iea ctr || 0b00 if lk then lr ? iea cia + 4 description the bi field specifies the bit in the condition register to be used as the condition of the branch. the bo field is encoded as described in the table below. the branch target address is ctr || 0b00. if lk = 1, the effective address of the instruction following the branch instruction is placed into the link register. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 bo bi bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 528 lk bo description 0000 y decrement the count register (ctr), then branch if the condition is false. 0001 y decrement the ctr, then branch if the condition is false. 001 zy branch if the condition is false. 0100 y decrement the ctr, then branch if the condition is true. 0101 y decrement the ctr, then branch if the condition is true. 011 zy branch if the condition is true. 1 z 00 y decrement the ctr, then branch if the decremented ctr 1 0 . 1 z 01 y decrement the ctr, then branch if the decremented ctr = 0 . 1 z 1 zz branch always. note: in this table, z indicates a bit that is ignored. the z bits must be cleared. the y bit has a hint about whether a conditional branch is likely to be taken.
mpc823e instruction setbcctr b-24 mpc823e reference manual motorola instruction set b if the decrement and test ctr option is specified (bo[2] = 0), the instruction form is invalid. other registers altered: affected: link register (lr) (if lk = 1) simplified mnemonics: bltctr equivalent to bcctr 12,0 bnectr cr2 equivalent to bcctr 4,10 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setbclr motorola mpc823e reference manual b-25 instruction set b bclr assembler syntax bclr bo,bi (lk = 0) bclrl bo,bi (lk = 1) definition branch conditional to link register operation m ? 32 if ? bo[2] then ctr ? ctr C 1 ctr_ok ? bo[2] | ((ctr 1 0) ? bo[3]) cond_ok ? bo[0] | (cr[bi] o bo[1]) if ctr_ok & cond_ok then nia ? iea lr || 0b00 if lk then lr ? iea cia + 4 description the bi field specifies the bit in the condition register to be used as the condition of the branch. the bo field is encoded as described in the table below. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 bo bi bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 16 lk bo description 0000 y decrement the ctr, then branch if the condition is false. 0001 y decrement the ctr, then branch if the condition is false. 001 zy branch if the condition is false. 0100 y decrement the ctr, then branch if the condition is true. 0101 y decrement the ctr, then branch if the condition is true. 011 zy branch if the condition is true. 1 z 00 y decrement the ctr, then branch if the decremented ctr 1 0. 1 z 01 y decrement the ctr, then branch if the decremented ctr = 0. 1 z 1 zz branch always. note: in this table, z indicates a bit that is ignored. the z bits must be cleared. the y bit has a hint about whether a conditional branch is likely to be taken.
mpc823e instruction setbclr b-26 mpc823e reference manual motorola instruction set b the branch target address is lr[0-29] || 0b00. if lk = 1, then the effective address of the instruction following the branch instruction is placed into the link register. other registers altered: affected: count register (ctr) (if bo[2] = 0) affected: link register (lr) (if lk = 1) simplified mnemonics: bltlr equivalent to bclr 12,0 bnelr cr2 equivalent to bclr 4,10 bdnzlr equivalent to bclr 16,0 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcmp motorola mpc823e reference manual b-27 instruction set b cmp assembler syntax cmp crfd,l,ra,rb definition compare operation a ? exts( r a) b ? exts( r b) if a < b then c ? 0b100 else if a > b then c ? 0b010 else c ? 0b001 cr[4 * crf dC4 * crf d + 3] ? c || xer[so] description the contents of r a are compared with the contents of r b treating the operands as signed integers. the result of the comparison is placed into cr field crf d. other registers altered: o condition register (cr field specified by operand crfd): affected: lt, gt, eq, so simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 crfd 0 l a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 0000000000 0 cmpd r a ,r b equivalent to cmp 0,1,r a ,r b cmpw cr3,r a ,r b equivalent to cmp 3,0,r a ,r b powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setcmpi b-28 mpc823e reference manual motorola instruction set b cmpi assembler syntax cmpi crfd,l,ra,simm definition compare immediate operation a ? ( r a) if a < exts(simm) then c ? 0b100 else if a > exts(simm) then c ? 0b010 else c ? 0b001 cr[4 * crf dC4 * crf d + 3] ? c || xer[so] description the contents of r a are compared with the sign-extended value of the simm field, treating the operands as signed integers. the result of the comparison is placed into cr field crf d. other registers altered: o condition register (cr field specified by operand crfd): affected: lt, gt, eq, so simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 11 crfd 0 l a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm cmpdi r a , value equivalent to cmpi 0,1,r a , value cmpwi cr3,r a , value equivalent to cmpi 3,0,r a , value powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setcmpl motorola mpc823e reference manual b-29 instruction set b cmpl assembler syntax cmpl crfd,l,ra,rb definition compare logical operation a ? r a b ? r b if a u b then c ? 0b010 else c ? 0b001 cr[4 * crf dC4 * crf d + 3] ? c || xer[so] description the contents of r a are compared with the contents of r b, treating the operands as unsigned integers. the result of the comparison is placed into cr field crf d. other registers altered: o condition register (cr field specified by operand crfd): affected: lt, gt, eq, so simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 crfd 0 l a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b320 cmpld r a ,r b equivalent to cmpl 0,1,r a ,r b cmplw cr3,r a ,r b equivalent to cmpl 3,0,r a ,r b powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setcmpli b-30 mpc823e reference manual motorola instruction set b cmpli assembler syntax cmpli crfd,l,ra,uimm definition compare logical immediate operation a ? ( r a) if a u ((16)0 || uimm) then c ? 0b010 else c ? 0b001 cr[4 * crf dC4 * crf d + 3] ? c || xer[so] description the contents of r a are compared with 0x0000|| uimm, treating the operands as unsigned integers. the result of the comparison is placed into cr field crf d. other registers altered: o condition register (cr field specified by operand crfd): affected: lt, gt, eq, so simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 10 crfd 0 l a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm cmpldi r a , value equivalent to cmpli 0,1,r a , value cmplwi cr3,r a , value equivalent to cmpli 3,0,r a , value powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setcntlzw motorola mpc823e reference manual b-31 instruction set b cntlzw assembler syntax cntlzw ra,rs (rc = 0) cntlzw. ra,rs (rc = 1) definition count leading zeros word operation n ? 0 do while n < 32 if r s[n] = 1 then leave n ? n + 1 r a ? n description a count of the number of consecutive zero bits starting at bit 0 of r s is placed into r a. this number ranges from 0 to 32, inclusive. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so(if rc = 1) if rc = 1, then lt is cleared in the cr0 field. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 26 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setcrand b-32 mpc823e reference manual motorola instruction set b crand assembler syntax crand crbd,crba,crbb definition condition register and operation cr[ crb d] ? cr[ crb a] & cr[ crb b] the bit in the condition register specified by crb a is anded with the bit in the condition register specified by crb b. the result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 257 0 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcrandc motorola mpc823e reference manual b-33 instruction set b crandc assembler syntax crandc crb d, crb a, crb b definition condition register and with complement operation cr[ crb d] ? cr[ crb a] & ? cr[ crb b] description the bit in the condition register specified by crb a is anded with the complement of the bit in the condition register specified by crb b and the result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 129 0 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcreqv b-34 mpc823e reference manual motorola instruction set b creqv assembler syntax creqv crbd,crba,crbb definition condition register equivalent operation cr[ crb d] ? cr[ crb a] o cr[ crb b] the bit in the condition register specified by crb a is xored with the bit in the condition register specified by crb b and the complemented result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 289 0 crset crb d equivalent to creqv crb d ,crb d , crb d powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcrnand motorola mpc823e reference manual b-35 instruction set b crnand assembler syntax crnand crbd,crba,crbb definition condition register nand operation cr[ crb d] ? ? (cr[ crb a] & cr[ crb b]) the bit in the condition register specified by crb a is anded with the bit in the condition register specified by crb b and the complemented result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 225 0 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcrnor b-36 mpc823e reference manual motorola instruction set b crnor assembler syntax crnor crbd,crba,crbb definition condition register nor operation cr[ crb d] ? ? (cr[ crb a] | cr[ crb b]) the bit in the condition register specified by crb a is ored with the bit in the condition register specified by crb b and the complemented result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 33 0 crnot crb d ,crb a equivalent to crnor crb d ,crb a , crb a powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcror motorola mpc823e reference manual b-37 instruction set b cror assembler syntax cror crbd,crba,crbb definition condition register or operation cr[ crb d] ? cr[ crb a] | cr[ crb b] description the bit in the condition register specified by crb a is ored with the bit in the condition register specified by crb b. the result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 449 0 crmove crb d ,crb a equivalent to cror crb d ,crb a , crb a powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcrorc b-38 mpc823e reference manual motorola instruction set b crorc assembler syntax crorc crbd,crba,crbb definition condition register or with complement operation cr[ crb d] ? cr[ crb a] | ? cr[ crb b] description the bit in the condition register specified by crb a is ored with the complement of the condition register bit specified by crb b and the result is placed into the condition register bit specified by crb d. other registers altered: o condition register: affected: bit specified by operand crbd bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 417 0 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setcrxor motorola mpc823e reference manual b-39 instruction set b crxor assembler syntax crxor crbd,crba,crbb definition condition register xor operation cr[ crb d] ? cr[ crb a] ? cr[ crb b] description the bit in the condition register specified by crb a is xored with the bit in the condition register specified by crb b and the result is placed into the condition register specified by crb d. other registers altered: o condition register: affected: bit specified by crbd simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crbd crba bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crbb 193 0 crclr crb d equivalent to crxor crb d ,crb d , crb d powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setdcbf b-40 mpc823e reference manual motorola instruction set b dcbf assemblersyntax dcbf ra,rb definition data cache block flush operation ea is the sum ( r a|0) + ( r b). description the dcbf instruction invalidates the block in the data cache addressed by ea, copying the block to memory first, if there is any dirty data in it. if the processor is a multiprocessor implementation and the block is marked coherency-required, the processor will, if necessary, send an address-only broadcast to other processors. the broadcast of the dcbf instruction causes another processor to copy the block to memory, if it has dirty data, and then invalidate the block from the cache. the action taken depends on the memory mode associated with the block containing the byte addressed by ea and on the state of that block. the list below describes the action taken for the various states of the memory coherency attribute (m bit). ? coherency required o unmodified blockinvalidates copies of the block in the data caches of all processors. o modified blockcopies the block to memory. invalidates copies of the block in the data caches of all processors. o absent blockif modified copies of the block are in the data caches of other processors, causes them to be copied to memory and invalidated in those data caches. if unmodified copies are in the data caches of other processors, causes those copies to be invalidated in those data caches. ? coherency not required o unmodified blockinvalidates the block in the processors data cache. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b860
mpc823e instruction setdcbf motorola mpc823e reference manual b-41 instruction set b o modified blockcopies the block to memory. invalidates the block in the processors data cache. o absent block (target block not in cache)no action is taken. the function of this instruction is independent of the write- through, write-back and caching-inhibited /allowed modes of the block containing the byte addressed by ea. this instruction may be treated as a load from the addressed byte with respect to address translation and memory protection. it may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. other registers altered: ? none powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setdcbi b-42 mpc823e reference manual motorola instruction set b dcbi asembler syntax dcbi ra,rb definition data cache block invalidate operation ea is the sum ( r a|0) + ( r b). description the action taken is dependent on the memory mode associated with the block containing the byte addressed by ea and on the state of that block. the list below describes the action taken if the block containing the byte addressed by ea is or is not in the cache. ? coherency required o unmodified blockinvalidates copies of the block in the data caches of all processors. o modified blockinvalidates copies of the block in the data caches of all processors. (discards the modified contents.) o absent blockif copies of the block are in the data caches of any other processor, causes the copies to be invalidated in those data caches. (discards any modified contents.) ? coherency not required o unmodified blockinvalidates the block in the processors data cache. o modified blockinvalidates the block in the processors data cache. (discards the modified contents.) o absent block (target block not in cache)no action is taken. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 470 0
mpc823e instruction setdcbi motorola mpc823e reference manual b-43 instruction set b when data address translation is enabled, msr[dr] = 1, and the virtual address has no translation, a dsi exception occurs. the function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the block containing the byte addressed by ea. this instruction operates as a store to the addressed byte with respect to address translation and protection. the referenced and changed bits are modified appropriately. this is a supervisor-level instruction. other registers altered: ? none powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setdcbst b-44 mpc823e reference manual motorola instruction set b dcbst assembler syntax dcbst ra,rb definition data cache block store operation ea is the sum ( r a|0) + ( r b). description the dcbst instruction executes as follows: ? if the block containing the byte addressed by ea is in coherency-required mode, and a block containing the byte addressed by ea is in the data cache of any processor and has been modified, the writing of it to main memory is initiated. ? if the block containing the byte addressed by ea is in coherency-not-required mode, and a block containing the byte addressed by ea is in the data cache of this processor and has been modified, the writing of it to main memory is initiated. the function of this instruction is independent of the write- through and caching-inhibited/allowed modes of the block containing the byte addressed by ea. the processor treats this instruction as a load from the addressed byte with respect to address translation and memory protection. it may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. other registers altered: ? none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b540 powerpc architecture level supervisor level optional form vea x
mpc823e instruction setdcbt motorola mpc823e reference manual b-45 instruction set b dcbt assembler syntax dcbt ra,rb definition data cache block touch operation ea is the sum ( r a|0) + ( r b). description this instruction is a hint that performance will probably be improved if the block containing the byte addressed by ea is fetched into the data cache, because the program will probably soon load from the addressed byte. the hint is ignored if the block is caching-inhibited. executing dcbt does not cause the system alignment error handler to be invoked. this instruction may be treated as a load from the addressed byte with respect to address translation, memory protection, and reference and change recording, except that no exception occurs in the case of a translation fault or protection violation. the program uses the dcbt instruction to request a cache block fetch before it is actually needed by the program. the program can later execute load instructions to put data into registers. however, the processor is not obliged to load the addressed block into the data cache. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 278 0 powerpc architecture level supervisor level optional form vea x
mpc823e instruction setdcbtst b-46 mpc823e reference manual motorola instruction set b dcbtst assembler syntax dcbtst ra,rb definition data cache block touch for store operation ea is the sum ( r a|0) + ( r b). description this instruction is a hint that performance will be improved if the block containing the byte addressed by ea is fetched into the data cache, because the program will probably soon store into the addressed byte. the hint is ignored if the block is caching- inhibited. executing dcbtst does not cause the system alignment error handler to be invoked. this instruction operates as a load from the addressed byte with respect to address translation and protection, except that no exception occurs in the case of a translation fault or protection violation. also, if the referenced and changed bits are recorded, they are recorded as if the access was a load. the program uses dcbtst to request a cache block fetch to guarantee that a subsequent store will be to a cached location. the program can later execute store instructions to put data into memory. however, the processor is not obliged to load the addressed cache block into the data cache. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 246 0 powerpc architecture level supervisor level optional form vea x
mpc823e instruction setdcbz motorola mpc823e reference manual b-47 instruction set b dcbz assembler syntax dcbz ra,rb definition data cache block set to zero operation ea is the sum ( r a|0) + ( r b). description the dcbz instruction executes as follows: o if the cache block containing the byte addressed by ea is in the data cache, all bytes are cleared. o if the cache block containing the byte addressed by ea is not in the data cache and the corresponding page is caching-allowed, the cache block is allocated in the data cache (without fetching the block from main memory), and all bytes are cleared. o if the page containing the byte addressed by ea is in caching-inhibited or write-through mode, either all bytes of main memory that correspond to the addressed cache block are cleared or the alignment exception handler is invoked. the exception handler clears all bytes in main memory that corresponds to the addressed cache block. o if the cache block containing the byte addressed by ea is in coherency-required mode, and the cache block exists in the data cache(s) of any other processor(s), it is kept coherent in those caches. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 1014 0
mpc823e instruction setdcbz b-48 mpc823e reference manual motorola instruction set b this instruction is treated as a store to the addressed byte with respect to address translation, memory protection, referenced and changed recording and the ordering enforced by eieio or by the combination of caching-inhibited and guarded attributes for a page. other registers altered: o none powerpc architecture level supervisor level optional form vea x
mpc823e instruction setdivw motorola mpc823e reference manual b-49 instruction set b divw assembler syntax divw rd,ra,rb (oe = 0 rc = 0) divw. rd,ra,rb (oe = 0 rc = 1) divwo rd,ra,rb (oe = 1 rc = 0) divwo. rd,ra,rb (oe = 1 rc = 1) definition divide word operation dividend ? ( r a) divisor ? ( r b) r d ? dividend ? divisor description the dividend is the contents of r a. the divisor is the contents of r b. the 32-bit quotient is formed and placed in r d. the remainder is not supplied as a result. both the operands and the quotient are interpreted as signed integers. the quotient is the unique signed integer that satisfies the equationdividend = (quotient * divisor) + r where 0 r < |divisor| (if the dividend is non-negative), and C|divisor| < r 0 (if the dividend is negative). if an attempt is made to perform any of the divisions 0x8000_0000 ? C1or ? 0then the contents of r d are undefined, as are the contents of the lt, gt, and eq bits of the cr0 field (if rc = 1). in this case, if oe = 1 then ov is set. the 32-bit signed remainder of dividing the contents of ra by the contents of rb can be computed as follows, except in the case that the contents of ra = C231 and the contents of rb = C1. divw r d ,r a ,r b# r d = quotient mullw r d ,r d ,r b# r d = quotient * divisor subf r d ,r d ,r a# r d = remainder bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b oe 491 rc
mpc823e instruction setdivw b-50 mpc823e reference manual motorola instruction set b other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) o xer: affected: so, ov (if oe = 1) the setting of the affected bits in the xer is mode-independent, and reflects overflow of the 32-bit result. powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setdivwu motorola mpc823e reference manual b-51 instruction set b divwu assembler syntax divwu rd,ra,rb (oe = 0 rc = 0) divwu. rd,ra,rb (oe = 0 rc = 1) divwuo rd,ra,rb (oe = 1 rc = 0) divwuo. rd,ra,rb (oe = 1 rc = 1) definition divide word unsigned operation dividend ? ( r a) divisor ? ( r b) r d ? dividend ? divisor description the dividend is the contents of r a. the divisor is the contents of r b. a 32-bit quotient is formed. the 32-bit quotient is placed into r d. the remainder is not supplied as a result. both operands and the quotient are interpreted as unsigned integers, except that if rc = 1 the first three bits of cr0 field are set by signed comparison of the result to zero. the quotient is the unique unsigned integer that satisfies the equation dividend = (quotient * divisor) + r (where 0 r < divisor). if an attempt is made to perform the division ? 0then the contents of r d are undefined as are the contents of the lt, gt, and eq bits of the cr0 field (if rc = 1). in this case, if oe = 1 then ov is set. the 32-bit unsigned remainder of dividing the contents of ra by the contents of rb can be computed as follows: divwu rd,ra,rb # rd = quotient mullw rd,rd,rb # rd = quotient * divisor subf rd,rd,ra # rd = remainder bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b oe 459 rc
mpc823e instruction setdivwu b-52 mpc823e reference manual motorola instruction set b other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so(if rc = 1) o xer: affected: so, ov(if oe = 1) the setting of the affected bits in the xer is mode- independent, and reflects overflow of the 32-bit result. powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction seteciwx motorola mpc823e reference manual b-53 instruction set b eciwx assembler syntax eciwx rd,ra,rb definition external control in word indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) paddr ? address translation of ea send load word request for paddr to device identified by ear[rid] r d ? word from device description the eciwx instruction allows the system designer to map special devices in an alternative way. the mmu translation of the ea is not used to select the special device, as it is used in most instructions such as loads and stores. rather, it is used as an address operand that is passed to the device over the address bus. four other pins (the burst and size pins on the 60x bus) are used to select the device; these four pins output the 4-bit resource id (rid) field that is located in the ear register. the eciwx instruction also loads a word from the data bus that is output by the special device. the eciwx instruction and the ear register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers. ea is the sum ( r a|0) + ( r b). a load word request for the physical address (referred to as real address in the architecture specification) corresponding to ea is sent to the device identified by ear[rid], bypassing the cache. the word returned by the device is placed in r d. ear[e] must be 1. if it is not, a dsi exception is generated. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 310 0
mpc823e instruction seteciwx b-54 mpc823e reference manual motorola instruction set b ea must be a multiple of four. if it is not, one of the following occurs: ? a system alignment exception is generated. ? a dsi exception is generated (possible only if ear[e] = 0). ? the results are boundedly undefined. the eciwx instruction is supported for eas that reference memory segments in which sr[t] = 1 and for eas mapped by the dbat registers. if the ea references a direct-store segment (sr[t] = 1), either a dsi exception occurs or the results are boundedly undefined. however, note that the direct-store facility is being phased out of the architecture and will not likely be supported in future devices. thus, software must not depend on its effects. if this instruction is executed when msr[dr] = 0 (real addressing mode), the results are boundedly undefined. this instruction is treated as a load from the addressed byte with respect to address translation, memory protection, referenced and changed bit recording, and the ordering performed by eieio . this instruction is optional in the powerpc architecture. other registers altered: ? none powerpc architecture level supervisor level optional form vea ? x
mpc823e instruction setecowx motorola mpc823e reference manual b-55 instruction set b ecowx assembler syntax ecowx rs,ra,rb definition external control out word indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) paddr ? address translation of ea send store word request for paddr to device identified by ear[rid] send r s to device description the ecowx instruction and the ear register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers. ea is the sum ( r a|0) + ( r b). a store word request for the physical address corresponding to ea and the contents of r s are sent to the device identified by ear[rid], bypassing the cache. ear[e] must be 1, if it is not, a dsi exception is generated. ea must be a multiple of four. if it is not, one of the following occurs: ? a system alignment exception is generated. ? a dsi exception is generated (possible only if ear[e] = 0). ? the results are boundedly undefined. the ecowx instruction is supported for effective addresses that reference memory segments in which sr[t] = 0, and for eas mapped by the dbat registers. if the ea references a direct- store segment (sr[t] = 1), either a dsi exception occurs or the results are boundedly undefined. however, note that the direct- store facility is being phased out of the architecture and will not likely be supported in future devices. thus, software must not depend on its effects. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 438 0
mpc823e instruction setecowx b-56 mpc823e reference manual motorola instruction set b if this instruction is executed when msr[dr] = 0 (real addressing mode), the results are boundedly undefined. this instruction is treated as a store from the addressed byte with respect to address translation, memory protection, nd referenced and changed bit recording, and the ordering performed by eieio . this instruction is optional in the powerpc architecture. other registers altered: ? none powerpc architecture level supervisor level optional form vea ? x
mpc823e instruction seteieio motorola mpc823e reference manual b-57 instruction set b eieio definition enforce in-order execution of i/o description the eieio instruction provides an ordering function for the effects of load and store instructions executed by a processor. these loads and stores are divided into two sets, which are ordered separately. the memory accesses caused by a dcbz instruction are ordered like a store. the two sets are as follows: ? loads and stores to memory that are caching-inhibited, guarded, and stores to memory that is write-through required. the eieio instruction controls the order in which the accesses are performed in main memory. it ensures that all applicable memory accesses caused by instructions preceding the eieio instruction have completed with respect to main memory before any applicable memory accesses caused by instructions following the eieio instruction access main memory. it acts as a barrier that flows through the memory queues to main memory, preventing the reordering of memory accesses across the barrier. no ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked. all accesses in this set are ordered as a single setthat is, there is not one order for loads and stores to caching-inhibited and guarded memory and another order for stores to write-through required memory. ? stores to memory that have all of the following attributes caching-allowed, write-through not required, and memory- coherency required. the eieio instruction controls the order in which the accesses are performed with respect to coherent memory. it ensures that all applicable stores caused by instructions preceding the eieio instruction have completed with respect to coherent memory before any applicable stores caused by instructions following the eieio instruction complete with respect to coherent memory. with the exception of dcbz , eieio does not affect the order of cache operations (whether caused explicitly by execution of bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 854 0
mpc823e instruction seteieio b-58 mpc823e reference manual motorola instruction set b a cache management instruction, or implicitly by the cache coherency mechanism). the eieio instruction does not affect the order of accesses in one set with respect to accesses in the other set. the eieio instruction may complete before memory accesses caused by instructions preceding the eieio instruction have been performed with respect to main memory or coherent memory as appropriate. the eieio instruction is intended for use in managing shared data structures, in accessing memory-mapped i/o, and in preventing load/store combining operations in main memory. for the first use, the shared data structure and the lock that protects it must be altered only by stores that are in the same set (1 or 2; see previous discussion). for the second use, eieio can be thought of as placing a barrier into the stream of memory accesses issued by a processor, such that any given memory access appears to be on the same side of the barrier to both the processor and the i/o device. because the processor performs store operations in order to memory that is designated as both caching-inhibited and guarded, the eieio instruction is needed for such memory only when loads must be ordered with respect to stores or with respect to other loads. note that the eieio instruction does not connect hardware considerations to it, such as multiprocessor implementations that send an eieio address-only broadcast (useful in some designs). for example, if a design has an external buffer that reorders loads and stores for better bus efficiency, the eieio broadcast signals to that buffer that previous loads/stores (marked caching-inhibited, guarded, or write-through required) must complete before any following loads/stores (marked caching-inhibited, guarded, or write-through required). other registers altered: o none powerpc architecture level supervisor level optional form vea x
mpc823e instruction seteqv motorola mpc823e reference manual b-59 instruction set b eqv assembler syntax eqv ra,rs,rb (rc = 0) eqv. ra,rs,rb (rc = 1) definition equivalent operation r a ? ( r s) o ( r b) description the contents of r s are xored with the contents of r b and the complemented result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 284 rc powerpc architecture level supervisor level optional form vea x
mpc823e instruction setextsb b-60 mpc823e reference manual motorola instruction set b extsb assembler syntax extsb ra,rs (rc = 0) extsb. ra,rs (rc = 1) definition extend sign byte operation s ? r s[24] r a[24-31] ? r s[24-31] r a[0C23] ? (24)s description the contents of r s[24-31] are placed into r a[24-31]. bit 24 of r s is placed into r a[0-23]. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 954 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setextsh motorola mpc823e reference manual b-61 instruction set b extsh assembler syntax extsh ra,rs (rc = 0) extsh. ra,rs (rc = 1) definition extend sign half word operation s ? r s[16] r a[16-31] ? r s[16-31] r a[0-15] ? (16)s description the contents of r s[16-31] are placed into r a[16-31]. bit 16 of r s is placed into r a[0C15]. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 922 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction seticbi b-62 mpc823e reference manual motorola instruction set b icbi assembler syntax icbi ra,rb definition instruction cache block invalidate description ea is the sum ( r a|0) + ( r b). if the block containing the byte addressed by ea is in coherency- required mode, and a block containing the byte addressed by ea is in the instruction cache of any processor, the block is made invalid in all such instruction caches, so that subsequent references cause the block to be refetched. if the block containing the byte addressed by ea is in coherency- not-required mode, and a block containing the byte addressed by ea is in the instruction cache of this processor, the block is made invalid in that instruction cache, so that subsequent references cause the block to be refetched. the function of this instruction is independent of the write-through, write-back, and caching-inhibited/allowed modes of the block containing the byte addressed by ea. this instruction is treated as a load from the addressed byte with respect to address translation and memory protection. it may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. implementations with a combined data and instruction cache treat the icbi instruction as a no-op, except that they may invalidate the target block in the instruction caches of other processors if the block is in coherency-required mode. the icbi instruction invalidates the block at ea (ra|0 + rb). if the processor is a multiprocessor implementation and the block is marked coherency-required, the processor will send an address only broadcast to other processors causing those processors to invalidate the block from their instruction caches. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 982 0
mpc823e instruction seticbi motorola mpc823e reference manual b-63 instruction set b for faster processing, many implementations will not compare the entire ea (ra|0 + rb) with the tag in the instruction cache. instead, they will use the bits in the ea to locate the set that the block is in, and invalidate all blocks in that set. other registers altered: o none powerpc architecture level supervisor level optional form vea x
mpc823e instruction setisync b-64 mpc823e reference manual motorola instruction set b isync definition instruction synchronize description the isync instruction provides an ordering function for the effects of all instructions executed by a processor. executing an isync instruction ensures that all instructions preceding the the isync instruction have completed before the isync instruction completes, except that memory accesses caused by those instructions need not have been performed with respect to other processors and mechanisms. it also ensures that no subsequent instructions are initiated by the processor until after the isync instruction completes. finally, it causes the processor to discard any prefetched instructions, with the effect that subsequent instructions will be fetched and executed in the context established by the instructions preceding the isync instruction. the isync instruction has no effect on the other processors or on their caches. this instruction is context synchronizing. context synchronization is necessary after certain code sequences that perform complex operations within the processor. these code sequences are usually operating system tasks that involve memory management. for example, if an instruction a changes the memory translation rules in the memory management unit (mmu) , the isync instruction must be executed so that the instructions following instruction a will be discarded from the pipeline and refetched according to the new translation rules. this instruction is context synchronizing. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 150 0 powerpc architecture level supervisor level optional form vea xl
mpc823e instruction setlbz motorola mpc823e reference manual b-65 instruction set b lbz assembler syntax lbz rd,d(ra) definition load byte and zero operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) r d ? (24)0 || mem(ea, 1) description ea is the sum ( r a|0) + d. the byte in memory addressed by ea is loaded into the low-order eight bits of r d. the remaining bits in r d are cleared. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 34 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlbzu b-66 mpc823e reference manual motorola instruction set b lbzu assembler syntax lbzu rd,d(ra) definition load byte and zero with update operation ea ? ( r a) + exts(d) r d ? (24)0 || mem(ea, 1) r a ? ea description ea is the sum ( r a) + d. the byte in memory addressed by ea is loaded into the low-order eight bits of r d. the remaining bits in r d are cleared. ea is placed into r a. if ra = 0, or ra = rd, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 35 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlbzux motorola mpc823e reference manual b-67 instruction set b lbzux assembler syntax lbzux rd,ra,rb definition load byte and zero with update indexed operation ea ? ( r a) + ( r b) r d ? (24)0 || mem(ea, 1) r a ? ea description ea is the sum ( r a) + ( r b). the byte in memory addressed by ea is loaded into the low-order eight bits of r d. the remaining bits in r d are cleared. ea is placed into r a. if ra = 0 or ra = rd, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 119 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlbzx b-68 mpc823e reference manual motorola instruction set b lbzx assembler syntax lbzx rd,ra,rb definition load byte and zero indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) r d ? (24)0 || mem(ea, 1) description ea is the sum ( r a|0) + ( r b). the byte in memory addressed by ea is loaded into the low-order eight bits of r d. the remaining bits in r d are cleared. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b870 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlha motorola mpc823e reference manual b-69 instruction set b lha assembler syntax lha rd,d(ra) definition load half word algebraic operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) r d ? exts(mem(ea, 2)) description ea is the sum ( r a|0) + d. the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are filled with a copy of the most-significant bit of the loaded half word. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 42 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlhau b-70 mpc823e reference manual motorola instruction set b lhau assembler syntax lhau rd,d(ra) definition load half word algebraic with update operation ea ? ( r a) + exts(d) r d ? exts(mem(ea, 2)) r a ? ea description ea is the sum ( r a) + d. the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are filled with a copy of the most-significant bit of the loaded half word. ea is placed into ra. if r a = 0 or r a = r d, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 43 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlhaux motorola mpc823e reference manual b-71 instruction set b lhaux assembler syntax lhaux rd,ra,rb definition load half word algebraic with update indexed operation ea ? ( r a) + ( r b) r d ? exts(mem(ea, 2)) r a ? ea description ea is the sum ( r a) + ( r b). the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are filled with a copy of the most-significant bit of the loaded half word. ea is placed into r a. if ra = 0 or ra = rd, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 375 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlhax b-72 mpc823e reference manual motorola instruction set b lhax assembler syntax lhax rd,ra,rb definition load half word algebraic indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) r d ? exts(mem(ea, 2)) description ea is the sum ( r a|0) + ( r b). the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are filled with a copy of the most-significant bit of the loaded half word. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 343 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlhbrx motorola mpc823e reference manual b-73 instruction set b lhbrx assembler syntax lhbrx rd,ra,rb definition load half word byte-reverse indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) r d ? (16)0 || mem(ea + 1, 1) || mem(ea, 1) description ea is the sum ( r a|0) + ( r b). bits 0C7 of the half word in memory addressed by ea are loaded into the low-order eight bits of r d. bits 8C15 of the half word in memory addressed by ea are loaded into the subsequent low-order eight bits of r d. the remaining bits in r d are cleared. the powerpc architecture cautions programmers that some implementations of the architecture may run the lhbrx instructions with greater latency than other types of load instructions. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 790 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlhz b-74 mpc823e reference manual motorola instruction set b lhz assembler syntax lhz rd,d(ra) definition load half word and zero operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) r d ? (16)0 || mem(ea, 2) description ea is the sum ( r a|0) + d. the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are cleared. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 40 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlhzu motorola mpc823e reference manual b-75 instruction set b lhzu assembler syntax lhzu rd,d(ra) definition load half word and zero with update operation ea ? r a + exts(d) r d ? (16)0 || mem(ea, 2) r a ? ea description ea is the sum ( r a) + d. the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are cleared. ea is placed into r a. if r a = 0 or r a = r d, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 41 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlhzux b-76 mpc823e reference manual motorola instruction set b lhzux assembler syntax lhzux rd,ra,rb definition load half word and zero with update indexed operation ea ? ( r a) + ( r b) r d ? (16)0 || mem(ea, 2) r a ? ea description ea is the sum ( r a) + ( r b). the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are cleared. ea is placed into r a. if r a = 0 or r a = r d, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 311 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlhzx motorola mpc823e reference manual b-77 instruction set b lhzx assembler syntax lhzx rd,ra,rb definition load half word and zero indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) r d ? (16)0 || mem(ea, 2) description ea is the sum ( r a|0) + ( r b). the half word in memory addressed by ea is loaded into the low-order 16 bits of r d. the remaining bits in r d are cleared. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 279 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlmw b-78 mpc823e reference manual motorola instruction set b lmw assembler syntax lmw rd,d(ra) definition load multiple word operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) r ? r d do while r 31 gpr(r) ? mem(ea, 4) r ? r + 1 ea ? ea + 4 description ea is the sum ( r a|0) + d. n = (32 C r d). n consecutive words starting at ea are loaded into gprs r d through r31 . ea must be a multiple of four. if it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. if r a is in the range of registers specified to be loaded, including the case in which r a = 0, the instruction form is invalid. note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 46 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlswi motorola mpc823e reference manual b-79 instruction set b lswi assembler syntax lswi rd,ra,nb definition load string word immediate operation if r a = 0 then ea ? 0 else ea ? ( r a) if nb = 0 then n ? 32 else n ? nb r ? r d C 1 i ? 32 do while n > 0 if i = 32 then r ? r + 1 (mod 32) gpr(r) ? 0 gpr(r)[iCi + 7 ] ? mem(ea, 1) i ? i + 8 if i = 32 then i ? 0 ea ? ea + 1 n ? n C 1 description ea is (ra|0). let n = nb if nb 1 0, n = 32 if nb = 0; n is the number of bytes to load. let nr = ceil( n ? 4); nr is the number of registers to be loaded with data. n consecutive bytes starting at ea are loaded into gprs r d through r d + nr C 1. bytes are loaded left to right in each register. the sequence of registers wraps around to r0 if required. if the 4 bytes of register r d + nr C 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. if r a is in the range of registers specified to be loaded, including the case in which r a = 0, the instruction form is invalid. under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field nb 597 0
mpc823e instruction setlswi b-80 mpc823e reference manual motorola instruction set b note that, in some implementations, this instruction is likely to have greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. other registers altered: o none powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlswx motorola mpc823e reference manual b-81 instruction set b lswx assembler syntax lswx rd,ra,rb definition load string word indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) n ? xer[25C31] r ? r d C 1 i ? 32 r d ? undefined do while n > 0 if i = 32 then r ? r + 1 (mod 32) gpr(r) ? 0 gpr(r)[iCi + 7] ? mem(ea, 1) i ? i + 8 if i = 32 then i ? 0 ea ? ea + 1 n ? n C 1 description ea is the sum ( r a|0) + ( r b). let n = xer[25C31]; n is the number of bytes to load. let nr = ceil( n ? 4); nr is the number of registers to receive data. if n > 0, n consecutive bytes starting at ea are loaded into gprs r d through r d + nr C 1. bytes are loaded left to right in each register. the sequence of registers wraps around through r0 if required. if the four bytes of r d + nr C 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. if n = 0, the contents of r d are undefined. if r a or r b is in the range of registers specified to be loaded, including the case in which r a = 0, either the system illegal instruction error handler is invoked or the results are boundedly undefined. if r d = r a or r d = r b, the instruction form is invalid. if r d and r a both specify gpr0, the form is invalid. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 533 0
mpc823e instruction setlswx b-82 mpc823e reference manual motorola instruction set b under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. other registers altered: o none powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlwarx motorola mpc823e reference manual b-83 instruction set b lwarx assembly syntax lwarx rd,ra,rb definition load word and reserve indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) reserve ? 1 reserve_addr ? physical_addr(ea) r d ? mem(ea,4) description ea is the sum ( r a|0) + ( r b). the word in memory addressed by ea is loaded into r d. this instruction creates a reservation for use by a store word conditional indexed ( stwcx. ) instruction. the physical address computed from ea is associated with the reservation, and replaces any address previously associated with the reservation. ea must be a multiple of four. if it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. when the reserve bit is set, the processor enables hardware snooping for the block of memory addressed by the reserve address. if the processor detects that another processor writes to the block of memory it has reserved, it clears the reserve bit. the stwcx. instruction will only do a store if the reserve bit is set. the stwcx. instruction sets the cr0[eq] bit if the store was successful and clears it if it failed. the lwarx and stwcx. combination can be used for atomic read-modify-write sequences. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b200
mpc823e instruction setlwarx b-84 mpc823e reference manual motorola instruction set b note that the atomic sequence is not guaranteed, but its failure can be detected if cr0[eq] = 0 after the stwcx. instruction. other registers altered: o none powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlwbrx motorola mpc823e reference manual b-85 instruction set b lwbrx assembler syntax lwbrx rd,ra,rb definition load word byte-reverse indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) r d ? mem(ea + 3, 1) || mem(ea + 2, 1) || mem(ea + 1, 1) || mem(ea, 1) description ea is the sum ( r a|0) + r b. bits 0C7 of the word in memory addressed by ea are loaded into the low-order 8 bits of r d. bits 8C15 of the word in memory addressed by ea are loaded into the subsequent low-order 8 bits of r d. bits 16C23 of the word in memory addressed by ea are loaded into the subsequent low-order eight bits of r d. bits 24C31 of the word in memory addressed by ea are loaded into the subsequent low-order 8 bits of r d. the mpc823e may run the lwbrx instructions with greater latency than other types of load instructions. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 534 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlwz b-86 mpc823e reference manual motorola instruction set b lwz assembler syntax lwz rd,d(ra) definition load word and zero operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) r d ? mem(ea, 4) description ea is the sum ( r a|0) + d. the word in memory addressed by ea is loaded into r d. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 32 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlwzu motorola mpc823e reference manual b-87 instruction set b lwzu assembler syntax lwzu rd,d(ra) definition load word and zero with update operation ea ? r a + exts(d) r d ? mem(ea, 4) r a ? ea description ea is the sum ( r a) + d. the word in memory addressed by ea is loaded into r d. ea is placed into r a. if r a = 0, or r a = r d, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 33 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setlwzux b-88 mpc823e reference manual motorola instruction set b lwzux assembler syntax lwzux rd,ra,rb definition load word and zero with update indexed operation ea ? ( r a) + ( r b) r d ? mem(ea, 4) r a ? ea description ea is the sum ( r a) + ( r b). the word in memory addressed by ea is loaded into r d. ea is placed into r a. if r a = 0, or r a = r d, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b550 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setlwzx motorola mpc823e reference manual b-89 instruction set b lwzx assembler syntax lwzx rd,ra,rb definition load word and zero indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + r b r d ? mem(ea, 4) description ea is the sum ( r a|0) + ( r b). the word in memory addressed by ea is loaded into r d. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b230 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setmcrf b-90 mpc823e reference manual motorola instruction set b mcrf assembler syntax mcrf crfd,crfs definition move condition register field operation cr[4 * crf dC4 * crf d + 3] ? cr[4 * crf sC4 * crf s + 3] description the contents of condition register field crf s are copied into condition register field crf d. all other condition register fields remain unchanged. other registers altered: o condition register (cr field specified by operand crfd): affected: lt, gt, eq, so bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 crfd 00 crfs 00 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 0000000000 0 powerpc architecture level supervisor level optional form uisa xl
mpc823e instruction setmcrxr motorola mpc823e reference manual b-91 instruction set b mcrxr assembler syntax mcrxr crfd definition move to condition register from xer operation cr[4 * crf dC4 * crf d + 3 ] ? xer[0C3] xer[0C3] ? 0b0000 description the contents of xer[0C3] are copied into the condition register field designated by crf d. all other fields of the condition register remain unchanged. xer[0C3] is cleared. other registers altered: o condition register (cr field specified by operand crfd): affected: lt, gt, eq, so o xer[0C3] bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 crfd 00 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 512 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setmfcr b-92 mpc823e reference manual motorola instruction set b mfcr assembler syntax mfcr rd definition move from condition register operation r d ? cr description the contents of the condition register (cr) are placed into r d. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 19 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setmfmsr motorola mpc823e reference manual b-93 instruction set b mfmsr assembler syntax mfmsr rd definition move from machine state register operation r d ? msr description the contents of the msr are placed into r d. this is a supervisor level instruction. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 83 0 powerpc architecture level supervisor level optional form oea ? x
mpc823e instruction setmfspr b-94 mpc823e reference manual motorola instruction set b mfspr assembler syntax mfspr rd,spr definition move from special-purpose register operation n ? spr[5C9] || spr[0C4] r d ? spr( n ) description in the powerpc uisa, the spr field denotes a special-purpose register, encoded as shown in the table below. the contents of the designated special-purpose register are placed into r d. if the spr field contains any value other than one of the values shown in table 9 (and the processor is in user mode), one of the following occurs: ? the system illegal instruction error handler is invoked. ? the system supervisor-level instruction error handler is invoked. ? the results are boundedly undefined. other registers altered: ? none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d spr* bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field spr* 339 0 note: *this is a split field. spr* register name decimal spr[5C9] spr[0C4] 1 00000 00001 xer 8 00000 01000 lr 9 00000 01001 ctr note: *the order of the two 5-bit halves of the spr number is reversed compared with the actual instruction coding.
mpc823e instruction setmfspr motorola mpc823e reference manual b-95 instruction set b simplified mnemonics: in the powerpc oea, the spr field denotes a special-purpose register, encoded as shown in the table below. the contents of the designated spr are placed into r d. spr[0] = 1 if and only if reading the register is supervisor-level. execution of this instruction specifying a defined and supervisor-level register when msr[pr] = 1 will result in a priviledged instruction type program exception. if msr[pr] = 1, the only effect of executing an instruction with an spr number that is not shown in the table below and has spr[0] = 1 is to cause a supervisor-level instruction type program exception or an illegal instruction type program exception. for all other cases, msr[pr] = 0 or spr[0] = 0. if the spr field contains any value that is not shown in the table, either an illegal instruction type program exception occurs or the results are boundedly undefined. other registers altered: ? none mfxer r d equivalent to mfspr r d ,1 mflr r d equivalent to mfspr r d ,8 mfctr r d equivalent to mfspr r d ,9 spr 1 register name access decimal spr[5C9] spr[0C4] 1 00000 00001 xer user 8 00000 01000 lr user 9 00000 01001 ctr user 18 00000 10010 dsisr supervisor 19 00000 10011 dar supervisor 22 00000 10110 dec supervisor 26 00000 11010 srr0 supervisor 27 00000 11011 srr1 supervisor 80 00010 10000 eie 2 supervisor 81 00010 10001 eid 3 supervisor 144 00100 10000 cmpa 4 supervisor 145 00100 10001 cmpb 4 supervisor
mpc823e instruction setmfspr b-96 mpc823e reference manual motorola instruction set b 146 00100 10010 cmpc 4 supervisor 147 00100 10011 cmpd 4 supervisor 148 00100 10100 icr 4 supervisor 149 00100 10101 der 4 supervisor 150 00100 10110 counta 4 supervisor 151 00100 10111 countb 4 supervisor 152 00100 11000 cmpe 4 supervisor 153 00100 11001 cmpf 4 supervisor 154 00100 11010 cmpg 4 supervisor 155 00100 11011 cmph 4 supervisor 156 00100 11100 lctrl1 4 supervisor 157 00100 11101 lctrl2 4 supervisor 158 00100 11110 ictrl 4 supervisor 159 00100 11111 bar 4 supervisor 272 01000 10000 sprg0 supervisor 273 01000 10001 sprg1 supervisor 274 01000 10010 sprg2 supervisor 275 01000 10011 sprg3 supervisor 287 01000 11111 pvr supervisor 560 10001 10000 ic_cst supervisor 561 10001 10001 ic_adr supervisor 562 10001 10010 ic_dat supervisor 568 10001 11000 dc_cst supervisor 569 10001 11001 dc_adr supervisor 570 10001 11010 dc_dat supervisor 630 10011 10110 dpdr 4 supervisor 638 10011 11110 immr supervisor 784 11000 10000 mi_ctr supervisor 786 11000 10010 mi_ap supervisor 787 11000 10011 mi_epn supervisor 789 11000 10101 mi_twc supervisor 790 11000 10110 mi_rpn supervisor 792 11000 11000 md_ctr supervisor 793 11000 11001 m_casid supervisor spr 1 register name access decimal spr[5C9] spr[0C4]
mpc823e instruction setmfspr motorola mpc823e reference manual b-97 instruction set b 794 11000 11010 md_ap supervisor 795 11000 11011 md_epn supervisor 796 11000 11100 m_twb supervisor 797 11000 11101 md_twc supervisor 798 11000 11110 md_rpn supervisor 799 11000 11111 m_tw supervisor 816 11001 10000 mi_dbcam supervisor 817 11001 10001 mi_dbram0 supervisor 818 11001 10010 mi_dbram1 supervisor 824 11001 11000 md_dbcam supervisor 825 11001 11001 mi_dbram0 supervisor 826 11001 11010 mi_dbram1 supervisor notes: 1. the order of the two 5-bit halves of the spr number is reversed compared with actual instruction coding. 2. sets the ee bit in the msr. 3. clears the ee bit in the msr. 4. development support (debug) register. for mtspr and mfspr instructions, the spr number coded in assembly language does not appear directly as a 10-bit binary number in the instruction. the number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits 16C20 of the instruction and the low-order five bits in bits 11C15. powerpc architecture level supervisor level optional form uisa/oea ? xfx note: mfspr is supervisor-level only if spr[0] = 1. spr 1 register name access decimal spr[5C9] spr[0C4]
mpc823e instruction setmftb b-98 mpc823e reference manual motorola instruction set b mftb assembler syntax mftb rd,tbr definition move from time base operation n ? tbr[5C9] || tbr[0C4] if n = 268 then r d ? tbl else if n = 269 then r d ? tbu description if the tbr field contains any value other than one of the values shown in the table above, then one of the following occurs: ? the system illegal instruction error handler is invoked. ? the system supervisor-level instruction error handler is invoked. ? the results are boundedly undefined. it is important to note that some implementations may implement mftb and mfspr identically, therefore, a tbr number must not match an spr number. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d tbr bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tbr 371 0 tbr* register name access decimal tbr[5C9] tbr[0C4] 268 01000 01100 tb read user 269 01000 01101 tbu read user note: *the order of the two 5-bit halves of the tbr number is reversed.
mpc823e instruction setmftb motorola mpc823e reference manual b-99 instruction set b other registers altered: ? none simplified mnemonics: mftb r d equivalent to mftb r d ,268 mftbu r d equivalent to mftb r d ,269 powerpc architecture level supervisor level optional form vea xfx
mpc823e instruction setmtcrf b-100 mpc823e reference manual motorola instruction set b mtcrf assembler syntax mtcrf crm,rs definition move to condition register fields operation mask ? (4)(crm[0]) || (4)(crm[1]) ||... (4)(crm[7]) cr ? ( r s & mask) | (cr & ? mask) description the contents of r s are placed into the condition register under control of the field mask specified by crm. the field mask identifies the 4-bit fields affected. let i be an integer in the range 0C7. if crm(i) = 1, cr field i (cr bits 4 * i through 4 * i + 3) is set to the contents of the corresponding field of r s. note that updating a subset of the eight fields of the condition register may have substantially poorer performance on some implementations than updating all of the fields. other registers altered: o cr fields selected by mask simplified mnemonics: mtcr r s equivalent to mtcrf 0xff ,r s bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s 0 crm bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field crm 0 144 0 powerpc architecture level supervisor level optional form uisa xfx
mpc823e instruction setmtmsr motorola mpc823e reference manual b-101 instruction set b mtmsr assembler syntax mtmsr rs definition move to machine state register operation msr ? ( r s) description the contents of r s are placed into the msr. this is a supervisor level instruction. it is also an execution synchronizing instruction except with respect to alterations to the pow and le bits. in addition, alterations to the msr[ee] and msr[ri] bits are effective as soon as the instruction completes. thus if msr[ee] = 0 and an external or decrementer exception is pending, executing an mtmsr instruction that sets msr[ee] = 1 will cause the external or decrementer exception to be taken before the next instruction is executed, if no higher priority exception exists. other registers altered: o msr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 146 0 powerpc architecture level supervisor level optional form oea ? x
mpc823e instruction setmtspr b-102 mpc823e reference manual motorola instruction set b mtspr assembler syntax mtspr spr,rs definition move to special-purpose register operation n ? spr[5C9] || spr[0C4] spr( n ) ? r s description in the powerpc uisa, the spr field denotes a special-purpose register, encoded as shown in the following table. the contents of r s are placed into the designated special-purpose register. if the spr field contains any value other than one of the values shown in the table above, and the processor is operating in user mode, one of the following occurs: ? the system illegal instruction error handler is invoked. ? the system supervisor instruction error handler is invoked. ? the results are boundedly undefined. other registers altered: ? see table above. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s spr* bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field spr* 467 0 note: *this is a split field. spr* register name decimal spr[5C9] spr[0C4] 1 00000 00001 xer 8 00000 01000 lr 9 00000 01001 ctr note: *the order of the two 5-bit halves of the spr number is reversed compared with actual instruction coding.
mpc823e instruction setmtspr motorola mpc823e reference manual b-103 instruction set b simplified mnemonics: in the powerpc oea, the spr field denotes a special-purpose register, encoded as shown in the following table. the contents of r s are placed into the designated special-purpose register. for this instruction, sprs tbl and tbu are treated as separate 32-bit registers; setting one leaves the other unaltered. the value of spr[0] = 1 if and only if writing the register is a supervisor-level operation. execution of this instruction specifying a defined and supervisor-level register when msr[pr] = 1 results in a privileged instruction type program exception. if msr[pr] = 1 then the only effect of executing an instruction with an spr number that is not shown in the following table and has spr[0] = 1 is to cause a privileged instruction type program exception or an illegal instruction type program exception. for all other cases, msr[pr] = 0 or spr[0] = 0, if the spr field contains any value that is not shown in the table, either an illegal instruction type program exception occurs or the results are boundedly undefined. mtxer r d equivalent to mtspr 1,r d mtlr r d equivalent to mtspr 8,r d mtctr r d equivalent to mtspr 9,r d powerpc architecture level supervisor level optional form uisa/oea ? xfx note: mtspr is supervisor-level only if spr[0] = 1.
mpc823e instruction setmulhw b-104 mpc823e reference manual motorola instruction set b mulhw assembler syntax mulhw rd,ra,rb (rc = 0) mulhw. rd,ra,rb (rc = 1) definition multiply high word operation prod[0C63] ? r a * r b r d ? prod[0C31] description the 64 -bit product is formed from the contents of r a and r b. the high-order 32 bits of the 64-bit product of the operands are placed into r d. both the operands and the product are interpreted as signed integers. this instruction may execute faster on some implementations if r b contains the operand having the smaller absolute value. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 0 75 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setmulhwu motorola mpc823e reference manual b-105 instruction set b mulhwu assembler syntax mulhwu rd,ra,rb(rc = 0) mulhwu. rd,ra,rb(rc = 1) definition multiply high word unsigned operation prod[0C63 ] ? r a * r b r d ? prod[0C31] description the 32-bit operands are the contents of r a and r b. the high order 32 bits of the 64-bit product of the operands are placed into r d. both the operands and the product are interpreted as unsigned integers, except that if rc = 1 the first three bits of cr0 field are set by signed comparison of the result to zero. this instruction may execute faster on some implementations if r b contains the operand having the smaller absolute value. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 0 11 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setmulli b-106 mpc823e reference manual motorola instruction set b mulli assembler syntax mulli rd,ra,simm definition multiply low immediate operation prod[0C48 ] ? ( r a) * simm r d ? prod[16-48] description the first operand is ( r a). the 16-bit second operand is the value of the simm field. the low-order 32-bits of the 48-bit product of the operands are placed into r d. both the operands and the product are interpreted as signed integers. the low-order 32 bits of the product are calculated independently of whether the operands are treated as signed or unsigned 32-bit integers. this instruction can be used with mulhd x or mulhw x to calculate a full 64-bit product. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 07 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setmullw motorola mpc823e reference manual b-107 instruction set b mullw assembler syntax mullw rd,ra,rb (oe = 0 rc = 0) mullw. rd,ra,rb (oe = 0 rc = 1) mullwo rd,ra,rb (oe = 1 rc = 0) mullwo. rd,ra,rb (oe = 1 rc = 1) definition multiply low word operation r d ? r a * r b description the 32-bit operands are the contents of r a and r b. the low- order 32 bits of the 64-bit product ( r a) * ( r b) are placed into r d. the low-order 32 bits of the product are the correct 32-bit product for 32-bit implementations. the low-order 32-bits of the product are independent of whether the operands are regarded as signed or unsigned 32-bit integers. if oe = 1, then ov is set if the product cannot be represented in 32 bits. both the operands and the product are interpreted as signed integers. note that this instruction may execute faster on some implementations if r b contains the operand having the smaller absolute value. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1). the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: so, ov (if oe = 1). the setting of the affected bits in the xer is mode- independent, and reflects overflow of the 32-bit result. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b oe 235 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setnand b-108 mpc823e reference manual motorola instruction set b nand assembler syntax nand ra,rs,rb (rc = 0) nand. ra,rs,rb (rc = 1) definition nand operation r a ? ? (( r s) & ( r b)) description the contents of r s are anded with the contents of r b and the complemented result is placed into r a. nand with r s = r b can be used to obtain the one's complement. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 476 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setneg motorola mpc823e reference manual b-109 instruction set b neg assembler syntax neg rd,ra (oe = 0 rc = 0) neg. rd,ra (oe = 0 rc = 1) nego rd,ra (oe = 1 rc = 0) nego. rd,ra (oe = 1 rc = 1) definition negate operation r d ? ? ( r a) + 1 description the value 1 is added to the complement of the value in r a, and the resulting twos complement is placed into r d. if r a contains the most negative 32-bit number (0x8000_0000), the result is the most negative number and, if oe = 1, ov is set. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) o xer: affected: so ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 oe 104 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setnor b-110 mpc823e reference manual motorola instruction set b nor assembler syntax nor ra,rs,rb (rc = 0) nor. ra,rs,rb (rc = 1) definition nor operation r a ? ? (( r s) | ( r b)) description the contents of r s are ored with the contents of r b and the complemented result is placed into r a. nor with r s = r b can be used to obtain the ones complement. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 124 rc not r d ,r s equivalent to nor r a ,r s ,r s powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setor motorola mpc823e reference manual b-111 instruction set b or assembler syntax or ra,rs,rb (rc = 0) or. ra,rs,rb (rc = 1) definition or operation r a ? ( r s) | ( r b) description the contents of r s are ored with the contents of r b and the result is placed into r a. the simplified mnemonic mr (shown below) demonstrates the use of the or instruction to move register contents. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 444 rc mr r a ,r s equivalent to or r a ,r s ,r s powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setorc b-112 mpc823e reference manual motorola instruction set b orc assembler syntax orc ra,rs,rb (rc = 0) orc. ra,rs,rb (rc = 1) definition or with complement operation r a ? ( r s) | ? ( r b) description the contents of r s are ored with the complement of the contents of r b and the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 412 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setori motorola mpc823e reference manual b-113 instruction set b ori assembler syntax ori ra,rs,uimm definition or immediate operation r a ? ( r s) | ((16)0 || uimm) description the contents of r s are ored with 0x0000|| uimm and the result is placed into r a. the preferred no-op (an instruction that does nothing) is ori 0,0,0 . other registers altered: o none simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 24 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm nop equivalent to ori 0,0,0 powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setoris b-114 mpc823e reference manual motorola instruction set b oris assembler syntax oris ra,rs,uimm definition or immediate shifted operation r a ? ( r s) | (uimm || (16)0) description the contents of r s are ored with uimm || 0x0000 and the result is placed into r a. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 25 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setrfi motorola mpc823e reference manual b-115 instruction set b rfi definition return from interrupt operation msr[16C23, 25C27, 30C31] ? srr1[16C23, 25C27, 30C31] nia ? iea srr0[0C29] || 0b00 description bits srr1[0,5-9,16-31] are placed into the corresponding bits of the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address srr0[0C29] || 0b00. if the new msr value enables one or more pending exceptions, the exception associated with the highest priority pending exception is generated; in this case the value placed into srr0 by the exception processing mechanism is the address of the instruction that would have been executed next had the exception not occurred. note that an implementation may define addtional msr bits, and in this case, may also cause them to be saved to srr1 from msr on an exception and restored to msr from srr1 on an rfi. this is a supervisor-level, context synchronizing instruction. other registers altered: o msr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 19 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 50 0 powerpc architecture level supervisor level optional form oea ? xl
mpc823e instruction setrlwimi b-116 mpc823e reference manual motorola instruction set b rlwimi assembler syntax rlwimi ra,rs,sh,mb,me (rc = 0) rlwimi. ra,rs,sh,mb,me (rc = 1) definition rotate left word immediate then mask insert operation n ? sh r ? rotl( r s, n ) m ? mask(mb, me) r a ? (r & m) | ( r a & ? m) description the contents of r s are rotated left the number of bits specified by operand sh. a mask is generated having 1 bits from bit mb through bit me and 0 bits elsewhere. the rotated data is inserted into r a under control of the generated mask. note that rlwimi can be used to insert a bit field into the contents of ra using the methods shown below: o to insert an n-bit field, that is left-justified rs, into ra starting at bit position b, set sh = 32 C b, mb = b, and me = (b + n) C 1. o to insert an n-bit field, that is right-justified in rs, into ra starting at bit position b, set sh = 32 C (b + n), mb = b, and me = (b + n) C 1. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so(if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 20 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field sh mb me rc
mpc823e instruction setrlwimi motorola mpc823e reference manual b-117 instruction set b simplified mnemonics: inslwi r a ,r s , n , b equivalent to rlwimi r a ,r s , 32 C b , b , b + n C 1 insrwi r a ,r s , n , b (n > 0) equivalent to rlwimi r a ,r s ,32 C ( b + n ) , b , ( b + n ) C 1 powerpc architecture level supervisor level optional form uisa m
mpc823e instruction setrlwinm b-118 mpc823e reference manual motorola instruction set b rlwinm assembler syntax rlwinm ra,rs,sh,mb,me (rc = 0) rlwinm. ra,rs,sh,mb,me (rc = 1) definition rotate left word immediate then and with mask operation n ? sh r ? rotl( r s, n ) m ? mask(mb, me) r a ? r & m description the contents of r s are rotated left the number of bits specified by operand sh. a mask is generated having 1 bits from bit mb through bit me and 0 bits elsewhere. the rotated data is anded with the generated mask and the result is placed into r a. description rlwinm can be used to extract, rotate, shift, and clear bit fields using the methods shown below: o to extract an n field, that starts at bit position b in r s, right-justified into r a (clearing the remaining 32 C n bits of r a), set sh = b + n, mb = 32 C n, and me = 31. o to extract an n field, that starts at bit position b in rs, left- justified into ra (clearing the remaining 32 C n bits of r a), set sh = b, mb = 0, and me = n C 1. o to rotate the contents of a register left (or right) by n bits, set sh = n (32 C n), mb = 0, and me = 31. o to shift the contents of a register right by n bits, by setting sh = 32 C n, mb = n, and me = 31. it can be used to clear the high-order b bits of a register and then shift the result left by n bits by setting sh = n, mb = b C n and me = 31 C n. o to clear the low-order n bits of a register, by setting sh = 0, mb = 0, and me = 31 C n. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 21 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field sh mb me rc
mpc823e instruction setrlwinm motorola mpc823e reference manual b-119 instruction set b other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so(if rc = 1) simplified mnemonics: extlwi r a ,r s , n , b ( n > 0) equivalent to rlwinm r a ,r s , b ,0, n C 1 extrwi r a ,r s , n , b ( n > 0) equivalent to rlwinm r a ,r s , b + n , 32 C n ,31 rotlwi r a ,r s , n equivalent to rlwinm r a ,r s , n ,0,31 rotrwi r a ,r s , n equivalent to rlwinm r a ,r s ,32 C n ,0,31 slwi r a ,r s , n ( n < 32) equivalent to rlwinm r a ,r s , n ,0, 31 C n srwi r a ,r s , n ( n < 32) equivalent to rlwinm r a ,r s , 32 C n , n ,31 clrlwi r a ,r s , n ( n < 32) equivalent to rlwinm r a ,r s ,0, n , 31 clrrwi r a ,r s , n ( n < 32) equivalent to rlwinm r a ,r s ,0,0, 31 C n clrlslwi r a ,r s , b , n ( n b < 32) equivalent to rlwinm r a ,r s , n , b C n , 31 C n powerpc architecture level supervisor level optional form uisa m
mpc823e instruction setrlwnm b-120 mpc823e reference manual motorola instruction set b rlwnm assembler syntax rlwnm ra,rs,rb,mb,me (rc = 0) rlwnm. ra,rs,rb,mb,me (rc = 1) definition rotate left word then and with mask operation n ? r b[27-31] r ? rotl( r s, n ) m ? mask(mb, me) r a ? r & m description the contents of r s are rotated left the number of bits specified by the low-order five bits of r b. a mask is generated having 1 bits from bit mb through bit me and 0 bits elsewhere. the rotated data is anded with the generated mask and the result is placed into r a. rlwnm can be used to extract and rotate bit fields using the methods shown as follows: o to extract an n field, that starts at variable bit position b in r s, right-justified into r a (clearing the remaining 32 C n bits of r a), by setting the low-order five bits of r b to b + n, mb = 32 C n, and me = 31. o to extract an n field, that starts at variable bit position b in r s, left-justified into r a (clearing the remaining 32 C n bits of r a), by setting the low-order five bits of r b to b, mb = 0, and me = n C 1. o to rotate the contents of a register left (or right) by n bits, by setting the low-order five bits of r b to n (32 C n), mb = 0, and me = 31. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 23 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field bmbme0
mpc823e instruction setrlwnm motorola mpc823e reference manual b-121 instruction set b other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) simplified mnemonics: rotlw r a ,r s ,r b equivalent to rlwnm a ,r s ,r b ,0,31 powerpc architecture level supervisor level optional form uisa m
mpc823e instruction setsc b-122 mpc823e reference manual motorola instruction set b sc assembler syntax sc definition system call description the sc instruction calls the operating system to perform a service. when control is returned to the program that executed the system call, the content of the registers depends on the register conventions used by the program providing the system service. the effective address of the instruction following the sc instruction is placed into srr0. bits 0, 5-9, and 16-31 of the msr are placed into the corresponding bits of srr1, and bits 1- 4 and 10-15 of srr1 are set to undefined values. an sc exception is generated. the exception alters the msr. the exception causes the next instruction to be fetched from offset 0xc00 from the base real address indicated by the new setting of msr[ip]. other registers altered: o dependent on the system service o srr0 o srr1 o msr bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 17 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000000000000 1 0 powerpc architecture level supervisor level optional form uisa/oea sc
mpc823e instruction setslw motorola mpc823e reference manual b-123 instruction set b slw assembler syntax slw ra,rs,rb (rc = 0) slw. ra,rs,rb (rc = 1) definition shift left word operation n ? r b[27-31] r a ? rotl( r s, n ) description if bit 26 of r b = 0, the contents of r s are shifted left the number of bits specified by r b[27C31]. bits shifted out of position 0 are lost. zeros are supplied to the vacated positions on the right. the 32-bit result is placed into r a. if bit 26 of r b = 1, 32 zeros are placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b24rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setsraw b-124 mpc823e reference manual motorola instruction set b sraw assembler syntax sraw ra,rs,rb (rc = 0) sraw. ra,rs,rb (rc = 1) definition shift right algebraic word operation n ? r b[27-31] ra ? rotl( r s, n ) description if r b[26] = 0,then the contents of r s are shifted right the number of bits specified by r b[27C31]. bits shifted out of position 31 are lost. the result is padded on the left with sign bits before being placed into r a. if r b[26] = 1, then r a is filled with 32 sign bits (bit 0) from r s. cr0 is set based on the value written into r a. xer[ca] is set if r s contains a negative number and any 1 bits are shifted out of position 31; otherwise xer[ca] is cleared. a shift amount of zero causes xer[ca] to be cleared. the sraw instruction, followed by addze , can by used to divide quickly by 2 n . the setting of the xer[ca] bit, by sraw , is independent of mode. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so(if rc = 1) o xer: affected: ca bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 792 rc
mpc823e instruction setsrawi motorola mpc823e reference manual b-125 instruction set b srawi assembler syntax srawi ra,rs,sh (rc = 0) srawi. ra,rs,sh (rc = 1) definition shift right algebraic word immediate operation n ? sh r ? rotl( r s, 32 C n ) description the contents of r s are shifted right the number of bits specified by operand sh. bits shifted out of position 31 are lost. the shifted value is sign-extended before being placed in r a. the 32-bit result is placed into r a. xer[ca] is set if r s contains a negative number and any 1 bits are shifted out of position 31; otherwise xer[ca] is cleared. a shift amount of zero causes xer[ca] to be cleared. the srawi instruction, followed by addze , can be used to divide quickly by 2 n . the setting of the ca bit, by srawi , is independent of mode. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) o xer: affected: ca bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field sh 824 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setsrw b-126 mpc823e reference manual motorola instruction set b srw assembler syntax srw ra,rs,rb (rc = 0) srw. ra,rs,rb (rc = 1) definition shift right word operation n ? r b[27-31] r ? rotl( r s, 32 C n ) description the contents of r s are shifted right the number of bits specified by the low-order six bits of r b. bits shifted out of position 31 are lost. zeros are supplied to the vacated positions on the left. the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 536 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstb motorola mpc823e reference manual b-127 instruction set b stb assembler syntax stb rs,d(ra) definition store byte operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) mem(ea, 1) ? r s[24-31] description ea is the sum ( r a|0) + d. the contents of the low-order eight bits of r s are stored into the byte in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 38 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setstbu b-128 mpc823e reference manual motorola instruction set b stbu assembler syntax stbu rs,d(ra) definition store byte with update operation ea ? ( r a) + exts(d) mem(ea, 1) ? r s[24-31] r a ? ea description ea is the sum ( r a) + d. the contents of the low-order eight bits of r s are stored into the byte in memory addressed by ea. ea is placed into r a. if r a = 0, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 39 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setstbux motorola mpc823e reference manual b-129 instruction set b stbux assembler syntax stbux rs,ra,rb definition store byte with update indexed operation ea ? ( r a) + ( r b) mem(ea, 1) ? r s[24-31] r a ? ea description ea is the sum ( r a) + ( r b). the contents of the low-order eight bits of r s are stored into the byte in memory addressed by ea. ea is placed into r a. if r a = 0, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 247 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstbx b-130 mpc823e reference manual motorola instruction set b stbx assembler syntax stbx rs,ra,rb definition store byte indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) mem(ea, 1) ? r s[24-31] description ea is the sum ( r a|0) + ( r b). the contents of the low-order eight bits of r s are stored into the byte in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 215 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setsth motorola mpc823e reference manual b-131 instruction set b sth assembler syntax sth rs,d(ra) definition store half word operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) mem(ea, 2) ? r s[16-31] description ea is the sum ( r a|0) + d. the contents of the low-order 16 bits of r s are stored into the half word in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 44 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setsthbrx b-132 mpc823e reference manual motorola instruction set b sthbrx assembler syntax sthbrx rs,ra,rb definition store half word byte-reverse indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) mem(ea, 2) ? r s[24-31] || r s[16-23] description ea is the sum ( r a|0) + ( r b). the contents of the low-order eight bits of r s are stored into bits 0C7 of the half word in memory addressed by ea. the contents of the subsequent low-order eight bits of r s are stored into bits 8C15 of the half word in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 918 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setsthu motorola mpc823e reference manual b-133 instruction set b sthu assembler syntax sthu rs,d(ra) definition store half word with update operation ea ? (r a) + exts(d) mem(ea, 2) ? r s[16-31] r a ? ea description ea is the sum ( r a) + d. the contents of the low-order 16 bits of r s are stored into the half word in memory addressed by ea. ea is placed into r a. if r a = 0, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 45 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setsthux b-134 mpc823e reference manual motorola instruction set b sthux assembler syntax sthux rs,ra,rb definition store half word with update indexed operation ea ? ( r a) + ( r b) mem(ea, 2) ? r s[16-31] r a ? ea description ea is the sum ( r a) + ( r b). the contents of the low-order 16 bits of r s are stored into the half word in memory addressed by ea. ea is placed into r a. if r a = 0, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 439 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setsthx motorola mpc823e reference manual b-135 instruction set b sthx assembler syntax sthx rs,ra,rb definition store half word indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) mem(ea, 2) ? r s[16-31] description ea is the sum ( r a|0) + ( r b). the contents of the low-order 16 bits of r s are stored into the half word in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 407 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstmw b-136 mpc823e reference manual motorola instruction set b stmw assembler syntax stmw rs,d(ra) definition store multiple word operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) r ? r s do while r 31 mem(ea, 4) ? gpr(r) r ? r + 1 ea ? ea + 4 description ea is the sum ( r a|0) + d. n = (32 C r s). n consecutive words starting at ea are stored from the gprs r s through r31 . for example, if r s = 30, 2 words are stored. ea must be a multiple of four. if it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. note that this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 47 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setstswi motorola mpc823e reference manual b-137 instruction set b stswi assembler syntax stswi rs,ra,nb definition store string word immediate operation if r a = 0 then ea ? 0 else ea ? ( r a) if nb = 0 then n ? 32 else n ? nb r ? r s C 1 i ? 32 do while n > 0 if i = 32 then r ? r + 1 (mod 32) mem(ea, 1) ? gpr(r)[iCi + 7] i ? i + 8 if i = 64 then i ? 32 ea ? ea + 1 n ? n C 1 description ea is ( r a|0). let n = nb if nb 1 0, n = 32 if nb = 0; n is the number of bytes to store. let nr = ceil( n ? 4); nr is the number of registers to supply data. n consecutive bytes starting at ea are stored from gprs r s through r s + nr C 1. bytes are stored left to right from each register. the sequence of registers wraps around through r0 if required. under certain conditions (like segment boundary crossing), the data alignment exception handler may be invoked. in some implementations, this instruction is likely to have a greater latency and take longer to execute than a sequence of individual load or store instructions that produce the same results. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field nb 725 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstswx b-138 mpc823e reference manual motorola instruction set b stswx assembler syntax stswx r s, r a, r b definition store string word indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) n ? xer[25C31] r ? r s C 1 i ? 32 do while n > 0 if i = 32 then r ? r + 1 (mod 32) mem(ea, 1) ? gpr(r)[iCi + 7] i ? i + 8 if i = 64 then i ? 32 ea ? ea + 1 n ? n C 1 description ea is the sum ( r a|0) + ( r b). let n = xer[25C31]; n is the number of bytes to store. let nr = ceil( n ? 4); nr is the number of registers to supply data. n consecutive bytes starting at ea are stored from gprs r s through r s + nr C 1. bytes are stored left to right from each register. the sequence of registers wraps around through r0 if required. if n = 0, no bytes are stored. under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 861 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstw motorola mpc823e reference manual b-139 instruction set b stw assembler syntax stw rs,d(ra) definition store word operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + exts(d) mem(ea, 4) ? r s description ea is the sum ( r a|0) + d. the contents of r s are stored into the word in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 36 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setstwbrx b-140 mpc823e reference manual motorola instruction set b stwbrx assembler syntax stwbrx rs,ra,rb definition store word byte-reverse indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) mem(ea, 4) ? r s[24-31] || r s[16-23] || r s[8-15] || r s[0-7] description ea is the sum ( r a|0) + ( r b). the contents of the low-order eight bits of r s are stored into bits 0C7 of the word in memory addressed by ea. the contents of the subsequent eight low- order bits of r s are stored into bits 8C15 of the word in memory addressed by ea. the contents of the subsequent eight low- order bits of r s are stored into bits 16C23 of the word in memory addressed by ea. the contents of the subsequent eight low- order bits of r s are stored into bits 24C31 of the word in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 662 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstwcx. motorola mpc823e reference manual b-141 instruction set b stwcx. assembler syntax stwcx. rs,ra,rb definition store word conditional indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) if reserve then if reserve_addr = physical_addr(ea) mem(ea, 4) ? r s cr0 ? 0b00 || 0b1 || xer[so] else u ? undefined 1-bit value if u then mem(ea, 4) ? r s cr0 ? 0b00 || u || xer[so] reserve ? 0 else cr0 ? 0b00 || 0b0 || xer[so] description ea is the sum ( r a|0) + ( r b). if the reserved bit is set, the stwcx. instruction stores r s to effective address ( r a + r b), clears the reserved bit, and sets cr0[eq]. if the reserved bit is not set, the stwcx. instruction does not do a store; it leaves the reserved bit cleared and clears cr0[eq]. software must look at cr0[eq] to see if the stwcx. was successful. the reserved bit is set by the lwarx instruction. the reserved bit is cleared by any stwcx. instruction to any address, and also by snooping logic if it detects that another processor does any kind of store to the block indicated in the reservation buffer when reserved is set. if a reservation exists, and the memory address specified by the stwcx. instruction is the same as that specified by the load and reserve instruction that established the reservation, the contents of r s are stored into the word in memory addressed by ea and the reservation is cleared. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 150 1
mpc823e instruction setstwcx. b-142 mpc823e reference manual motorola instruction set b if a reservation exists, but the memory address specified by the stwcx. instruction is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the contents of r s are stored into the word in memory addressed by ea. if no reservation exists, the instruction completes without altering memory. the cr0 field is set to reflect whether the store operation was performed as follows. cr0[lt gt eq s0] = 0b00 || store_performed || xer[so] ea must be a multiple of four. if it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. the granularity with which reservations are managed is implementation-dependent . therefore, the memory to be accessed by the load and reserve and store conditional instructions should be allocated by a system library program. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstwu motorola mpc823e reference manual b-143 instruction set b stwu assembler syntax stwu rs,d(ra) definition store word with update operation ea ? ( r a) + exts(d) mem(ea, 4) ? r s r a ? ea description ea is the sum ( r a) + d. the contents of r s are stored into the word in memory addressed by ea. ea is placed into r a. if r a = 0, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 37 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setstwux b-144 mpc823e reference manual motorola instruction set b stwux assembler syntax stwux rs,ra,rb definition store word with update indexed operation ea ? ( r a) + ( r b) mem(ea, 4) ? r s r a ? ea description ea is the sum ( r a) + ( r b). the contents of r s are stored into the word in memory addressed by ea. ea is placed into r a. if r a = 0, the instruction form is invalid. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 183 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setstwx motorola mpc823e reference manual b-145 instruction set b stwx assembler syntax stwx rs,ra,rb definition store word indexed operation if r a = 0 then b ? 0 else b ? ( r a) ea ? b + ( r b) mem(ea, 4) ? r s description ea is the sum ( r a|0) + ( r b). the contents of r s are is stored into the word in memory addressed by ea. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 151 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setsubf b-146 mpc823e reference manual motorola instruction set b subf assembler syntax subf rd,ra,rb (oe = 0 rc = 0) subf. rd,ra,rb (oe = 0 rc = 1) subfo rd,ra,rb (oe = 1 rc = 0) subfo. rd,ra,rb (oe = 1 rc = 1) definition subtract from operation r d ? ? ( r a) + ( r b) + 1 description the sum ? ( r a) + ( r b) + 1 is placed into r d. the subf instruction is preferred for subtraction because it sets few status bits. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) o xer: affected: so, ov (if oe = 1) simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field boe 40 rc sub r d ,r a ,r b equivalent to subf r d ,r b ,r a powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setsubfc motorola mpc823e reference manual b-147 instruction set b subfc assembler syntax subfc rd,ra,rb (oe = 0 rc = 0) subfc. rd,ra,rb (oe = 0 rc = 1) subfco rd,ra,rb (oe = 1 rc = 0) subfco. rd,ra,rb (oe = 1 rc = 1) definition subtract from carrying operation r d ? ? ( r a) + ( r b) + 1 description the sum ? ( r a) + ( r b) + 1 is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field boe 8 rc subc r d ,r a ,r b equivalent to subfc r d ,r b ,r a powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setsubfe b-148 mpc823e reference manual motorola instruction set b subfe assembler syntax subfe rd,ra,rb (oe = 0 rc = 0) subfe. rd,ra,rb (oe = 0 rc = 1) subfeo rd,ra,rb (oe = 1 rc = 0) subfeo. rd,ra,rb (oe = 1 rc = 1) definition subtract from extended operation r d ? ? ( r a) + ( r b) + xer[ca] description the sum ? ( r a) + ( r b) + xer[ca] is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b oe 136 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setsubfic motorola mpc823e reference manual b-149 instruction set b subfic assembler syntax subfic rd,ra,simm definition subtract from immediate carrying operation r d ? ? ( r a) + exts(simm) + 1 description the sum ? ( r a) + exts(simm) + 1 is placed into r d. other registers altered: o xer: affected: ca bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 08 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setsubfme b-150 mpc823e reference manual motorola instruction set b subfme assembler syntax subfme rd,ra (oe = 0 rc = 0) subfme. rd,ra (oe = 0 rc = 1) subfmeo rd,ra (oe = 1 rc = 0) subfmeo. rd,ra (oe = 1 rc = 1) definition subtract from minus one extended operation r d ? ? ( r a) + xer[ca] C 1 description the sum ? ( r a) + xer[ca] + (32)1 is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so(if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 oe 232 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setsubfze motorola mpc823e reference manual b-151 instruction set b subfze assembler syntax subfze rd,ra (oe = 0 rc = 0) subfze. rd,ra (oe = 0 rc = 1) subfzeo rd,ra (oe = 1 rc = 0) subfzeo. rd,ra (oe = 1 rc = 1) definition subtract from zero extended operation r d ? ? ( r a) + xer[ca] description the sum ? ( r a) + xer[ca] is placed into r d. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) the cr0 field may not reflect the true (infinitely precise) result if overflow occurs (see xer below). o xer: affected: ca affected: so, ov (if oe = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 d a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 oe 200 rc powerpc architecture level supervisor level optional form uisa xo
mpc823e instruction setsync b-152 mpc823e reference manual motorola instruction set b sync assembler syntax sync definition synchronize description the sync instruction provides an ordering function for the effects of all instructions executed by a given processor. executing a sync instruction ensures that all instructions preceding the sync instruction appear to have completed before the sync instruction completes, and that no subsequent instructions are initiated by the processor until after the sync instruction completes. when the sync instruction completes, all external accesses caused by instructions preceding the sync instruction will have been performed with respect to all other mechanisms that access memory. multiprocessor implementations also send a sync address-only broadcast that is useful in some designs. for example, if a design has an external buffer that reorders loads and stores for better bus efficiency, the sync broadcast signals to that buffer that previous loads/stores must be completed before any following loads/stores. the sync instruction can be used to ensure that the results of all stores into a data structure, caused by store instructions executed in a critical section of a program, are seen by other processors before the data structure is seen as unlocked. the functions performed by the sync instruction will normally take a significant amount of time to complete, so indiscriminate use of this instruction may adversely affect performance. in addition, the time required to execute sync may vary from one execution to another. the eieio instruction may be more appropriate than sync for many cases. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 598 0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction settlbia motorola mpc823e reference manual b-153 instruction set b tlbia assembler syntax tlbia definition translation lookaside buffer invalidate all operation all tlb entries ? invalid description the entire translation lookaside buffer (tlb) is invalidated (that is, all entries are removed). the tlb is invalidated regardless of the settings of msr[ir] and msr[dr]. the invalidation is done without reference to the slb, segment table, or segment registers. this instruction does not cause the entries to be invalidated in other processors. this is a supervisor-level instructon. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 370 0 powerpc architecture level supervisor level optional form oea ?? x
mpc823e instruction settlbie b-154 mpc823e reference manual motorola instruction set b tlbie assembler syntax tlbie rb definition translation lookaside buffer invalidate entry operation vps ? r b[4-19] identify tlb entries corresponding to vps each such tlb entry ? invalid description ea is the contents of r b. if the translation lookaside buffer (tlb) contains an entry corresponding to ea, that entry is made invalid (that is, removed from the tlb). multiprocessing implementations (for example, the 601, and 604) send a tlbie address-only broadcast over the address bus to tell other processors to invalidate the same tlb entry in their tlbs. the tlb search is done regardless of the settings of msr[ir] and msr[dr]. the search is done based on a portion of the logical page number within a segment, without reference to the segment registers. all entries matching the search criteria are invalidated. block address translation for ea, if any, is ignored. this is a supervisor-level instruction. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 30k6 0 powerpc architecture level supervisor level optional form oea ?? x
mpc823e instruction settlbsync motorola mpc823e reference manual b-155 instruction set b tlbsync assembler syntax tlbsync definition tlb synchronize description if an implementation sends a broadcast for tlbie then it will also send a broadcast for tlbsync . executing a tlbsync instruction ensures that all tlbie instructions previously executed by the processor executing the tlbsync instruction have completed on all other processors. the operation performed by this instruction is treated as a caching-inhibited and guarded data access with respect to the ordering done by eieio . this instruction is supervisor-level. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 00000 00000 bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field 00000 566 0 powerpc architecture level supervisor level optional form oea ?? x
mpc823e instruction settw b-156 mpc823e reference manual motorola instruction set b tw assembler syntax tw to,ra,rb definition trap word operation a ? exts( r a) b ? exts( r b) if (a < b) & to[0] then trap if (a > b) & to[1] then trap if (a = b) & to[2] then trap if (a u b) & to[4] then trap description the contents of r a are compared with the contents of r b. if any bit in the to field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. other registers altered: o none simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 to a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b40 tweq r a ,r b equivalent to tw 4,r a ,r b twlge r a ,r b equivalent to tw 5,r a ,r b trap equivalent to tw 31,0,0 powerpc architecture level supervisor level optional form uisa x
mpc823e instruction settwi motorola mpc823e reference manual b-157 instruction set b twi assembler syntax twi to,ra,simm definition trap word immediate operation a ? exts( r a) if (a < exts(simm)) & to[0] then trap if (a > exts(simm)) & to[1] then trap if (a = exts(simm)) & to[2] then trap if (a u exts(simm)) & to[4] then trap description the contents of r a are compared with the sign-extended value of the simm field. if any bit in the to field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. other registers altered: o none simplified mnemonics: bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 03 to a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field simm twgti r a , value equivalent to twi 8,r a , value twllei r a , value equivalent to twi 6,r a , value powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setxor b-158 mpc823e reference manual motorola instruction set b xor assembler syntax xor ra,rs,rb (rc = 0) xor. ra,rs,rb (rc = 1) definition xor operation r a ? ( r s) ? ( r b) description the contents of r s is xored with the contents of r b and the result is placed into r a. other registers altered: o condition register (cr0 field): affected: lt, gt, eq, so (if rc = 1) bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 31 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field b 316 rc powerpc architecture level supervisor level optional form uisa x
mpc823e instruction setxori motorola mpc823e reference manual b-159 instruction set b xori assembler syntax xori ra,rs,uimm definition xor immediate operation r a ? ( r s) ? ((16)0 || uimm) description the contents of r s are xored with 0x0000 || uimm and the result is placed into r a. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 26 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm powerpc architecture level supervisor level optional form uisa d
mpc823e instruction setxoris b-160 mpc823e reference manual motorola instruction set b xoris assembler syntax xoris ra,rs,uimm definition xor immediate shifted operation r a ? ( r s) ? (uimm || (16)0) description the contents of r s are xored with uimm || 0x0000 and the result is placed into r a. other registers altered: o none bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field 27 s a bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field uimm powerpc architecture level supervisor level optional form uisa d
motorola mpc823e reference manual index-1 index a access, restricting, 15-5 acronyms (defined), 24-1 address bus, 13-32 address field, 16-273 address multiplexing, 15-60 address translation, 11-2 ale_b, 2-7 algorithm, risc timer table, 16-25 apg (definition), 11-4 appletalk (localtalk), 16-265 applications, 1-11 arbitration, 13-27 architecture memory controller, 15-4 architecture, powerpc, 7-1 as, 2-6 asid (definition), 11-2 async hdlc mode, 16-269 asynchronous bus masters, 15-66 , 15-68 asynchronous mode, 16-203 at0, 2-8 at1, 2-7 at2, 2-7 at3, 2-8 atomic transaction, 13-16 atomic update primitives, 7-4 autobaud operation, 16-159 autobuffer, 16-91 b back trace, 20-6 bar, 6-17 , 20-44 base registers, 15-9 battery preservation, 5-24 baud rate generator clock frequency, 5-20 baud rate generators 16-157 block diagram, 16-157 configuration register (brgcx), 16-160 features, 16-157 memory map, 3-8 uart examples, 16-162 baud rates, typical, 16-162 bb, 2-4 , 13-7 , 13-29 bd (definition), 16-178 bdip, 2-2 , 13-5 , 13-36 bg, 2-4 , 13-7 , 13-29 bi, 2-3 , 13-6 , 13-36 big-endian sdma, 16-83 bit assignments control registers, 6-20 bit-stuffing (definition), 16-233 blank, 2-12 block diagram clocks, 5-11 core, 6-3 spll, 5-12 block diagrams baud rate generators, 16-157 communication processor module, 16-3 data cache, 10-2 dpll receive, 16-194 dpll transmit, 16-194 i2c controller, 16-456 ieee 1149.1 test access port, 21-2 instruction cache, 9-3 lcd controller, 18-7 memory controller, 15-3 memory periodic timer request, 15-42 mpc823e, 1-7 parallel i/o port pa14, 16-483 parallel i/o port pa15, 16-482 periodic interrupt timer, 12-22 real-time clock, 12-17 risc microcontroller, 16-5 serial communication controllers, 16-164 serial interface, 16-113 serial management controllers, 16-383 serial peripheral interface, 16-434 software watchdog timer, 12-27 timers cascaded mode, 16-76 timers, 16-74 video controller, 19-3 boot rom, locating, 15-37 boundary scan bit definitions, 21-7 boundary scan register, 21-4 br, 2-4 , 13-7 , 13-28 branch folding, 6-5 branch instructions, predicted and mispredicted, 6- 6
index index-2 mpc823e reference manual motorola branch prediction policy (table), 6-6 branch reservation station, 6-6 breakpoints, 20-9 breaks 16-211 sending, 16-212 brg (definition), 16-157 brgclk divisor, defining, 15-27 brgclk, 5-19 brgcx, 16-160 brgo1, 2-8 , 2-9 brgo2, 2-9 brgo3, 2-9 brgout2, 2-9 bs, 15-56 bs_b0, 2-5 bs_b1, 2-5 bs_b2, 2-5 bs_b3, 2-5 buffer chaining, 16-91 buffer descriptor ring usb, 16-375 buffer descriptors i2c controller receive, 16-469 transmit, 16-471 idma, 16-96 sccx in async hdlc mode receive, 16-280 transmit, 16-282 sccx in ethernet mode receive, 16-340 transmit, 16-343 sccx in hdlc mode receive, 16-244 transmit, 16-248 sccx in transparent mode receive, 16-310 transmit, 16-312 sccx in uart mode receive, 16-220 transmit, 16-224 sccx, 16-178 serial management controllers, 16-384 serial peripheral interface receive, 16-447 transmit, 16-449 smc in transparent mode receive, 16-418 transmit, 16-420 smc in uart mode receive, 16-399 transmit, 16-403 universal serial bus receive, 16-366 transmit, 16-369 burst access, initiated by the mpc823, 13-45 burst mechanism, 13-16 burst show cycle, 13-33 burst, 2-2 , 13-4 , 13-32 bus arbitration and transfers, 16-84 bus bandwidth utilization, minimizing, 10-11 bus busy, 13-29 bus cycle access, requesting, 15-8 bus exceptions, 16-112 bus grant, 13-29 bus interface features, 13-1 operation address transfer phase signals, 13-31 arbitration phase signals, 13-27 basic transfers, 13-8 burst mechanism, 13-16 burst transfers, 13-16 data transfer phase signals, 13-36 exception control cycles, 13-41 single beat transfers, 13-8 storage reservation, 13-38 termination signals, 13-36 transfer alignment and packaging, 13-25 operation, 13-7 signal descriptions, 13-4 transfer signals, 13-1 bus interface, 13-1 bus master support, 15-68 bus master, becoming, 13-27 bus monitor, 12-11 bus request, 13-28 bus signals (illustration), 13-3 byte selects, enabling, 15-57 c c/i (definition), 16-150 cache coherency, 9-14 , 10-13 cache hit, 9-1 , 9-7 cache inhibit, 11-4 cache miss, 9-1 , 9-8 cascaded mode, 16-76 casid (definition), 11-2 cd2, 2-10 cd3, 2-11 ce1_b, 2-4 ce2_b, 2-5 channel reception smc in gci mode (c/i), 16-426 smc in gci mode (monitor), 16-426 channel transmission smc in gci mode (c/i), 16-426 smc in gci mode (monitor), 16-426
index motorola mpc823e reference manual index-3 checkstop state, 7-9 chip-select logic updating code and programming memory regions, 9-14 cicr, 16-507 cimr, 16-510 cipr, 16-509 cisr, 16-511 civr, 16-512 clk, 2-12 clk1, 2-8 clk2, 2-8 clk3, 2-9 clk4, 2-9 clkout, 2-6 , 5-16 , 5-19 clock glitches, 16-197 clock input to the prescaler, 16-158 clock operation, 5-10 clock skew, 13-7 clock source and configuration options, determining, 5-22 clock source and distribution (illustration), 5-2 clock, of the video controller, 19-3 clock, spll reference, 5-12 clocks block diagram, 5-11 configuration, 5-22 internal clock signals baud rate generator clock, 5-19 general system clocks, 5-16 lcd clocks, 5-21 synchronization clocks, 5-20 internal clock signals, 5-16 keys memory map, 3-4 low-power divider, 5-14 memory map, 3-3 operation oscillators and external clock input, 5-12 system pll block diagram, 5-12 system pll, 5-12 operation, 5-10 registers, 5-3 timing, 15-44 clocks and power control features, 5-1 clocks and power control, 5-1 cmpa-d, 20-42 cmpax, 6-17 cmpe-f, 20-43 cmpg-h, 20-44 coding, 16-196 collisions, 16-266 , 16-335 color ram, 18-12 command 15-40 commands arm idma, 16-11 arm_idma, 16-100 cache disable, 9-11 cache enable, 9-11 cache line flush, 10-13 close rx bd, 16-11 , 16-208 , 16-240 , 16- 278 , 16-308 , 16-331 , 16-396 , 16-415 , 16- 441 , 16-466 copyback, 10-13 data cache disable, 10-13 data cache enable, 10-13 data cache, 10-13 debug port, 20-38 dsp, 16-32 end download procedure, 20-40 endpoint, 16-363 enter hunt mode, 16-11 , 16-207 , 16- 240 , 16-278 , 16-308 , 16-331 , 16-396 , 16- 415 flg, 16-364 gci abort request, 16-11 gci timeout, 16-11 graceful stop transmit, 16-207 , 16- 239 , 16-277 , 16-308 , 16-331 graceful stop tx, 16-11 i2c controller, 16-466 idma, 16-100 init dsp chain, 16-32 init dsp, 16-11 init idma, 16-11 init rx and tx params, 16-11 init rx parameters, 16-208 , 16-240 , 16- 278 , 16-308 , 16-331 , 16-396 , 16-415 , 16- 441 , 16-466 init rx params, 16-11 init tx and rx parameters, 16-430 init tx parameters, 16-207 , 16-239 , 16- 277 , 16-308 , 16-331 , 16-396 , 16-415 , 16- 441 , 16-466 init tx params, 16-11 init_idma, 16-100 instruction cache block invalidate, 9-9 instruction cache, 9-8 invalidate all, 9-9 , 10-13 load & lock, 9-10 lock line, 10-13 restart transmit, 16-207 , 16-239 , 16- 277 , 16-308 , 16-331 , 16-396 , 16-415 restart tx, 16-11 risc microcontroller, 16-9 , 16-11 rst, 16-363 run, 15-18 , 15-40 sccx in async hdlc mode, 16-277
index index-4 mpc823e reference manual motorola sccx in ethernet mode, 16-330 sccx in hdlc mode, 16-239 sccx in transparent mode, 16-307 sccx in uart mode, 16-207 serial peripheral interface, 16-441 set group address, 16-11 , 16-332 set timer, 16-11 , 16-22 smc in gci mode, 16-430 smc in transparent mode, 16-415 smc in uart mode, 16-396 start download procedure, 20-40 start dsp chain, 16-32 start dsp, 16-11 stop idma, 16-11 stop transmit, 16-207 , 16-239 , 16-277 , 16-307 , 16-330 , 16-396 , 16-415 stop tx, 16-11 stop_idma, 16-100 timeout, 16-430 transmit abort request, 16-430 universal serial bus, 16-363 unlock all, 9-11 , 10-13 unlock line, 9-10 , 10-13 usb, 16-11 usbcmd, 16-363 write, 15-77 , 15-89 communication processor module baud rate generator clock, 5-19 baud rate generators autobaud operation, 16-159 block diagram, 16-157 configuration registers, 16-160 features, 16-157 uart baud rate examples, 16-162 baud rate generators, 16-157 block diagram, 16-3 commands cpm command register example, 16-13 cpm interrupt controller 16-499 features, 16-501 interrupt examples pc6, 16-512 usb, 16-513 interrupt examples, 16-512 interrupt vectors, 16-505 masking interrupt sources, 16-504 operation, 16-499 programming, 16-507 registers interrupt configuration, 16-507 interrupt in-service, 16-511 interrupt mask, 16-510 interrupt pending, 16-509 interrupt vector, 16-512 source priorities, 16-501 structure (illustration), 16-500 digital signal processing commands, 16-32 demod, 16-62 execution times, 16-73 features, 16-26 fir1, 16-39 fir2, 16-42 fir3, 16-46 fir5, 16-50 fir6, 16-54 iir, 16-57 lms1, 16-65 lms2, 16-67 mod, 16-60 programming, 16-27 wadd, 16-70 digital signal processing, 16-26 features, 16-1 i2c controller 16-456 block diagram, 16-456 buffer descriptor ring, 16-467 commands, 16-466 features, 16-457 operation, 16-457 parameter ram memory map, 16-463 programming, 16-468 receive buffer descriptor, 16-469 registers, 16-468 transmission and reception, 16-458 transmit buffer descriptor, 16-471 idma emulation buffer descriptors, 16-96 commands, 16-100 interface signals, 16-90 operation, 16-90 parameter ram memory map, 16-92 idma emulation, 16-89 memory map, 3-7 parallel i/o ports 16-477 features, 16-478 port a example configuration, 16-482 operation, 16-478 pins, 16-479 registers, 16-480 port b configuration example, 16-490 operation, 16-484 registers, 16-485 port c pins, 16-490
index motorola mpc823e reference manual index-5 registers, 16-492 port d operation, 16-497 registers, 16-498 risc microcontroller block diagram, 16-5 commands, 16-9 , 16-11 configuration register (rccr), 16-7 core interface, 16-6 features, 16-5 microcode development support control register (rmds), 16-7 microcode, 16-7 risc microcontroller, 16-4 sdma channels bus arbitration and transfers, 16-84 sdma channels, 16-82 serial communication controller async hdlc mode registers, 16-279 serial communication controllers appletalk mode features, 16-266 programming examples, 16-269 programming, 16-268 async hdlc mode commands, 16-277 configuration, 16-276 errors, 16-278 parameter ram memory map, 16-274 programming, 16-279 receive buffer descriptors, 16-280 transmit buffer descriptor, 16-282 asynchronous hdlc mode 16-269 block diagram, 16-164 buffer descriptors, 16-178 clock glitches, 16-197 data synchronization register, 16-177 digital phase-locked loop, 16-193 disabling on-the-fly, 16-199 dpll and serial infra-red encoder/decoder, 16-198 dpll receive block diagram, 16-194 dpll transmit block diagram, 16-194 ethernet mode 16-318 commands, 16-330 configuration, 16-330 errors, 16-336 features, 16-319 operation, 16-319 parameter ram memory map, 16-326 programming example, 16-348 receive buffer descriptor, 16-340 registers, 16-337 transmit buffer descriptor, 16-343 features, 16-165 general sccx mode registers, 16-166 hdlc bus controller features, 16-259 hdlc bus controller, 16-257 hdlc mode commands, 16-239 errors, 16-240 features, 16-234 parameter ram memory map, 16-236 programming, 16-238 receive buffer descriptors, 16-244 registers, 16-242 transmit buffer descriptor, 16-248 hdlc mode, 16-233 initialization, 16-188 interrupts, 16-187 irda mode examples, 16-297 high-speed, 16-290 low-speed, 16-288 middle-speed, 16-289 registers, 16-294 irda mode, 16-287 parameter ram memory map, 16-182 sccx in appletalk mode 16-265 sccx in async hdlc mode features, 16-269 sccx in hdlc mode features, 16-234 sccx in hdlc mode, 16-233 timing control, 16-189 transmit-on-demand register, 16-177 transparent mode 16-301 commands, 16-307 errors, 16-309 examples, 16-317 features, 16-302 operation, 16-301 parameter ram memory map, 16-307 receive buffer descriptors, 16-310 registers, 16-309 transmit buffer descriptors, 16-312 uart mode commands, 16-207 errors, 16-214 features, 16-202 programming, 16-206 receive buffer descriptors, 16-220 registers, 16-217 transmit buffer descriptors, 16-224
index index-6 mpc823e reference manual motorola uart mode, 16-201 serial communication controllers, 16-163 serial interface with time-slot assigner block diagram, 16-113 configuration, 16-114 connections, 16-117 features, 16-114 general circuit interface, 16-150 idl interface, 16-144 nmsi configuration, 16-154 ram operation, 16-117 registers, 16-128 serial interface with time-slot assigner, 16-112 serial management controllers block diagram, 16-383 buffer descriptors operation, 16-384 disabling on-the-fly, 16-390 features, 16-384 gci mode 16-425 commands, 16-430 features, 16-425 parameter ram memory map, 16-427 registers, 16-431 general smc mode register, 16-384 operation, 16-382 transparent mode 16-409 commands, 16-415 errors, 16-416 features, 16-409 interrupts, 16-425 nmsi programming example, 16-423 parameter ram memory map, 16-415 receive buffer descriptor, 16-418 registers, 16-416 transmit buffer descriptor, 16-420 tsa programming example, 16-424 uart mode commands, 16-396 errors, 16-397 features, 16-393 interrupts, 16-408 parameter ram memory map, 16-394 programming example, 16-407 programming, 16-395 receive buffer descriptor, 16-399 registers, 16-398 transmit buffer descriptor, 16-403 uart mode, 16-392 serial management controllers, 16-382 serial peripheral interface 16-433 block diagram, 16-434 features, 16-434 interrupts, 16-455 master programming example, 16-453 operation, 16-435 parameter ram memory map, 16-438 programming, 16-443 receive buffer descriptor, 16-447 registers, 16-443 slave programming example, 16-454 transmission and reception, 16-436 transmit buffer descriptor, 16-449 synchronization clocks, 5-20 timers block diagram, 16-74 cascaded mode block diagram, 16-76 examples, 16-81 features, 16-74 operation, 16-75 timers, 16-74 universal serial bus buffer descriptor ring, 16-374 command register, 16-372 commands, 16-363 endpoint configuration registers, 16-373 errors, 16-364 event register, 16-376 features, 16-352 initialization example, 16-378 , 16-380 mask register, 16-377 mode register, 16-365 operation, 16-353 parameter ram memory map, 16-358 receive buffer descriptor, 16-366 slave address register, 16-371 status register, 16-377 transmission and reception, 16-355 transmit buffer descriptors, 16-369 universal serial bus, 16-350 communication processor module (cpm), 16-1 communication, with peripherals, 16-6 communication, with the core, 16-6 comparing timer counts, 16-25 condition register, 6-22 configuration clock, 5-22 for pcmcia, 17-1 general-purpose chip-select machine, 15-27 hdlc bus controller, 16-258 memory controller (illustration), 15-5 nmsi, 16-154 page mode dram, 15-76 page mode extended data-out dram, 15-88 port a example, 16-482 port b example, 16-490
index motorola mpc823e reference manual index-7 power-on reset clock (table), 5-13 reset, 4-7 sccx in async hdlc mode, 16-276 sccx in ethernet mode, 16-330 system endian, 14-1 system interface unit, 12-2 tdm with dynamic frames, 16-119 tdm with static frames, 16-118 , 16-120 time-slot assigner, 16-114 upma, 15-19 upmb, 15-22 connecting mpc823 to external peripheral, 15-31 connecting the mpc823 to an sram device, 15-38 connecting the mpc823 to memory device, 15-29 connecting the mpc823 to static ram memory, 15- 38 connecting upm ram array to dram, 15-76 connections irda, 16-198 sccx in appletalk mode, 16-267 to the time-slot assigner, 16-117 control byte, 16-265 control field, 16-273 control frames, 16-265 copyback mode, 10-11 core basic instruction pipeline, 6-4 basic structure, 6-2 block diagram, 6-3 features, 6-1 instruction flow, 6-2 register unit control registers, 6-16 register unit, 6-15 sequencer unit external interrupt, 6-13 flow control, 6-5 interrrupt ordering, 6-14 interrupt processing, 6-11 interrupts, 6-7 issuing instructions, 6-6 precise exception model, 6-8 serialization, 6-12 sequencer unit, 6-4 core, 6-1 cost, reduction, 5-12 counta, 20-53 countb, 20-54 cpcr, 16-9 cpm command register, 16-9 cpm interrupt controller 16-499 configuration register (cicr), 16-507 features, 16-501 in-service register (cisr), 16-511 interrupt mask register (cimr), 16-510 interrupt pending register (cipr), 16-509 interrupt structure (illustration), 16-500 interrupt vector register (civr), 16-512 interrupt vectors encoding, 16-506 interrupt vectors, 16-505 interrupts, 16-512 masking interrupts, 16-504 operation, 16-499 pc6 example, 16-512 programming, 16-507 source priorities highest priority interrupt, 16-502 nested interrupts, 16-504 usb and scc2 relative priority, 16-502 source priorities, 16-501 usb example, 16-513 cpm, 16-1 cr, 6-19 , 6-22 crc (definition), 16-233 cs output configurations, 15-29 cs, 15-55 cs2, 2-6 cs3, 2-6 cs6, 2-4 cs7, 2-5 csma/cd, 16-318 cts2, 2-10 cts3, 2-9 , 2-11 cycle types, 15-41 cyclic redundancy check, 16-233 d dar, 6-16 , 7-10 data cache block diagram, 10-2 cache-inhibited accesses, 10-12 coherency, 10-13 commands cache line flush, 10-13 copyback, 10-13 data cache disable, 10-13 data cache enable, 10-13 invalidate all, 10-13 lock line, 10-13 unlock all, 10-13 unlock line, 10-13 commands, 10-13 data path block diagram, 10-3 debug support, 10-12 features, 10-1 freeze, 10-12 how to enable and disable, 10-13
index index-8 mpc823e reference manual motorola implementation-specific operations, 10-4 instructions, 10-3 , 10-14 operation, 10-10 organization, 10-2 programming, 10-3 read, 10-10 reading, 10-14 registers special, 10-4 write, 10-10 data cache address register, 10-7 data cache control and status register, 10-5 data cache, 10-1 data cache, how to flush and invalidate, 10-13 data sampling, 15-64 dc_adr, 10-7 dc_cst, 10-5 dcbf, 10-14 , 11-48 dcbi, 10-14 , 11-48 dcbst, 10-14 , 11-48 dcbt, 10-14 dcbtst, 10-14 dcbz, 10-14 , 11-48 debug mode entering, 20-26 dec, 6-16 , 12-13 decoding data, with a dpll, 16-196 decrementer register, 12-13 decrementer, 12-12 demod applications, 16-65 function descriptor, 16-63 modulation table, sample data buffers, and agc constants, 16-63 parameter packet, 16-64 demod, 16-62 der, 6-17 , 20-57 development capabilities 20-1 development system interface debug mode support, 20-22 development interface port shift register, 20- 30 development port, 20-29 trap enable control register, 20-31 trap enable mode, 20-22 development system interface, 20-20 features, 20-1 program flow tracking instruction fetch show cycle control, 20-8 operation compressing cancelled instructions, 20- 8 external hardware, 20-5 internal hardware, 20-3 operation, 20-3 program flow tracking, 20-2 programming debug mode registers, 20-55 development port data registers, 20-60 development port registers, 20-42 protecting the registers, 20-41 programming, 20-41 software monitor debugger support freeze indication, 20-41 software monitor debugger support, 20-40 watchpoints and breakpoints examples, 20-13 internal, 20-9 operation, 20-16 watchpoints and breakpoints, 20-8 development port configuration, 4-7 development port, 20-29 dfnh, 5-17 dfnl, 5-17 dialog, 16-266 differences between autobuffer and buffer chaining, 16-96 hdlc and async hdlc, 16-286 differences between mpc823e and mpc823, 1-12 differential manchester, 16-197 digital phase-locked loop, 16-193 digital signal processing, 16-26 disable timer mechanism, 15-43 , 15-64 disabling all modules, 16-199 idle sequence function, 16-215 part of sccx receiver, 16-200 part of sccx transmitter, 16-199 part of smc receiver, 16-392 part of smc transmitter, 16-391 sccs, 16-199 sccx receiver, 16-200 sccx transmitter, 16-199 smc receiver, 16-391 smc transmitter, 16-391 smc, 16-390 dma pcmcia, 17-8 dma controller memory map, 3-5 dma, video controller, 19-4 dp0, 2-3 dp1, 2-3 dp2, 2-4 dp3, 2-4 dpdr, 6-17 , 20-60 dpir, 6-17 dpir/dpdr, 20-30 dpll (definition), 16-193
index motorola mpc823e reference manual index-9 dram bank, sharing access to, 15-72 dram with ras precharge time, 15-64 dram, types, 15-76 dreq1, 2-10 dreq2, 2-10 dreqx, about, 16-90 dsck, 2-7 , 2-12 , 20-29 dsdi, 2-12 , 20-29 dsdo, 2-8 , 2-12 , 20-29 dsisr, 6-16 , 7-10 dsp firmware, 16-27 dsp function descriptors, 16-29 dsp functionality, 16-26 dsp hardware, 16-27 dsp implementation, 16-35 dsp library, 16-38 dsp parameter ram, 16-30 dsp programming example (core and cpm), 16-37 dsp programming example (core), 16-36 dsp software, 16-27 dsr, 16-177 dual-port ram memory map, 3-12 e echo mode (automatic), 16-175 echo mode, 16-115 edge interrupt, 12-7 edge sensitive idma, 16-90 edo (definition), 15-88 eest, 16-321 eieio, 11-52 electrical contention, avoiding, 13-37 electrical information 22-1 dc, 22-4 layout, 22-3 power, 22-2 ratings, 22-1 thermal, 22-2 emulation, idma, 16-89 emulators, 20-1 encoding data, with a dpll, 16-196 encoding, 16-273 endian modes big endian features, 14-5 little endian features, 14-3 operation, 14-2 , 14-5 powerpc little-endian features, 14-5 endian modes, 14-1 errors abort sequence, 16-241 , 16-278 break sequence received, 16-279 break sequence, 16-216 , 16-397 busy, 16-336 , 16-364 carrier sense lost during frame transmission, 16-336 cd lost during character reception, 16-215 cd lost during frame reception, 16-241 , 16- 278 cd lost during message reception, 16-309 control characters, 16-210 crc, 16-242 , 16-279 , 16-337 , 16-364 cts lost during character transmission, 16- 214 cts lost during frame transmission, 16-240 , 16-278 cts lost during message transmission, 16- 309 framing, 16-216 , 16-397 glitches, 16-197 heartbeat, 16-336 idle sequence receive, 16-215 , 16-397 late collision, 16-336 noise, 16-215 nonoctet aligned frame, 16-241 non-octet aligned packet, 16-364 non-octet, 16-337 overrun, 16-215 , 16-241 , 16-278 , 16-309 , 16-336 , 16-364 , 16-397 , 16-416 parity, 16-215 , 16-397 retransmission attempts limit expired, 16-336 sccx in async hdlc mode, 16-278 sccx in ethernet mode, 16-336 sccx in hdlc mode, 16-240 sccx in transparent mode, 16-309 sccx in uart mode, 16-214 smc in transparent mode, 16-416 smc in uart mode, 16-397 sync signals, 16-124 transmit timeout, 16-364 transmit underrun, 16-364 transmitter underrun, 16-240 , 16-309 , 16-336 underrun, 16-416 universal serial bus, 16-364 ethernet introduction to, 16-321 ethernet mode, sccx, 16-318 examples byte-working mode, 20-13 cpm command register, 16-13 cpm interrupt controller pc6, 16-512 usb, 16-513 dpll encoding, 16-196 dsp implementation, 16-35 dsp programming (core and cpm), 16-37
index index-10 mpc823e reference manual motorola dsp programming for core, 16-36 external bus master, 15-72 general circuit interface, 16-153 half-word working mode 1, 20-13 half-word working mode 2, 20-14 hdlc bus controller programming, 16-264 hdlc interrupt event, 16-251 hierarchical bus interface, 15-67 idl interface. 16-149 initializing the risc timers, 16-24 interrupt table handling, 12-11 memory system interface page mode extended data-out, 15-88 page-mode dram, 15-76 memory system interface, 15-76 pcmcia timing, 17-22 port a configuration, 16-482 port b configuration, 16-490 risc timer interrupt handling, 16-25 scc2 in appletalk mode programming, 16-269 scc2 in ethernet mode programming, 16-348 scc2 in high-speed irda mode programming, 16-300 scc2 in low-speed irda mode programming, 16-297 scc2 in middle-speed mode programming, 16- 298 scc2 in transparent mode programming, 16- 317 sccx hdlc receive buffer descriptor, 16-245 sccx in async hdlc mode programming, 16- 286 sccx in ethernet mode receive buffer descriptor, 16-340 sccx in hdlc mode address recognition, 16- 238 sccx in hdlc mode programming, 16-255 , 16-256 sccx in uart mode programming, 16-230 sccx in uart mode s-record programming, 16-232 sccx uart interrupt event, 16-227 sccx uart receive buffer descriptor, 16-221 serial peripheral interface master programming, 16-453 serial peripheral interface slave programming, 16-454 slow device interface, 15-67 smc in transparent mode programming nmsi, 16-423 smc in transparent mode tsa programming, 16-424 smc in uart mode programming, 16-407 smc in uart mode receive buffer descriptor, 16-402 spi with different len values, 16-445 timer initialization, 16-81 translation reload, 11-50 transparent synchronization, 16-306 uart baud rate, 16-162 universal serial bus initialization, 16-378 , 16- 380 video controller programming, 19-19 examples, instruction execution, 8-4 exception control cycles, 13-41 exception handling, 15-59 exception sources, 6-7 exception, causes of, 6-7 exception, detecting an, 6-9 exceptions, 20-28 exceptions, powerpc, 7-2 execution, dsp, 16-73 exiting from low-power mode, 5-28 exs (definition), 15-41 extal, 2-6 extclk, 2-6 external accesses (definition), 15-68 external bus masters, 15-68 external bus, operating at lower frequencies, 5-17 external hard reset, 4-3 external interrupt latency, 6-13 external memory access requests, 15-42 external soft reset, 4-4 f features baud rate generators, 16-157 big endian mode, 14-5 bus interface, 13-1 clocks and power control, 5-1 communication processor module, 16-1 core, 6-1 cpm interrupt controller, 16-501 data cache, 10-1 development capabilities, 20-1 digital signal processing, 16-26 hdlc bus controller, 16-259 i2c controller, 16-457 idma, 16-90 instruction cache, 9-1 lcd controller, 18-1 little endian mode, 14-3 memory controller, 15-1 memory management unit, 11-1 not supported by smc in uart mode, 16-392 parallel i/o ports, 16-478 pcmcia, 17-1 powerpc little-endian mode, 14-5
index motorola mpc823e reference manual index-11 risc microcontroller, 16-5 risc timer tables, 16-17 sccx in appletalk mode, 16-266 sccx in async hdlc mode, 16-269 sccx in ethernet mode, 16-319 sccx in hdlc mode, 16-234 sccx in transparent mode, 16-302 sccx uart controller, 16-202 serial communication controllers, 16-165 serial interface, 16-114 serial management controllers, 16-384 serial peripheral interface, 16-434 smc in gci mode, 16-425 smc in transparent mode, 16-409 smc in uart mode, 16-393 system interface unit, 12-2 timers, 16-74 universal serial bus, 16-352 video controller, 19-2 fetch serialization, causes of, 6-12 field, 2-11 filter, context-dependent, 20-14 finite impulse response (fir) filter, 16-26 fir (definition), 16-26 fir1 applications, 16-41 coefficients and sample data buffers, 16-39 function descriptor, 16-40 parameter packet, 16-41 fir1, 16-39 fir2 applications, 16-45 coefficients and sample data buffers, 16-42 function descriptor, 16-43 parameter packet, 16-45 fir3 applications, 16-49 coefficients and sample data buffers, 16-47 function descriptor, 16-47 parameter ram, 16-49 fir3, 16-46 fir5 applications, 16-53 coefficients and sample data buffers, 16-50 function descriptor, 16-51 parameter ram, 16-53 fir5, 16-50 fir6 coefficients and sample data buffers, 16-54 function descriptor, 16-55 parameter packet, 16-57 fir6, 16-54 fixed-point exception cause register, 6-23 flag sequence, 16-273 fly-by mode, 16-103 fm0, 16-196 fm1, 16-196 format ethernet frame, 16-318 high-speed irda, 16-292 i2c controller memory, 16-467 level one descriptor, 11-9 level two descriptor, 11-10 localtalk frames, 16-265 low-speed irda, 16-288 middle-speed irda, 16-289 sccx buffer descriptors, 16-179 serial management controller memory, 16-385 serial peripheral interface memory, 16-442 smc in uart mode frames, 16-393 uart character, 16-201 universal serial bus commands, 16-363 video ram word, 19-17 formats instructions, b-1 fractional stop bits, 16-213 frame buffer a start address register, 18-27 frame buffer b start address register, 18-28 frame buffer, 18-6 frame check sequence, 16-273 frame length, maximum, 16-115 frame reception sccx in async hdlc mode, 16-270 sccx in ethernet mode, 16-324 sccx in hdlc mode, 16-235 sccx in transparent mode, 16-303 smc in transparent mode, 16-410 smc in uart mode, 16-394 frame transmission sccx in async hdlc mode, 16-269 sccx in ethernet mode, 16-323 sccx in hdlc mode, 16-234 sccx in transparent mode, 16-302 smc in transparent mode, 16-409 smc in uart mode, 16-393 frame, 2-12 free access override mode, 11-4 frequencies, requirements for switching, 5-17 frequency jitter, 5-14 frequency of an application, 5-17 frequency of interrupt routines, 5-17 frz, 2-4 , 20-30 full-duplex operation, 16-259 function descriptor (fd), 16-27 g gci (definition), 16-150 , 16-425 gclkx frequency, 5-19 gclkx, 5-14
index index-12 mpc823e reference manual motorola gclkx_50 frequency, 5-19 gclkx_50, 5-14 gclkxc, 5-14 general circuit interface activation and deactivation, 16-151 operation, 16-150 programming example, 16-153 normal mode, 16-152 scit mode, 16-152 programming, 16-152 general circuit interface, 16-425 general-purpose chip-select machine configuring, 15-27 general-purpose chip-select machine, 15-27 generating serial infrared interaction pulses, 16-293 glue logic, 15-5 gnd, 2-12 gotolink dsp protocol table 16-2 gotolink dual port ram protocol table 16-2 gotolink mpc823_s16b idma protocol table 16-2 gotolink mpc823_s16c scc parameter table 16-2 gotolink risc timer table protocol table 16-2 gotolink s16c_cpm uart protocol table 16-2 gotolink s16d_cpm hdlc protocol table 16-2 gotolink s16e_cpm appletalk protocol table 16-2 async hdlc protocol table 16-2 infra-red protocol 16-2 transparent protocol table 16-2 gotolink s16f_cpm ethernet protocol table 16-2 smc protocol table 16-2 smc uart protocol table 16-2 gotolink s16g_cpm gci protocol table 16-2 spi protocol table 16-2 transparent protocol table 16-2 usb protocol table 16-2 gotolink s16h_cpm i2c protocol table 16-2 parallel ports 16-2 gpcm (definition), 15-27 gpl_a0, 2-5 gpl_a1, 2-5 gpl_a2, 2-6 gpl_a3, 2-6 gpl_a4, 2-6 gpl_a5, 2-6 gpl_b0, 2-5 gpl_b1, 2-5 gpl_b2, 2-6 gpl_b3, 2-6 gpl_b4, 2-6 gpl_b5, 2-2 gsmr_h, 16-166 gsmr_l, 16-170 guarded, 11-4 h hard reset configuration word, 4-10 hard reset, registers affected, 6-24 hash table algorithm, 16-334 hdlc (definition), 16-233 hdlc bus controller accessing, 16-260 delayed rts mode, 16-262 performance, 16-261 using the time-slot assigner, 16-263 hdlc bus controller, 16-257 hdlc mode sccx, 16-233 history buffer storage, 6-9 history buffer, instructions that fill it, 6-9 horizontal sync, 18-5 hreset, 2-6 , 4-3 hsync, 2-12 i i2add, 16-473 i2brg, 16-474 i2c controller 16-456 address register (i2add), 16-473 baud rate generator register (i2brg), 16-474 buffer descriptor ring, 16-467 command register (i2com), 16-474 commands, 16-466 event register (i2cer), 16-475 features, 16-457 mask register (i2cmr), 16-476 memory map, 3-5 mode register (i2mod), 16-468 operation, 16-457 parameter ram memory map, 16-463 programming, 16-468 receive buffer descriptor, 16-469 transmission and reception, 16-458 transmit buffer descriptor, 16-471 i2cer, 16-475 i2cmr, 16-476 i2com, 16-474 i2cscl, 2-9
index motorola mpc823e reference manual index-13 i2csda, 2-9 i2mod, 16-468 i-address, 20-9 ic_adr, 9-6 ic_cst, 9-5 ic_dat, 9-7 icbi, 11-48 icr, 20-55 ictrl, 6-17 , 20-45 idg (definition), 16-266 idl (definition), 16-144 idl interface implementation, 16-145 operation, 16-144 programming example, 16-149 programming, 16-148 idle condition (definition), 16-201 idma buffer descriptors, 16-96 commands, 16-100 edge-sensitive mode, 16-101 features, 16-90 interface signals, 16-90 level-sensitive mode, 16-101 operand transfers, 16-102 operation, 16-90 parameter ram memory map, 16-92 single address mode, 16-103 single-buffer burst fly-by mode, 16-105 starting, 16-101 transfers, 16-101 idma transfers, performing, 16-91 idma, 16-89 idma1 and 2 mask register, 16-95 , 16-110 idma1 and 2 status register, 16-94 , 16-109 idmrx, 16-95 , 16-110 idsrx, 16-94 , 16-109 ifg (definition), 16-266 iir applications, 16-59 coefficients and sample data buffers, 16-57 function descriptor, 16-58 parameter packet, 16-59 iir, 16-57 image sizes, switching between, 19-4 immr, 3-1 , 6-18 , 12-34 implementation idl interface, 16-145 sccx async hdlc, 16-273 implementing a precise exception model, 6-8 in token, 16-357 infra-red encoder/decoder, 16-198 initialization of the control registers, 6-24 sccx in uart mode example, 16-230 serial communication controllers, 16-188 universal serial bus example, 16-378 , 16-380 instruction address, 20-9 instruction cache coherency, 9-14 commands cache disable, 9-11 cache enable, 9-11 instruction cache block invalidate, 9-9 invalidate all, 9-9 load & lock, 9-10 unlock all, 9-11 unlock line, 9-10 commands, 9-8 data path block diagram, 9-4 debug support, 9-15 features, 9-1 instruction fetch on a predicted path, 9-8 invalidating, 9-9 operation, 9-7 reading, 9-12 reset, 9-14 restoring the state of, 9-15 restrictions, 9-14 special purpose control registers, 9-4 updating code and memory region attributes, 9-14 writing, 9-14 instruction cache address register, 9-6 instruction cache control and status register, 9-5 instruction cache data port register, 9-7 instruction cache, 9-1 instruction cache, how to disable, 9-11 instruction cache, how to enable, 9-11 instruction cache, how to inhibit, 9-11 instruction execution timing examples, 8-4 instruction execution timing, 8-1 instruction fetch show cycles, 20-8 instruction flow (illustration), 6-3 instruction register, 21-19 instruction, long latency, 6-9 instructions b-1 add, b-7 addc, b-8 adde, b-9 addi, b-10 addic, b-11 addic., b-12 addis, b-13 addme, b-14 addze, b-15 and, b-16
index index-14 mpc823e reference manual motorola andc, b-17 andi., b-18 andis., b-19 b, b-20 bc, b-21 bcctr, b-23 bclr, b-25 branch, 8-1 bypass, 21-20 cache control, 8-3 clamp, 21-20 cmp, b-27 cmpi, b-28 cmpl, b-29 cmpli, b-30 cntlzwx, b-31 conditions for retiring from head of queue, 6-13 cr logical, 8-1 crand, b-32 crandc, b-33 creqv, b-34 crnand, b-35 crnor, b-36 cror, b-37 crorc, b-38 crxor, b-39 data cache, 10-3 , 10-14 dcbf, b-40 dcbi, b-42 dcbst, b-44 dcbt, b-45 dcbtst, b-46 dcbz, b-47 divw, b-49 divwu, b-51 eciwx, b-53 ecowx, b-55 eieio, b-57 eqv, b-59 execution results, 6-23 extest, 21-19 extsb, b-60 extsh, b-61 fields, b-2 fixed-point arithmetic (divide), 8-2 fixed-point arithmetic (multiply), 8-2 fixed-point arithmetic, 8-2 fixed-point compare, 8-2 fixed-point load and store, 8-2 fixed-point load, 8-2 fixed-point logical, 8-2 fixed-point rotate and shift, 8-2 fixed-point store, 8-2 fixed-point trap, 8-1 format, b-1 hi-z, 21-20 icbi, b-62 illegal and reserved, 7-1 isync, b-64 lbz, b-65 lbzu, b-66 lbzux, b-67 lbzx, b-68 lha, b-69 lhau, b-70 lhaux, b-71 lhax, b-72 lhbrx, b-73 lhz, b-74 lhzu, b-75 lhzux, b-76 lhzx, b-77 lmw, b-78 lswi, b-79 lswx, b-81 lwarx, b-83 lwbrx, b-85 lwz, b-86 lwzu, b-87 lwzux, b-88 lwzx, b-89 mcrf, b-90 mcrxr, b-91 mfcr b-92 mfmsr, b-93 mfspr, b-94 mftb, b-98 move condition register from xer, 8-2 move from external to core, 8-1 move from others, 8-2 move from special registers, 8-1 move to external to the core, 8-1 move to lr, ctr, 8-1 move to special 8-1 move to/from special purpose register, 8-2 mtcrf, b-100 mtmsr, b-101 mtspr, b-102 mulhw, b-104 mulhwu, b-105 mulli, b-106 mullw, b-107 nand, b-108 neg, b-109 nonoptional, 7-1 nor, b-110 notations and conventions, b-3 optional, 7-1 or, b-111 orc, b-112
index motorola mpc823e reference manual index-15 order storage access, 8-3 ori, b-113 oris, b-114 rfi, b-115 rlwimi, b-116 rlwinm, b-118 rlwnm, b-120 sample/preload, 21-20 sc, b-122 slw, b-123 sraw, b-124 srawi, b-125 srw, b-126 stb, b-127 stbu, b-128 stbux, b-129 stbx, b-130 sth, b-131 sthbrx, b-132 sthu, b-133 sthux, b-134 sthx, b-135 stmw, b-136 storage control, 8-3 storage synchronization, 8-2 string, 8-2 stswi, b-137 stswx, b-138 stw, b-139 stwbrx, b-140 stwcx, b-141 stwu, b-143 stwux, b-144 stwx, b-145 subf, b-146 subfc, b-147 subfe, b-148 subfic, b-149 subfme, b-150 subfze, b-151 sync, b-152 synchronize, 8-2 system call, 8-1 timing list, 8-1 tlbia, b-153 tlbie, b-154 tlbsync, b-155 tw, b-156 twi, b-157 xor, b-158 xori, b-159 xoris, b-160 instructions (cancelled), compression of, 20-8 instructions, class, 7-1 instructions, controlling the flow of, 6-5 instructions, definitions, 7-1 instructions, flow of, 6-2 instructions, invalid and preferred, 7-1 instructions, issuing, 6-6 instructions, serializing, 6-12 interdialog gap, 16-266 interface, development system 20-20 debug mode support, 20-22 trap enable mode, 20-22 interfacing with slow devices, 15-67 interference, reducing, 5-19 interference, reduction, 5-12 interframe gap, 16-266 internal accesses (definition), 15-68 internal arbiter, enabling, 13-42 internal hard reset, 4-3 internal hard reset, causes of, 4-3 internal memory map register, 3-1 internal soft reset, 4-4 interrupt controller memory map, 3-6 interrupt generation, 5-28 interrupt handler code, notification of restartability, 6-10 interrupt latency, minimal, 6-13 interrupt structure (illustration), 12-5 interrupt vectors encoding, 16-506 generating, 16-505 interrupt, conditions for, 6-7 interrupt, recovery from, 6-8 interrupt, restarting after an, 6-10 interrupts classes, 7-7 configuring, 12-5 cpm interrupt controller, 16-512 definitions, 7-8 external, 6-13 from sccx, 16-187 handling in sccs, 16-188 highest priority, 16-502 implementation-specific breakpoint, 6-10 debug port unmaskable, 6-10 implementation-specific data tlb error, 11-48 implementation-specific data tlb miss, 11-47 implementation-specific instruction tlb error, 11-48 implementation-specific instruction tlb miss, 11-47 implementation-specific, 6-10 masking sources in the cpm, 16-504 memory management unit implementation specific data tlb error,
index index-16 mpc823e reference manual motorola 11-48 implementation specific data tlb miss, 11- 47 implementation specific instruction tlb error, 11-48 memory managment unit implementation specific instruction tlb miss, 11-47 nested, 16-504 on a serial interface ram entry, 16-141 order of detection, 6-14 ordering, 6-14 pcmcia, 17-8 processing, 6-11 , 7-8 serial peripheral interface, 16-455 siu sources, 12-6 smc in transparent mode, 16-425 smc in uart mode, 16-408 system reset, 6-24 types, 6-14 interrupts, 7-7 interrupts, generating, 6-7 invalidating the tlb, 11-51 iois16_b, 2-7 iord, 2-5 iowr, 2-5 ip_b0, 2-7 ip_b1, 2-7 ip_b2, 2-7 ip_b3, 2-7 ip_b4, 2-7 ip_b5, 2-7 , 2-8 ip_b7, 2-8 irda 4ppm data encoding, 16-290 data link layer, 16-291 interaction pulses, 16-293 physical layer, 16-292 programming high-speed example, 16-300 low-speed example, 16-297 middle-speed example, 16-298 irda (definition), 16-198 irda high-speed, 16-290 irda low-speed, 16-288 irda middle-speed, 16-289 irda, 16-287 irlap (definition), 16-269 irmode, 16-294 irq0, 2-4 irq1, 2-4 irq2, 2-3 irq3, 2-3 irq4, 2-3 irq5, 2-4 irq6, 2-4 irq7, 2-4 irsip, 16-296 isdn, 16-384 isochronous operation, 16-202 iwp0, 2-7 iwp1, 2-7 iwp2, 2-7 j joint test action group, 21-1 jtag (definition), 21-1 k kapwr, 2-12 , 5-25 keep-alive power, 5-25 key register operation, 5-27 kr, 2-3 , 13-5 l l1rclka, 2-8 l1rclkb, 2-8 l1rqa, 2-10 l1rsynca, 2-11 l1rsyncb, 2-10 l1rxda, 2-8 l1rxdb, 2-9 l1st1, 2-10 l1st3, 2-10 l1st4, 2-10 l1st6, 2-10 l1st7, 2-10 l1st8, 2-10 l1tclka, 2-9 l1tclkb, 2-9 l1tsynca, 2-11 l1tsyncb, 2-9 l1txda, 2-8 l1txdb, 2-10 l-address, 20-9 last bit, 15-64 latency, command execution, 16-13 latency, interrupt, 6-11 lccr, 18-21 lcd controller block diagram, general, 18-7 color ram active four- and eight-bit color mode, 18- 36 four-bit/pixel grayscale mode, 18-33 one-bit/pixel monochrome mode, 18-30
index motorola mpc823e reference manual index-17 passive, four- and eight-bit color mode, 18- 35 two-bit/pixel grayscale mode, 18-32 color ram, 18-30 contrast and brightness control, 18-14 dma control, 18-13 features, 18-1 fifo, 18-9 frame control, 18-13 horizontal control, 18-13 interface active, 18-17 analog, 18-19 passive, 18-15 single- and dual-scan panels, 18-15 interface, 18-3 , 18-14 lcd clocks, 5-21 memory map, 3-5 operation, 18-8 panel connection examples, 18-37 pixel generation color, 18-12 grayscale, 18-10 pixel generation, 18-10 registers configuration register (lccr), 18-21 frame buffer a start address register (lcfaa), 18-27 frame buffer b start address register (lcfba), 18-28 horizontal control register (lchcr), 18-23 status register (lcsr), 18-29 vertical controler register (lcvcr), 18-25 registers, 18-21 system considerations, 18-19 timing control, 18-14 vertical control, 18-13 lcd controller, 18-6 lcd horizontal control register, 18-23 lcd interface active, 18-5 passive, 18-4 smart panel interface, 18-5 lcd interface, 18-3 lcd status register, 18-29 lcd technology, 18-2 lcd vertical control register, 18-25 lcd_a, 2-9 lcd_ac, 2-12 lcd_b, 2-10 lcd_c, 2-10 lcdclk and lcdclk50 frequency, 5-21 lcdclk, 5-21 lcdclk50, 5-21 lcfaa, 18-27 lcfba, 18-28 lchcr, 18-23 lcsr, 18-29 lctrl1, 20-48 lctrl2, 20-50 lctrlx, 6-17 lcvcr, 18-25 ld0, 2-11 ld1, 2-11 ld2, 2-11 ld3, 2-11 ld4, 2-11 ld5, 2-11 ld6, 2-11 ld7, 2-11 ld8, 2-11 l-data, 20-9 len values, 16-445 level interrupt, 12-7 level sensitive idma, 16-90 library, dsp, 16-38 limitations, of the usb host, 16-352 linefeed, 16-232 little-endian sdma, 16-83 lms1 applications, 16-67 coefficients and sample data buffers, 16-65 function descriptor, 16-66 parameter packet, 16-67 lms1, 16-65 lms2 applications, 16-70 coefficients and sample data buffers, 16-68 function descriptor, 16-68 parameter packet, 16-70 lms2, 16-67 load (instruction), 10-12 load, 2-12 load, 11-48 load/store address, 20-9 load/store data, 20-9 locating special-purpose registers, 6-19 loe, 2-12 loopback mode (local), 16-174 loopback mode, 16-115 loopback, 16-335 loopback/echo mode, 16-175 loops, nesting, 15-59 low-power divider, 5-14 low-power mode (illustration), 5-29 low-power mode, power consumption equations, 5- 31 low-power stop operation, 12-28 low-power, operating at, 5-28
index index-18 mpc823e reference manual motorola lwarx, 13-38 lwp0, 2-7 lwp1, 2-7 , 2-8 m m_casid, 11-18 m_tw, 11-37 m_twb, 11-36 mac (definition), 16-4 machine a mode register, 15-19 machine b mode register, 15-22 machine state register, 6-20 mamr, 15-19 manchester, 16-197 mar, 15-26 master, 16-435 mbmr, 15-22 mcr, 15-17 md_ap, 11-32 md_cam, 11-38 md_ctr, 11-17 md_epn, 11-20 md_ram0, 11-39 md_ram1, 11-41 md_rpn, 11-26 md_twc, 11-34 mdr, 15-26 mechanicals 23-1 pin assignment, 23-2 memory 16-92 memory access, controlling, 15-40 memory address register, 15-26 memory coherence, 7-4 , 11-4 memory command register, 15-17 memory controller architecture, 15-4 baud rate generator clock, 5-19 block diagram, 15-3 external masters examples, 15-72 types 15-68 external masters, 15-68 features, 15-1 gpcm configuration, 15-27 gpcm, 15-27 memory map, 3-2 memory system interface examples, 15-76 registers, 15-7 transfers, 13-25 upms block diagram, 15-40 clock timing, 15-44 programming, 15-43 ram array, 15-48 requests, 15-41 wait mechanism, 15-65 upms, 15-40 memory controller registers, using, 15-8 memory controller, 15-1 memory data register, 15-26 memory management unit accessing the control registers, 11-52 address translation, 11-2 features, 11-1 interrupts, 11-47 programming control registers, 11-16 data status registers, 11-37 instruction status registers, 11-43 programming, 11-15 protection, 11-3 storage control, 11-4 tlb manipulation, 11-49 translation lookaside buffers, 11-2 translation table structure level one descriptor, 11-9 level two descriptor, 11-10 translation table structure, 11-5 memory management unit, 11-1 memory map baud rate generators, 3-8 clocks and reset keys, 3-4 clocks and reset, 3-3 communication processor module, 3-7 cpm interrupt controller, 3-6 cpm timer, 3-7 dma controller, 3-5 dual-port ram, 3-12 hdlc bus controller, 16-264 i2c controller, 3-5 , 16-463 lcd controller, 3-5 memory controller, 3-2 parallel ports, 3-6 pcmcia, 3-1 port b, 3-11 sccx in async hdlc mode, 16-274 sccx in ethernet mode, 16-326 sccx in hdlc mode, 16-236 sccx in transparent mode, 16-307 sccx in uart mode, 16-204 sccx, 16-182 serial communication controller 2, 3-9 serial communication controller 3, 3-9 serial interface, 3-11 serial management controller 1, 3-10 serial management controller 2, 3-10
index motorola mpc823e reference manual index-19 serial management controllers, 16-385 serial peripheral interface, 3-11 , 16-438 smc in gci mode, 16-427 smc in transparent mode, 16-415 smc in uart mode, 16-394 specialized ram, 3-11 system integration timer keys, 3-4 system integration timers, 3-3 system interface unit, 3-1 universal serial bus, 3-8 , 16-358 video controller, 3-4 memory periodic timer prescaler register, 15-27 memory status register, 15-15 memory structure, sccx, 16-180 mfspr, 10-4 , 11-15 , 12-13 mftb, 12-14 mftbu, 12-14 mi_ap, 11-31 mi_cam, 11-43 mi_ctr, 11-16 mi_epn, 11-19 mi_ram0, 11-45 mi_ram1, 11-46 mi_rpn, 11-21 mi_twc, 11-33 microcode configurations, 16-9 microcode, executing from ram or rom, 16-7 mmu current address space id register, 11-18 mmu data access protection register, 11-32 mmu data cam entry read register, 11-38 mmu data control register, 11-17 mmu data effective page number, 11-20 mmu data ram entry read register 0, 11-39 mmu data ram entry read register 1, 11-41 mmu data real page number register, 11-26 mmu data tablewalk control register, 11-34 mmu instruction access protection register, 11-31 mmu instruction cam entry read register, 11-43 mmu instruction control register, 11-16 mmu instruction effective page number register, 11- 19 mmu instruction ram entry read register 0, 11-45 mmu instruction ram entry read register 1, 11-46 mmu instruction real page number register, 11-21 mmu instruction tablewalk control register, 11-33 mmu tablewalk base register, 11-36 mmu tablewalk special register, 11-37 mod applications, 16-62 function descriptor, 16-61 modulation table and sample data buffers, 16- 60 parameter packet, 16-62 modck1, 2-8 , 5-22 modck2, 2-8 , 5-22 mode 16-176 modes copyback, 10-11 data cache, 10-10 writethrough, 10-12 modes, switching between, 5-30 mpc823 block diagram, 1-7 debugging, 9-15 , 10-12 general system (illustration), 14-2 instruction set, b-6 lcd controller interface 18-14 operation, 18-8 panel connection examples, 18-37 registers, 18-21 system considerations, 18-19 power supply, 5-25 mptpr, 15-27 msr, 6-19 , 6-20 , 7-9 mstat, 15-15 mtspr, 10-4 , 11-15 , 12-13 mttb, 12-14 mttbu, 12-14 multibuffer operation, 16-206 multidrop environment, 16-208 n n/c, 2-12 newlink async hdlc protocol table 16-274 newlink brgs 16-157 newlink cpmic 16-499 newlink dsp protocol table 16-31 newlink ethernet protocol table 16-326 newlink gci protocol table 16-427 newlink hdlc protocol table 16-236 newlink i2c 16-456 newlink i2c protocol table 16-463 newlink idma protocol table 16-92 newlink infrared protocol 16-287 newlink parallel ports 16-477 newlink risc microcontroller 16-4 newlink risc timer table protocol table 16-19 newlink scc 16-163 newlink sccx parameter table 16-183 newlink serial interface 16-112 newlink siu 12-1 newlink smc 16-382 newlink smc protocol table 16-386 newlink smc uart protocol table 16-394 newlink spi 16-433 newlink spi protocol table 16-438 newlink timers 16-74
index index-20 mpc823e reference manual motorola newlink transparent protocol table 16-307 newlink uart protocol table 16-204 newlink usb 16-350 nmi (definition), 12-5 nmsi configuration, 16-154 features, 16-114 nmsi (definition), 16-112 no access override mode, 11-4 no override mode, 11-4 noise, reducing, 5-19 nrz, 16-196 nrzi mark, 16-196 nrzi space, 16-196 ntsc (definition), 19-20 o oe, 2-5 ohci (definition), 16-352 op2, 2-8 op3, 2-8 open host controller interface, 16-352 operand placement (effects), 7-5 operating frequencies, reducing and restoring, 5-15 operation address translation, 11-2 autobaud, 16-159 boot chip-select, 15-37 bus interface, 13-7 clocks, 5-10 cpm interrupt controller, 16-499 data cache, 10-10 digital phase-locked loop, 16-193 dsp, 16-26 endian mode, 14-5 freeze, 12-28 general circuit interface, 16-150 general-purpose chip-select machine, 15-27 hdlc bus controller, 16-257 i2c controller, 16-457 idl interface, 16-144 instruction cache, 9-7 irda, 16-198 lcd controller, 18-8 localtalk, 16-265 low-power, 5-28 low-speed irda, 16-288 memory controller (illustration), 15-7 parallel i/o ports, 16-477 pcmcia i/o cards, 17-7 pcmcia memory-only cards, 17-7 pcmcia, 17-7 port a, 16-478 port b, 16-484 port c, 16-490 port d, 16-497 power control, 5-24 program flow tracking, 20-3 ram word, 15-54 register unit of the core, 6-15 scc2 in irda mode, 16-287 sccx in ethernet mode, 16-318 , 16-320 sccx in hdlc mode, 16-233 sccx in transparent mode, 16-301 sccx in uart mode, 16-201 sdma, 16-84 sequencer unit of the core, 6-4 serial interface ram, 16-117 serial management controllers, 16-382 serial peripheral interface multimaster, 16-437 serial peripheral interface, 16-435 smc in gci mode, 16-425 timers, 16-75 translation lookaside buffers, 11-2 universal serial bus, 16-350 user-programmable machines, 15-40 video controller, 19-2 watchpoints and breakpoints, 20-16 operations that support endian modes, 14-2 option registers, 15-11 ordering information 23-1 oscillator, main clock, 5-12 oscillators, advantages, 5-10 oscm, 5-12 osi (definition), 16-233 ossclk, 5-12 out token, 16-356 output enable, 18-5 p package dimensions, 23-3 padat, 16-480 padir, 16-481 pal (definition), 19-24 paodr, 16-480 papar, 16-481 , 16-499 parallel i/o port operation port a, 16-478 parallel i/o ports 16-477 features, 16-478 operation, 16-477 port a examples, 16-482 registers
index motorola mpc823e reference manual index-21 data direction register (padir), 16-481 data register (padat), 16-480 open-drain (paodr), 16-480 pin assignment register (papar), 16- 481 registers, 16-480 port b configuration example, 16-490 operation, 16-484 pins, 16-484 registers open-drain (pbodr), 16-485 registers, 16-485 port c data direction register (pcdir), 16-493 data register (pcdat), 16-493 interrupt control register (pcint), 16-496 operation, 16-490 pin assignment register (pcpar), 16-494 pins, 16-490 registers, 16-492 special options register (pcso), 16-494 port d data direction register (pddir), 16-498 data register (pddat), 16-498 operation, 16-497 pin assignment register (pdpar), 16-499 pins, 16-497 registers, 16-498 registers port b data direction (pbdir), 16-488 data register (pbdat), 16-487 pin assignment (pbpar), 16-489 parallel ports memory map, 3-6 parameter ram dsp, 16-30 idma single-buffer mode, 16-106 sccx in async hdlc mode, 16-274 sccx, 16-182 parameter ram memory map i2c controller, 16-463 idma, 16-92 risc timer tables, 16-18 sccx in ethernet mode, 16-326 sccx in hdlc mode, 16-236 sccx in transparent mode, 16-307 sccx in uart mode, 16-204 serial peripheral interface, 16-438 smc in gci mode, 16-427 smc in transparent mode 16-415 smc in uart mode, 16-394 universal serial bus, 16-358 parameter ram tables i2c controller, 16-463 idma, 16-92 sccx in async hdlc mode, 16-274 sccx in ethernet mode, 16-326 sccx in hdlc mode, 16-236 sccx in transparent mode, 16-307 sccx in uart mode, 16-204 sccx, 16-183 serial peripheral interface, 16-438 smc in gci mode, 16-427 smc in uart and transparent modes, 16- 386 smc in uart mode, 16-394 universal serial bus, 16-358 parameter ram, structure, 16-15 parameter storage, 16-30 parity error, 15-7 , 15-8 parity, configuring, 15-8 patterns, preamble, 16-195 pbdat, 16-487 , 16-493 pbdir, 16-488 pbga (definition), 23-3 pbodr, 16-485 pbpar, 16-489 pbrx, 17-16 pcdir, 16-493 pci bridge (definition), 14-2 pcint, 16-496 pcmcia 17-1 configuration, 17-1 features, 17-1 memory map, 3-1 operation dma, 17-8 i/o cards, 17-7 interrupts, 17-8 memory-only cards, 17-7 power control, 17-8 reset and three-state, 17-8 operation, 17-7 programming, 17-9 registers base (pbrx), 17-16 interface enable (per), 17-13 interface general control register b (pgcrb), 17-15 interface input pins (pipr), 17-9 interface status change (pscr), 17-11 option (porx), 17-17 signals, 17-3 timing examples, 17-22 pcoe, 2-5 pcpar, 16-494 pcso, 16-494
index index-22 mpc823e reference manual motorola pcwe, 2-5 pda example, 16-4 pddat, 16-498 pddir, 16-498 per, 17-13 performance ethernet, 16-334 hdlc bus controller, 16-261 maximizing, 9-15 performance, achieving the best, 5-24 periodic interrupt count register key, 5-27 periodic interrupt status and control register key, 5- 27 periodic interrupt status and control register, 12-23 periodic interrupt timer block diagram, 12-22 periodic interrupt timer count register, 12-24 periodic interrupt timer register, 12-25 periodic interrupt timer, 12-22 periodic timers, 15-42 pgcrb, 17-15 phase jitter, 5-14 phase skew, 5-13 pin assignments port a, 16-479 port b, 16-484 port c, 16-490 port d, 16-497 pwm channels, 16-22 pinout diagram, 2-1 pins assignment, 23-2 development support, 20-29 nmsi, 16-155 system interface unit, 12-29 universal serial bus, 16-354 pins, 2-1 pins, unconnected, 2-12 pipeline bubbles, cause of, 6-5 pipr, 17-9 piscr, 12-23 piscrk, 5-27 pitc, 12-24 pitck, 5-27 pitr, 12-25 pixel generation, 18-10 pll, 13-7 pll, low power, and reset control register, 5-7 pll, low-power and reset control register key, 5-27 plprcrk, 5-27 poreset, 2-6 , 4-2 port a data direction register, 16-481 data register, 16-480 open-drain register, 16-480 pin assignment register, 16-481 port b memory map, 3-11 port b data direction register, 16-488 data register, 16-487 open-drain register, 16-485 pin assignment register, 16-489 port c data direction register, 16-493 data register, 16-493 interrupt control register, 16-496 pin assignment register, 16-494 special options register, 16-494 port d data direction register, 16-498 data register, 16-498 pin assignment register, 16-499 port width (definition), 13-1 ports, special to msr, 6-11 porx, 17-17 power conserving, 16-200 pcmcia, 17-8 power consumption minimizing, 9-7 , 10-11 power control keep-alive power register locking, 5-27 keep-alive power, 5-25 operation, 5-24 power rails, 5-24 power planes, 5-24 power rails, 5-24 power supply pins, 2-12 power supply requirements, 5-25 power, reducing, 5-19 power, switching schemes, 5-26 power-down mode, exiting from, 5-30 power-on reset, 4-2 power-on reset, state of key registers, 5-27 powerpc core about the, 6-1 basic structure, 6-2 features, 6-1 powerpc standards powerpc operating environment architecture (book 3) branch processor, 7-6 fixed-point processor, 7-6 interrupts, 7-7 optional facilities and instructions, 7-17 reference and change bits, 7-7 storage control instructions, 7-7 storage model, 7-6 timer facilities, 7-17
index motorola mpc823e reference manual index-23 powerpc operating environment architecture (book 3), 7-6 powerpc operating environment architecture (book 3), storage protection, 7-7 powerpc user instruction set architecture (book 1) branch instructions, 7-2 branch processor, 7-2 computation modes, 7-1 exceptions, 7-2 fixed point-processor, 7-2 instruction classes, 7-1 load/store processor, 7-3 reserved fields, 7-1 powerpc user instruction set architecture (book 1), 7-1 powerpc virtual environment architecture (book 2) operand placement effects, 7-5 storage control instructions, 7-5 storage model, 7-4 timebase, 7-6 powerpc virtual environment architecture (book 2), 7-4 powerpc user instruction set architecture book 1 instruction fetching, 7-2 ppm (definition), 16-290 ppp (definition), 16-269 pre token, 16-358 preamble, sending, 16-212 processor, state of, 6-20 program flow tracking, 20-2 program trace cycle (definition), 20-3 program trace, reconstructing, 20-2 programming 16-286 programming cpm interrupt controller, 16-507 data cache, 10-3 development port, 20-41 dsp, 16-27 general circuit interface, 16-152 hdlc bus controller, 16-264 idl interface, 16-148 instruction cache, 9-4 memory management unit, 11-15 pcmcia, 17-9 scc2 in ethernet mode example, 16-348 scc2 in irda mode, 16-294 scc2 in low-speed irda mode example, 16- 297 scc2 in middle-speed irda mode example, 16- 298 scc2 in transparent mode example, 16-317 sccx in appletalk mode, 16-268 sccx in async hdlc mode example, 16- 286 sccx in async hdlc mode, 16-279 sccx in ethernet mode, 16-337 sccx in hdlc mode example, 16-255 , 16- 256 sccx in hdlc mode, 16-238 sccx in uart mode example, 16-230 sccx in uart mode s-record example, 16- 232 sccx in uart mode, 16-206 sccx transparent mode patterns, 16-304 serial interface ram, 16-122 serial peripheral interface master example, 16- 453 serial peripheral interface slave example, 16- 454 serial peripheral interface, 16-443 siu interrupt controller, 12-7 smc in transparent mode nmsi example, 16- 423 smc in transparent mode tsa example, 16- 424 smc in uart mode example, 16-407 smc in uart mode, 16-395 system interface unit, 12-30 time-slot assigner, 16-115 tlb replacement counter, 11-51 universal serial bus, 16-365 user-programmable machines, 15-43 video controller, 19-5 programming the spll, 5-1 promiscuous operation, 16-301 protocols scc2 in irda mode, 16-287 sccx in async hdlc mode, 16-269 sccx in ethernet mode, 16-318 sccx in hdlc mode, 16-233 sccx in transparent mode, 16-301 sccx in uart mode, 16-201 smc in gci mode, 16-425 smc in transparent mode, 16-409 smc in uart mode, 16-392 protocols of the sccs, 16-163 protocols, asynchronous, 16-193 protocols, switching, 16-200 , 16-392 protocols, synchronous, 16-189 pscr, 17-11 psmr, 16-176 psmrCasync hdlc, 16-279 psmrCethernet, 16-337 psmrChdlc, 16-242 psmrCscc uart, 16-217 ptr, 2-8 , 13-4 pts (definition), 15-41
index index-24 mpc823e reference manual motorola pull-up resistors, 16-477 pulses, 16-293 pwm (definition), 16-17 r raindrop effect, 18-3 ram addresses, serial interface ram, 16-125 , 16- 126 ram array and signal generation (illustration), 15- 48 ram array size, 15-48 ram array, indexing service requests, 15-42 ram word (definition), 15-49 ram word format, 15-49 ram word operation, 15-54 ram words, storing, 15-43 ram, video control, 19-16 rbs (definition), 15-41 rccr, 16-7 rclk, 16-321 rd/wr, 2-2 , 13-4 , 13-32 read accesses, extending hold time, 15-34 read hit, 10-10 read miss, 10-10 real-time alarm register key, 5-27 real-time alarm seconds key, 5-27 real-time clock alarm register, 12-21 real-time clock alarm seconds register, 12-20 real-time clock block diagram, 12-17 real-time clock register key, 5-27 real-time clock register, 12-19 real-time clock status and control register key, 5-27 real-time clock status and control register, 12-18 real-time clock, 12-17 reference bit updates, 11-4 register universal serial bus status, 16-377 register unit, of the core, 6-15 registers baud rate generator configuration, 16-160 boundary scan, 21-4 breakpoint address, 20-44 breakpoint counter a value and control, 20-53 breakpoint counter b value and control, 20-54 comparator a-d value, 20-42 comparator e-f value, 20-43 comparator g-h value, 20-44 condition, 6-22 control, 6-16 cpm command, 16-9 cpm interrupt controller, 16-507 data cache (special), 10-4 data cache address, 10-7 data cache control and status, 10-5 data synchronization, 16-177 debug enable, 20-57 decrementer, 12-13 development port data, 20-60 development port shift, 20-30 dsp event, 16-33 dsp mask, 16-34 fixed-point exception cause, 6-23 frame buffer a start address set 0, 19-11 frame buffer a start address, 18-27 frame buffer b start address, 18-28 general sccx mode high and low, 16-166 general smc mode, 16-384 i2c address, 16-473 i2c baud rate generator, 16-474 i2c command, 16-474 i2c event, 16-475 i2c mask, 16-476 i2c mode, 16-468 idma1 and 2 mask, 16-95 , 16-110 idma1 and 2 status, 16-94 , 16-109 instruction cache address, 9-6 instruction cache control and status, 9-5 instruction cache data port, 9-7 instruction support control, 20-45 internal memory map, 3-1 , 12-34 interrupt cause, 20-55 key, 3-4 , 5-27 lcd controller configuration, 18-21 load/store support and-or control, 20-50 load/store support comparators control, 20-48 machine a mode, 15-19 machine b mode, 15-22 machine state, 6-20 memory address, 15-26 memory command, 15-17 memory controller base, 15-9 memory controller option, 15-11 memory controller, 15-7 memory data, 15-26 memory periodic timer prescaler, 15-27 memory status, 15-15 mmu current addresss space id, 11-18 mmu data access protection, 11-32 mmu data cam entry read, 11-38 mmu data control, 11-17 mmu data effective page number, 11-20 mmu data ram entry read 0, 11-39 mmu data ram entry read 1, 11-41 mmu data real page number, 11-26 mmu data tablewalk control, 11-34 mmu instruction access protection, 11-31 mmu instruction cam entry read, 11-43 mmu instruction control, 11-16 mmu instruction effective page number, 11-19
index motorola mpc823e reference manual index-25 mmu instruction ram entry read 0, 11-45 mmu instruction ram entry read 1, 11-46 mmu instruction real page number, 11-21 mmu instruction tablewalk control, 11-33 mmu tablewalk base, 11-36 mmu tablewalk special, 11-37 pcmcia base, 17-16 pcmcia interface enable, 17-13 pcmcia interface general control register b, 17-15 pcmcia interface input pins, 17-9 pcmcia interface status change, 17-11 pcmcia option, 17-17 periodic interrupt status and control, 12-23 periodic interrupt timer count, 12-24 periodic interrupt timer, 12-25 pll, low power, and reset control, 5-7 port a data direction, 16-481 port a data, 16-480 port a open-drain, 16-480 port a pin assignment, 16-481 port a, 16-480 port b data direction, 16-488 port b data, 16-487 port b open-drain, 16-485 port b pin assignment, 16-489 port b, 16-485 port c data direction, 16-493 port c data, 16-493 port c interrupt control, 16-496 port c pin assignment, 16-494 port c special options, 16-494 port c, 16-492 port d data direction, 16-498 port d data, 16-498 port d pin assignment, 16-499 port d, 16-498 protocol-specific mode, 16-176 real-time clock alarm seconds, 12-20 real-time clock alarm, 12-21 real-time clock status and control, 12-18 real-time clock, 12-19 reset status, 4-5 risc controller configuration, 16-7 risc microcode development support control, 16-7 risc timer event, 16-23 risc timer mask, 16-23 scc hdlc event, 16-250 scc hdlc mask, 16-253 scc hdlc mode, 16-242 scc hdlc status, 16-254 scc uart event, 16-227 scc uart mask, 16-229 scc uart status, 16-230 scc2 infrared serial interaction pulse control, 16-296 scc2 serial infrared mode, 16-294 sccx async hdlc event, 16-284 sccx async hdlc mode, 16-279 sccx ethernet event, 16-346 sccx ethernet mask, 16-348 sccx ethernet mode, 16-337 sccx ethernet status, 16-348 sccx transparent event, 16-314 sccx transparent mask, 16-316 sccx transparent status, 16-316 sdma address, 16-89 sdma configuration, 16-85 sdma mask, 16-88 sdma status, 16-87 sdma, 16-85 serial interface clock route, 16-136 serial interface command, 16-139 serial interface global mode, 16-128 serial interface mode, 16-129 serial interface ram pointer, 16-141 serial interface status, 16-140 siu interrupt edge/level, 12-9 siu interrupt mask, 12-8 siu interrupt pending, 12-7 siu interrupt vector, 12-10 siu module configuration, 12-30 smc gci event, 16-432 smc gci mask, 16-433 smc in gci mode, 16-431 smc transparent event, 16-422 smc transparent mask, 16-423 smc transparent mode, 16-416 smc uart event, 16-405 smc uart mask, 16-407 smc uart mode, 16-398 software service, 12-27 special purpose unsupported registers, 7-6 special-purpose, 6-16 spi command, 16-451 spi event, 16-452 spi mask, 16-453 spi mode, 16-443 system clock and reset control, 5-3 system protection control, 12-35 test access port instruction, 21-19 timebase reference, 12-15 timebase status and control, 12-16 timebase, 12-14 timer capture, 16-80 timer counter, 16-80 timer event, 16-81 timer global configuration, 16-76 , 16-77
index index-26 mpc823e reference manual motorola timer mode, 16-78 timer reference, 16-79 transfer error status, 12-36 transmit-on-demand, 16-177 trap enable control, 20-31 universal serial bus command, 16-372 universal serial bus endpoint configuration, 16- 373 universal serial bus event, 16-376 universal serial bus mask, 16-377 universal serial bus mode, 16-365 universal serial bus slave address, 16-371 video background color buffer, 19-9 video command, 19-8 video controller configuration, 19-5 video frame buffer a start address set 1, 19-14 video frame buffer b start address set 0, 19-12 video frame buffer b start address set 1, 19-15 video frame configuration set 0, 19-10 video frame configuration set 1, 19-13 video status, 19-7 write-protected, 5-27 registers (special) outside of the core encoding, 6-19 requests to initiate a upm cycle exception, 15-43 memory access, 15-42 memory periodic timer, 15-42 software, 15-43 requests to initiate a upm cycle, 15-41 reset configuration hard reset, 4-7 soft reset, 4-12 configuration, 4-7 hard and soft, 6-24 hard reset configuration word, 4-10 instruction cache, 9-14 pcmcia, 17-8 types, 4-2 reset status register key, 5-27 reset status register, 4-5 reset, 4-1 reset, results at, 4-1 resetting the registers and parameters for all the channels, 16-10 resolution, 16-75 restartability (interrupts), 6-10 restrictions on the mpc823, 21-21 retry, 2-3 , 13-5 , 13-42 rfc 1549 exceptions, 16-273 rfi, 16-507 , 16-511 , 16-512 , 16-513 risc microcontroller, 16-4 risc timer event register, 16-23 risc timer initialization example, 16-24 risc timer interrupt example, 16-25 risc timer mask register, 16-23 risc timer table algorithm, 16-25 rmds, 16-7 rs-232 standard, 16-201 rsr, 4-5 rsrk, 5-27 rss (definition), 15-41 rstconf, 2-6 rsv, 2-3 , 13-4 rtc, 12-19 rtcal, 12-21 rtcalk, 5-27 rtck, 5-27 rtcsc, 12-18 rtcsck, 5-27 rter, 16-23 rtmr, 16-23 rts2, 2-10 rts3, 2-10 rtseck, 5-27 rxd, 16-321 rxd2, 2-8 rxd3, 2-9 s s/t (definition), 16-150 scceCasync hdlc, 16-284 scceCethernet, 16-346 scceChdlc, 16-250 scceCtransparent, 16-314 scce-uart, 16-227 sccmCethernet, 16-348 sccmChdlc, 16-253 sccmCtransparent, 16-316 sccm-uart, 16-229 sccr, 5-3 sccrk, 5-27 sccs (definition), 16-163 sccsCethernet, 16-348 sccsChdlc, 16-254 sccsCtransparent, 16-316 sccsCuart, 16-230 sccx and usb priority, 16-502 schematic of the mpc823, 23-3 scit (definition), 16-150 scratchpad, 16-30 sdack1, 2-9 , 2-11 sdack2, 2-10 sdackx, about, 16-90 sdar, 16-89 sdcr, 16-85 sdma (definition), 16-4
index motorola mpc823e reference manual index-27 sdma address register, 16-89 sdma configuration register, 16-85 sdma mask register, 16-34 sdma status register, 16-33 , 16-87 sdma, 16-82 sdmr, 16-34 , 16-88 sdsr, 16-33 , 16-87 selecting a general system clock, 5-17 selecting a machine, 15-4 self-refresh mode, exiting, 15-43 sequence of interrupt detection, 6-14 sequencer unit, of the core, 6-4 serial communication controller 2 memory map, 3-9 serial communication controller 3 memory map, 3-9 serial communication controllers 16-163 appletalk mode connectivity, 16-267 features, 16-266 operation, 16-265 programming, 16-268 , 16-269 appletalk mode, 16-265 async hdlc mode 16-269 commands, 16-277 configuration, 16-276 errors, 16-278 event register (scce-async hdlc), 16- 284 features, 16-269 frame reception, 16-270 frame transmission, 16-269 implementation, 16-273 mode register (psmr-async hdlc), 16- 279 parameter ram memory map, 16-274 programming guide, 16-286 receive buffer descriptor, 16-280 transmit buffer descriptor, 16-282 block diagram, 16-164 buffer descriptors format, 16-179 buffer descriptors, 16-178 clock glitches, 16-197 data synchronization register (dsr), 16-177 digital phase-locked loop, 16-193 disabling on-the-fly, 16-199 ethernet mode 16-318 address recognition, 16-332 collision handling, 16-335 commands, 16-330 configuration, 16-330 connecting to eest, 16-321 errors, 16-336 event register, 16-346 features, 16-319 frame reception, 16-324 frame transmission, 16-323 hash table algorithm, 16-334 interpacket gap time, 16-335 loopback and full-duplex operation, 16- 335 mask register, 16-348 mode register (psmr-ethernet), 16-337 operation, 16-318 parameter ram memory map, 16-326 programming example, 16-348 receive buffer descriptor, 16-340 status register, 16-348 transmit buffer descriptor, 16-343 features, 16-165 general sccx mode high register (gsmr_h), 16-166 general sccx mode low register (gsmr_l), 16-171 hdlc bus controller 16-257 features, 16-259 memory map and programming, 16-264 hdlc mode commands, 16-239 errors, 16-240 event register (scce-hdlc), 16-250 frame reception, 16-235 frame transmission, 16-234 mask register (sccm-hdlc), 16-253 mode register (psmr-hdlc), 16-242 operation, 16-233 programming, 16-238 receive buffer descriptors, 16-244 status register (sccs-hdlc), 16-254 transmit buffer descriptor, 16-248 initialization, 16-188 interrupts, 16-187 irda mode 16-287 data link layer, 16-291 high-speed programming example, 16-300 high-speed, 16-290 infrared interaction pulses, 16-293 infrared serial interaction pulse control register (irsip), 16-296 low-speed programming example, 16-297 low-speed, 16-288 middle-speed programming example, 16- 298
index index-28 mpc823e reference manual motorola middle-speed, 16-289 physical layer, 16-292 programming, 16-294 serial infrared mode register (irmode), 16- 294 irda, 16-198 parameter ram memory map, 16-182 protocol-pecific mode register (psmr), 16-176 protocols, 16-163 switching protocols, 16-200 timing, 16-189 transmit-on-demand register (todr), 16-177 transparent mode 16-301 commands, 16-307 errors, 16-309 event register (scce-transparent), 16-314 examples, 16-317 features, 16-302 frame reception, 16-303 frame transmission, 16-302 mask register (sccm-transparent), 16-316 operation, 16-301 parameter ram memory map, 16-307 receive buffer descriptors, 16-310 status register (sccs-transparent), 16- 316 synchronization, 16-303 transmit buffer descriptor, 16-312 uart mode break support, 16-211 commands, 16-207 control characters, 16-209 errors, 16-214 features, 16-202 fractional stop bits, 16-213 parameter ram memory map, 16-204 programming example, 16-230 , 16-232 programming, 16-206 recognizing addresses, 16-208 scc uart event register (scce-uart), 16-227 scc uart mask register (sccm-uart), 16-229 scc uart status register (sccs-uart), 16-230 sending a break, 16-212 sending a preamble, 16-212 transmit buffer descriptors, 16-224 wake-up timer, 16-211 uart mode, 16-201 serial dma, 16-82 serial interface 16-112 block diagram, 16-113 change requirements, 16-125 clock route registe (sicr), 16-136 command register (sicmr), 16-139 global mode register (sigmr), 16-128 memory map, 3-11 mode register (simode), 16-129 nmsi features, 16-114 programming ram entries, 16-122 ram modes, 16-125 ram operation, 16-117 ram pointer register (sirp), 16-141 status register (sistr), 16-140 testing modes, 16-115 time-slot assigner features, 16-114 serial management controllers 16-382 buffer descriptors operation, 16-384 disabling on-the-fly, 16-390 features, 16-384 gci mode 16-425 c/i channel handling, 16-426 c/i channel reception, 16-426 c/i channel transmission, 16-426 commands, 16-430 event register (smce-gci), 16-432 features, 16-425 mask register (smcm-gci), 16-433 mode register (smcmr-gci), 16-431 monitor channel reception, 16-426 monitor channel transmission, 16-426 operation, 16-426 parameter ram memory map, 16-427 general parameter ram memory map, 16-385 general smc mode register (smcmr), 16-384 memory map, 3-10 parameter ram memory map, 16-385 transparent mode 16-409 commands, 16-415 errors, 16-416 event register (smce-transparent), 16- 422 features, 16-409 frame reception, 16-410 frame transmission, 16-409 interrupts, 16-425 mask register (smcm-transparent), 16- 423 mode register (smcmr-transparent), 16- 416 nmsi programming example, 16-423 parameter ram memory map, 16-415 receive buffer descriptor, 16-418
index motorola mpc823e reference manual index-29 synchronization with smsynx, 16-411 synchronization with the tsa, 16-413 transmit buffer descriptor, 16-420 tsa programming example, 16-424 uart mode commands, 16-396 errors, 16-397 event register (smce-uart), 16-405 features, 16-393 frame reception, 16-394 frame transmission, 16-393 interrupts, 16-408 mask register (smcm-uart), 16-407 mode register (smcmr-uart), 16-398 parameter ram memory map, 16-394 programming example, 16-407 programming, 16-395 receive buffer descriptors, 16-399 sending a break, 16-396 sending a preamble, 16-397 transmit buffer descriptor, 16-403 uart mode, 16-392 unsupported features, 16-392 serial peripheral interface 16-433 buffer descriptor ring, 16-442 command register (spcom), 16-451 commands, 16-441 event register (spie), 16-452 interrupts, 16-455 mask register (spim), 16-453 master programming example, 16-453 memory map, 3-11 mode register (spmode), 16-443 operation multimaster, 16-437 operation, 16-435 parameter ram memory map, 16-438 programming, 16-443 receive buffer descriptor, 16-447 slave programming example, 16-454 transmission and reception, 16-436 transmit buffer descriptor, 16-449 serialization latency, 6-12 serialization, 6-12 set timer command, 16-22 setup token, 16-357 shift/clk/clk, 2-12 show cycles (definition), 13-33 sicmr, 16-139 sicr, 16-136 siel, 12-9 sigmr, 16-128 signal timings, generating, 15-43 signals a, 17-3 ale_b, 2-7 , 17-4 as, 2-6 at0, 2-8 at1, 2-7 at2, 2-7 at3, 2-8 bb, 2-4 bdip, 2-2 bg, 2-4 bi, 2-3 blank, 2-12 bpl_b1, 2-5 br, 2-4 brgo1, 2-8 , 2-9 brgo2, 2-9 brgo3, 2-9 brgout2, 2-9 bs_b0, 2-5 bs_b1, 2-5 bs_b2, 2-5 bs_b3, 2-5 bsy_b, 17-6 burst, 2-2 bus interface, 13-4 bvd2_b, 17-5 cd2, 2-10 cd3, 2-11 cdx_b, 17-5 ce1_b, 2-4 ce2_b, 2-5 cex_b, 17-3 clk, 2-12 clk1, 2-8 clk2, 2-8 clk3, 2-9 clk4, 2-9 clkout, 2-6 cs2, 2-6 cs3, 2-6 cs6, 2-4 cs7, 2-5 cts2, 2-10 cts3, 2-9 , 2-11 d, 17-4 dp0, 2-3 dp1, 2-3 dp2, 2-4 dp3, 2-4 dreq1, 2-10 dreq2, 2-10 dsck, 2-12 dsck/at1, 2-7 dsdi, 2-12
index index-30 mpc823e reference manual motorola dsdo, 2-8 , 2-12 extal, 2-6 extclk, 2-6 field, 2-11 frame, 2-12 frz, 2-4 general circuit interface, 16-150 gnd, 2-12 gpl_a0, 2-5 gpl_a1, 2-5 gpl_a4, 2-6 gpl_a5, 2-6 gpl_b0, 2-5 gpl_b4, 2-6 gpl_b5, 2-2 hreset, 2-6 hsync, 2-12 i2cscl, 2-9 i2csda, 2-9 idl bus, 16-147 idma interface, 16-90 internal clock, 5-16 iois16, 17-4 iois16_b, 2-7 iord, 2-5 iord_b, 17-4 iowr, 2-5 iowr_b, 17-4 ip_b0, 2-7 ip_b1, 2-7 ip_b2, 2-7 ip_b3, 2-7 ip_b4, 2-7 ip_b5, 2-7 , 2-8 ip_b7, 2-8 ireq_b, 17-6 irq, 17-6 irq0, 2-4 irq1, 2-4 irq2, 2-3 irq3, 2-3 irq4, 2-3 irq5, 2-4 irq6, 2-4 irq7, 2-4 iwp0, 2-7 iwp1, 2-7 iwp2, 2-7 kapwr, 2-12 kr, 2-3 l1rclka, 2-8 l1rclkb, 2-8 l1rqa, 2-10 l1rsynca, 2-11 l1rsyncb, 2-10 l1rxda, 2-8 l1rxdb, 2-9 l1st1, 2-10 l1st2, 2-10 l1st3, 2-10 l1st4, 2-10 l1st5, 2-10 l1st6, 2-10 l1st7, 2-10 l1st8, 2-10 l1tclka, 2-9 l1tclkb, 2-9 l1tsynca, 2-11 l1tsyncb, 2-9 l1txda, 2-8 l1txdb, 2-10 lcd_a, 2-9 lcd_ac, 2-12 lcd_b, 2-10 lcd_c, 2-10 ld0, 2-11 ld1, 2-11 ld2, 2-11 ld3, 2-11 ld4, 2-11 ld5, 2-11 ld6, 2-11 ld7, 2-11 ld8, 2-11 load, 2-12 loe, 2-12 lwp0, 2-7 lwp1, 2-7 , 2-8 modck1, 2-8 modck2, 2-8 n/c, 2-12 oe, 2-5 oe_b, 17-4 op3, 2-8 pcmcia, 17-3 pcoe, 2-5 pcwe, 2-5 poe_b, 17-6 poreset, 2-6 power supply, 2-12 ptr, 2-8 r/w, 17-4 rd/wr, 2-2 rdy, 17-6 reg, 2-2 , 17-3 reset_b, 17-6 retry, 2-3 rstconf, 2-6 rsv, 2-3 rts2, 2-10
index motorola mpc823e reference manual index-31 rts3, 2-10 rxd2, 2-8 rxd3, 2-9 sdack1, 2-9 , 2-11 sdack2, 2-10 shift/clk/clk, 2-12 smrxd1, 2-9 smrxd2, 2-8 smsyn1, 2-9 smsyn2, 2-10 smtxd1, 2-9 smtxd2, 2-8 spiclk, 2-9 spimiso, 2-9 spimosi, 2-9 spisel, 2-9 spkr, 17-6 spkrout, 2-3 , 17-6 sreset, 2-6 sts, 2-8 stschg, 17-5 ta, 2-3 tck, 2-12 , 21-2 tdi, 2-12 , 21-2 tdo, 2-12 , 21-2 tea, 2-3 texp, 2-7 tgate1, 2-10 tgate2, 2-10 tin1, 2-8 tin2, 2-9 tin3, 2-8 tin4, 2-9 tms, 2-12 , 21-2 tout1, 2-8 tout2, 2-9 trst, 2-12 , 21-2 ts, 2-2 tsiz0, 2-2 tsiz1, 2-2 txd2, 2-8 txd3, 2-9 upwaita, 2-6 upwaitb, 2-6 usboe, 2-8 usbrxd, 2-8 usbrxn, 2-10 usbrxp, 2-10 usbtxn, 2-11 usbtxp, 2-11 vd0, 2-11 vd1, 2-11 vd2, 2-11 vd3, 2-11 vd4, 2-11 vd5, 2-11 vd6, 2-11 vd7, 2-11 vddh, 2-12 vddl, 2-12 vddsyn, 2-12 vf0, 2-7 vf1, 2-7 vf2, 2-7 vfls0, 2-7 vfls1, 2-7 vsssyn, 2-12 vsssyn1, 2-12 vsx_b, 17-5 vsync, 2-12 , 20-3 wait_b, 2-7 , 17-4 we_b, 17-4 we0, 2-5 we1, 2-5 we2, 2-5 we3, 2-5 wp, 17-5 xfc, 2-6 xtal, 2-6 signals, 2-2 simask, 12-8 simode, 16-129 single beat transfers read, 13-9 write, 13-12 single beat transfers, 13-8 sipend, 12-7 sirp, 16-141 sistr, 16-140 siu interrupt edge/level register, 12-9 siu interrupt mask register, 12-8 siu interrupt pending register, 12-7 siu interrupt vector register, 12-10 siu module configuration register, 12-30 siumcr, 12-30 sivec, 12-10 slave, 16-435 smc (definition), 16-382 smceCgci, 16-432 smceCtransparent, 16-422 smceCuart, 16-405 smcmCgci, 16-433 smcmr, 16-384 smcmr-gci, 16-431 smcmrCtransparent, 16-416 smcmrCuart, 16-398 smcmCtransparent, 16-423 smcmCuart, 16-407 smrxd1, 2-9 smrxd2, 2-8
index index-32 mpc823e reference manual motorola smsyn1, 2-9 smsyn2, 2-10 smtxd1, 2-9 smtxd2, 2-8 soft reset configuration, 4-12 soft reset, registers affected, 6-24 software monitor debugger, 20-40 software request, initiating, 15-43 software service register, 12-27 software tablewalk routine, minimizing, 11-9 software watchdog timer block diagram, 12-27 software watchdog timer, 12-26 spcom, 16-451 specialized ram memory map, 3-11 specifications (electrical), 22-1 spi (definition), 16-433 spiclk, 2-9 spie, 16-452 spim, 16-453 spimiso, 2-9 spimosi, 2-9 spisel, 2-9 spkrout, 2-3 spll operation, 5-12 spll, 5-1 spmode, 16-443 sram interface, 15-38 sreset, 2-6 , 4-3 srr0, 6-16 , 7-9 srr1, 6-16 , 7-9 stability, spll, 5-13 start address, locating, 15-54 start addresses, 15-54 start of frame token, 16-358 static branch prediction, 6-6 status, of the master, 13-33 storage reservation, 13-38 store (instruction), 10-12 store, 11-48 strobes, 16-115 sts, 2-8 , 13-5 , 13-33 stwcx conditions, 13-40 failure, 13-41 stwcx, 13-5 , 13-38 swsr, 12-27 swt, 12-26 sync, 10-13 synchronization in sccx transparent mode, 16-303 patterns, 16-304 signals, 16-305 the trace window to internal core events, 20-6 transparent example, 16-306 synchronization clock frequency, 5-20 synchronous bus masters, 15-65 , 15-68 synchronous mode, 16-203 sypcr, 12-35 system (definition), 14-1 system clock and reset control register, 5-3 system clock control key, 5-27 system configuration (illustration), 12-4 system design, 1-12 system integration timers memory map, 3-3 system interface unit bus monitor, 12-11 configuration, 12-2 features, 12-2 freeze operation, 12-28 interrupts programming, 12-7 source priority, 12-6 structure, 12-5 interrupts, 12-5 memory map, 3-1 periodic interrupt timer, 12-22 pin multiplexing, 12-29 powerpc decrementer, 12-12 powerpc timebase, 12-14 programming decrementer register, 12-13 programming, 12-30 real-time clock, 12-17 software watchdog timer, 12-26 system configuration and protection registers, 12-30 system interface unit, 12-1 system phase-locked loop, 5-1 system protection control register, 12-35 system protection, 15-5 system reset interrupt, 6-24 system reset, vccout, 5-17 t ta not asserting, 13-41 ta, 2-3 , 13-6 , 13-36 , 15-64 tablewalk operation, 11-49 tablewalk, 11-5 tap (definition), 21-1 tb, 12-14 tbk, 5-27 tbreff0k, 5-27 tbreff1k, 5-27 tbrefl, 12-15 tbrefu, 12-15 tbscr, 12-16 tbscrk, 5-27 tck, 2-12 tclk, 16-321
index motorola mpc823e reference manual index-33 tcnx, 16-80 tcrx, 16-80 tdi, 2-12 tdm (definition), 16-112 tdm channel routing, 16-117 tdo, 2-12 tea assertion, not occurring, 15-16 tea, 2-3 , 13-6 , 13-36 tecr, 20-31 termination localtalk frame, 16-265 termination control of a bus cycle error, 13-42 termination signals, 13-37 terminology, 24-1 terx, 16-81 tesr, 12-36 test access port 21-1 block diagram, 21-2 boundary scan bit order, 21-6 boundary scan register, 21-4 instruction register, 21-19 instructions bypass, 21-20 clamp, 21-20 extest, 21-19 hi-z, 21-20 sample/preload, 21-20 restrictions, 21-21 tap controller, 21-3 texp, 2-7 tgate1, 2-10 tgate2, 2-10 tgcrx, 16-77 timebase and decrementer register key, 5-27 timebase reference register 0 key, 5-27 timebase reference register 1 key, 5-27 timebase reference registers, 12-15 timebase register mapping, 6-16 timebase register, 12-14 timebase status and control register key, 5-27 timebase status and control register, 12-16 timebase, 12-14 time-fill, 16-273 timer capture registers (tcrx), 16-80 timer counter registers (tcnx), 16-80 timer event registers (terx), 16-81 timer global configuration register (tgcrx), 16-77 timer global configuration register, 16-76 timer mode registers (tmrx), 16-78 timer reference registers (trrx), 16-79 timers key memory map, 3-4 memory map, 3-7 timers, 16-74 time-slot assigner configuration, 16-114 connections, 16-117 features, 16-114 timing bus arbitration (illustration), 13-30 sccx, 16-189 timing, instruction cycles, 8-1 timing, single buffer, 16-110 tin1, 2-8 tin2, 2-9 tin3, 2-8 tin4, 2-9 tlb manipulation loading the reserved tlb entries, 11-51 tlb invalidation, 11-51 tlb replacement counter, 11-51 tlbia, 11-15 tlbie, 11-15 tmrx, 16-78 tms, 2-12 tokens in, 16-357 pre, 16-358 setup, 16-357 sof, 16-358 tout1, 2-8 tout2, 2-9 tracking microcontroller loading, 16-25 transfer error status register, 12-36 transfer start, 13-31 transfers on the bus alignment and packaging, 13-25 basic, 13-8 burst, 13-16 read bytes, 13-26 single beat, 13-8 write patterns, 13-27 transfers, burst-inhibited, 13-16 translation table structure, 11-5 transparency decoding, receiver, 16-271 transparency encoding, transmitter, 16-271 transparent mode sccx, 16-301 trrx, 16-79 trst, 2-12 ts, 2-2 , 13-5 tsa (definition), 16-112 tsiz, 13-33 tsiz0, 2-2 tsiz1, 2-2 txd, 16-321 txd2, 2-8
index index-34 mpc823e reference manual motorola txd3, 2-9 types of watchpoints and breakpoints, 20-11 u uart character format, 16-201 uart (definition), 16-201 uart mode sccx, 16-201 smc, 16-392 universal serial bus 16-350 buffer descriptors receive, 16-366 ring, 16-374 transmit, 16-369 command register (uscom), 16-372 commands, 16-363 endpoint configuration registers (usepx), 16- 373 endpoint parameters, 16-360 errors, 16-364 event register (usber), 16-376 features, 16-352 host controller limitations, 16-352 initialization example, 16-378 , 16-380 mask register (usbmr), 16-377 memory map, 3-8 mode register (usmod), 16-365 modes, 16-355 operation, 16-350 , 16-353 parameter ram memory map, 16-358 programming, 16-365 slave address register (usadr), 16-371 status register (usbs), 16-377 tokens, 16-356 transmission and reception, 16-355 upm holding in a particular state, 15-65 upm (definition), 15-40 upm cycle, initiating, 15-40 upm locations addressed, 15-41 upm routine execution, 15-17 upwaita, 2-6 upwaitb, 2-6 usadr, 16-371 usb (definition), 16-350 usb and sccx priority, 16-502 usber, 16-376 usbmr, 16-377 usboe, 2-8 usbrxd, 2-8 usbrxn, 2-10 usbrxp, 2-10 usbs, 16-377 usbtxn, 2-11 usbtxp, 2-11 uscom, 16-372 usep, 16-373 user-programmable machines block diagram, 15-40 programming, 15-43 ram array, 15-48 ram word, 15-49 requests exception, 15-43 memory access, 15-42 memory periodic timer, 15-42 software, 15-43 requests, 15-41 wait mechanism, 15-65 user-programmable machines, 15-40 using a low frequency crystal circuitry, 5-10 usmod, 16-365 v vbcb, 19-9 vccr, 19-5 vcmr, 19-8 vd0, 2-11 vd1, 2-11 vd2, 2-11 vd3, 2-11 vd4, 2-11 vd5, 2-11 vd6, 2-11 vd7, 2-11 vddh, 2-12 vddl, 2-12 vddsyn, 2-12 , 5-23 vertical sync, 18-5 vf instruction type encoding, 20-4 vf0, 2-7 vf1, 2-7 vf2, 2-7 vfaa0, 19-11 vfaa1, 19-14 vfba0, 19-12 vfba1, 19-15 vfcr0, 19-10 vfcr1, 19-13 vfls0, 2-7 vfls1, 2-7 video background color buffer register, 19-9 video command register, 19-8 video controller block diagram, 19-3
index motorola mpc823e reference manual index-35 clock, 19-3 features, 19-2 fifo and dma control, 19-4 image sizes, 19-4 memory map, 3-4 operation, 19-2 programming examples ntsc, 19-20 pal, 19-24 programming examples, 19-19 ram array format, 19-17 ram array, 19-16 registers 19-5 background color buffer register (vbcb), 19-9 command register (vcmr), 19-8 configuration register (vccr), 19-5 frame buffer a start address register set 0 (vfaa0), 19-11 frame buffer a start address set 1 (vfaa1), 19-14 frame buffer b start address register set 0 (vfba0), 19-12 frame buffer b start address register set 1 (vfba1), 19-15 frame configuration register set 0 (vfcr0), 19-10 frame configuration set 1 (vfcr1), 19-13 status register (vsr), 19-7 switching image sizes, 19-4 video controller configuration register, 19-5 video frame buffer a start address register set 0, 19- 11 video frame buffer a start address register set 1, 19- 14 video frame buffer b start address register set 0, 19- 12 video frame buffer b start address register set 1, 19- 15 video frame configuration register set 0, 19-10 video frame configuration register set 1, 19-13 video status register, 19-7 video system (illustration), 19-1 voltage failure, 4-2 vsr, 19-7 vsssyn, 2-12 , 5-23 vsssyn1, 2-12 , 5-23 vsync, 2-12 w wadd applications, 16-73 coefficients and sample data buffers, 16-71 function descriptor, 16-71 parameter packet, 16-72 wadd, 16-70 wait mechanism, 15-65 wait state configuration, 15-34 wait state, exiting, 15-66 wait_b, 2-7 wake-up timer, 16-211 watchpoints, 6-5 , 20-9 wbs (definition), 15-41 we0, 2-5 we1, 2-5 we2, 2-5 we3, 2-5 window trace, 20-6 write protection, 15-37 write-protect error, 15-15 write-protect violations, 15-7 write-protecting registers, 5-27 writethrough mode, 10-12 writethrough, 11-4 wss (definition), 15-41 x xer, 6-16 , 6-23 xfc, 2-6 , 5-23 xoff, 16-209 , 16-232 xon, 16-209 , 16-232 xtal, 2-6


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